SparcDisassembler.cpp Source File (original) (raw)

25using namespace llvm;

28#define DEBUG_TYPE "sparc-disassembler"

32namespace {

36public:

39 ~SparcDisassembler() override = default;

44};

45}

50 return new SparcDisassembler(STI, Ctx);

51}

66 SP::G0, SP::G1, SP::G2, SP::G3,

67 SP::G4, SP::G5, SP::G6, SP::G7,

68 SP::O0, SP::O1, SP::O2, SP::O3,

69 SP::O4, SP::O5, SP::O6, SP::O7,

70 SP::L0, SP::L1, SP::L2, SP::L3,

71 SP::L4, SP::L5, SP::L6, SP::L7,

72 SP::I0, SP::I1, SP::I2, SP::I3,

73 SP::I4, SP::I5, SP::I6, SP::I7 };

76 SP::F0, SP::F1, SP::F2, SP::F3,

77 SP::F4, SP::F5, SP::F6, SP::F7,

78 SP::F8, SP::F9, SP::F10, SP::F11,

79 SP::F12, SP::F13, SP::F14, SP::F15,

80 SP::F16, SP::F17, SP::F18, SP::F19,

81 SP::F20, SP::F21, SP::F22, SP::F23,

82 SP::F24, SP::F25, SP::F26, SP::F27,

83 SP::F28, SP::F29, SP::F30, SP::F31 };

86 SP::D0, SP::D16, SP::D1, SP::D17,

87 SP::D2, SP::D18, SP::D3, SP::D19,

88 SP::D4, SP::D20, SP::D5, SP::D21,

89 SP::D6, SP::D22, SP::D7, SP::D23,

90 SP::D8, SP::D24, SP::D9, SP::D25,

91 SP::D10, SP::D26, SP::D11, SP::D27,

92 SP::D12, SP::D28, SP::D13, SP::D29,

93 SP::D14, SP::D30, SP::D15, SP::D31 };

96 SP::Q0, SP::Q8, ~0U, ~0U,

97 SP::Q1, SP::Q9, ~0U, ~0U,

98 SP::Q2, SP::Q10, ~0U, ~0U,

99 SP::Q3, SP::Q11, ~0U, ~0U,

100 SP::Q4, SP::Q12, ~0U, ~0U,

101 SP::Q5, SP::Q13, ~0U, ~0U,

102 SP::Q6, SP::Q14, ~0U, ~0U,

103 SP::Q7, SP::Q15, ~0U, ~0U } ;

104

106 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };

107

109 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6,

110 SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13,

111 SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20,

112 SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,

113 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};

114

116 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK,

117 SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP,

118 SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE};

119

121 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,

122 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,

123 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,

124 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,

125};

126

128 SP::C0, SP::C1, SP::C2, SP::C3,

129 SP::C4, SP::C5, SP::C6, SP::C7,

130 SP::C8, SP::C9, SP::C10, SP::C11,

131 SP::C12, SP::C13, SP::C14, SP::C15,

132 SP::C16, SP::C17, SP::C18, SP::C19,

133 SP::C20, SP::C21, SP::C22, SP::C23,

134 SP::C24, SP::C25, SP::C26, SP::C27,

135 SP::C28, SP::C29, SP::C30, SP::C31

136};

137

139 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,

140 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,

141 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,

142 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31

143};

144

145

155

161

171

181

187

189 if (Reg == ~0U)

193}

194

204

213

222

231

236

237 if ((RegNo & 1))

239

240 RegNo = RegNo / 2;

243

246 return S;

247}

248

252 RegNo = RegNo / 2;

255

259}

260

268

277

284

291

292template

295 int64_t BranchOffset = SignExtend64(ImmVal, N) * 4;

297 Decoder))

300}

301

302#include "SparcGenDisassemblerTables.inc"

303

304

307 bool IsLittleEndian) {

308

309 if (Bytes.size() < 4) {

312 }

313

318}

319

324 uint32_t Insn;

325 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();

330

331

332

333 if (STI.hasFeature(Sparc::FeatureV9))

334 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address,

335 this, STI);

336 else

337 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);

338

341

343 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);

344

346}

MCDisassembler::DecodeStatus DecodeStatus

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

#define LLVM_EXTERNAL_VISIBILITY

static bool isBranch(unsigned Opcode)

static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:162

static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:223

static constexpr unsigned FCCRegDecoderTable[]

Definition SparcDisassembler.cpp:105

static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:269

static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:172

static DecodeStatus DecodeDisp(MCInst &MI, uint32_t ImmVal, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:293

static constexpr unsigned QFPRegDecoderTable[]

Definition SparcDisassembler.cpp:95

static MCDisassembler * createSparcDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition SparcDisassembler.cpp:47

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcDisassembler()

Definition SparcDisassembler.cpp:54

static DecodeStatus DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:250

static DecodeStatus DecodeSIMM5(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:278

static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:232

static constexpr unsigned CPRegDecoderTable[]

Definition SparcDisassembler.cpp:127

static constexpr uint16_t CPPairDecoderTable[]

Definition SparcDisassembler.cpp:138

static constexpr unsigned PRRegDecoderTable[]

Definition SparcDisassembler.cpp:115

static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:285

static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian)

Read four bytes from the ArrayRef and return 32 bit word.

Definition SparcDisassembler.cpp:305

static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:205

static DecodeStatus DecodeCoprocRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:196

static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:146

static constexpr uint16_t IntPairDecoderTable[]

Definition SparcDisassembler.cpp:120

static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:261

static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:156

static constexpr unsigned IntRegDecoderTable[]

Definition SparcDisassembler.cpp:65

static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:214

static constexpr unsigned DFPRegDecoderTable[]

Definition SparcDisassembler.cpp:85

static constexpr unsigned FPRegDecoderTable[]

Definition SparcDisassembler.cpp:75

static constexpr unsigned ASRRegDecoderTable[]

Definition SparcDisassembler.cpp:108

static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition SparcDisassembler.cpp:182

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Generic base class for all target subtargets.

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)

Context & getContext() const

value_type read(const void *memory, endianness endian)

Read a value of a particular endianness from memory.

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheSparcTarget()

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

Target & getTheSparcV9Target()

Target & getTheSparcelTarget()

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.