LLVM: lib/Target/Sparc/Disassembler/SparcDisassembler.cpp File Reference (original) (raw)

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◆ DEBUG_TYPE

#define DEBUG_TYPE "sparc-disassembler"

◆ createSparcDisassembler()

◆ DecodeASRRegsRegisterClass()

◆ DecodeCall()

◆ DecodeCoprocPairRegisterClass()

◆ DecodeCoprocRegsRegisterClass()

◆ DecodeDFPRegsRegisterClass()

◆ DecodeDisp()

◆ DecodeFCCRegsRegisterClass()

◆ DecodeFPRegsRegisterClass()

◆ DecodeI64RegsRegisterClass()

◆ DecodeIntPairRegisterClass()

◆ DecodeIntRegsRegisterClass()

◆ DecodePRRegsRegisterClass()

◆ DecodeQFPRegsRegisterClass()

◆ DecodeSIMM13()

◆ DecodeSIMM5()

◆ LLVMInitializeSparcDisassembler()

◆ readInstruction32()

◆ tryAddingSymbolicOperand()

◆ ASRRegDecoderTable

Initial value:

= {

SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6,

SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13,

SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20,

SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,

SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}

Definition at line 108 of file SparcDisassembler.cpp.

Referenced by DecodeASRRegsRegisterClass().

◆ CPPairDecoderTable

Initial value:

= {

SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,

SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,

SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,

SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31

}

Definition at line 138 of file SparcDisassembler.cpp.

Referenced by DecodeCoprocPairRegisterClass().

◆ CPRegDecoderTable

Initial value:

= {

SP::C0, SP::C1, SP::C2, SP::C3,

SP::C4, SP::C5, SP::C6, SP::C7,

SP::C8, SP::C9, SP::C10, SP::C11,

SP::C12, SP::C13, SP::C14, SP::C15,

SP::C16, SP::C17, SP::C18, SP::C19,

SP::C20, SP::C21, SP::C22, SP::C23,

SP::C24, SP::C25, SP::C26, SP::C27,

SP::C28, SP::C29, SP::C30, SP::C31

}

Definition at line 127 of file SparcDisassembler.cpp.

Referenced by DecodeCoprocRegsRegisterClass().

◆ DFPRegDecoderTable

Initial value:

= {

SP::D0, SP::D16, SP::D1, SP::D17,

SP::D2, SP::D18, SP::D3, SP::D19,

SP::D4, SP::D20, SP::D5, SP::D21,

SP::D6, SP::D22, SP::D7, SP::D23,

SP::D8, SP::D24, SP::D9, SP::D25,

SP::D10, SP::D26, SP::D11, SP::D27,

SP::D12, SP::D28, SP::D13, SP::D29,

SP::D14, SP::D30, SP::D15, SP::D31 }

Definition at line 85 of file SparcDisassembler.cpp.

Referenced by DecodeDFPRegsRegisterClass().

◆ FCCRegDecoderTable

◆ FPRegDecoderTable

Initial value:

= {

SP::F0, SP::F1, SP::F2, SP::F3,

SP::F4, SP::F5, SP::F6, SP::F7,

SP::F8, SP::F9, SP::F10, SP::F11,

SP::F12, SP::F13, SP::F14, SP::F15,

SP::F16, SP::F17, SP::F18, SP::F19,

SP::F20, SP::F21, SP::F22, SP::F23,

SP::F24, SP::F25, SP::F26, SP::F27,

SP::F28, SP::F29, SP::F30, SP::F31 }

Definition at line 75 of file SparcDisassembler.cpp.

Referenced by DecodeFPRegsRegisterClass().

◆ IntPairDecoderTable

Initial value:

= {

SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,

SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,

SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,

SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,

}

Definition at line 120 of file SparcDisassembler.cpp.

Referenced by DecodeIntPairRegisterClass().

◆ IntRegDecoderTable

Initial value:

= {

SP::G0, SP::G1, SP::G2, SP::G3,

SP::G4, SP::G5, SP::G6, SP::G7,

SP::O0, SP::O1, SP::O2, SP::O3,

SP::O4, SP::O5, SP::O6, SP::O7,

SP::L0, SP::L1, SP::L2, SP::L3,

SP::L4, SP::L5, SP::L6, SP::L7,

SP::I0, SP::I1, SP::I2, SP::I3,

SP::I4, SP::I5, SP::I6, SP::I7 }

Definition at line 65 of file SparcDisassembler.cpp.

Referenced by DecodeIntRegsRegisterClass(), and DecodeIntRegsRegisterClass().

◆ PRRegDecoderTable

Initial value:

= {

SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK,

SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP,

SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE}

Definition at line 115 of file SparcDisassembler.cpp.

Referenced by DecodePRRegsRegisterClass().

◆ QFPRegDecoderTable

Initial value:

= {

SP::Q0, SP::Q8, ~0U, ~0U,

SP::Q1, SP::Q9, ~0U, ~0U,

SP::Q2, SP::Q10, ~0U, ~0U,

SP::Q3, SP::Q11, ~0U, ~0U,

SP::Q4, SP::Q12, ~0U, ~0U,

SP::Q5, SP::Q13, ~0U, ~0U,

SP::Q6, SP::Q14, ~0U, ~0U,

SP::Q7, SP::Q15, ~0U, ~0U }

Definition at line 95 of file SparcDisassembler.cpp.

Referenced by DecodeQFPRegsRegisterClass().