SparcInstPrinter.cpp Source File (original) (raw)

21using namespace llvm;

23#define DEBUG_TYPE "asm-printer"

27namespace llvm {

29 using namespace SP;

30}

31}

33#define GET_INSTRUCTION_NAME

34#define PRINT_ALIAS_INSTR

35#include "SparcGenAsmWriter.inc"

38 return (STI.hasFeature(Sparc::FeatureV9)) != 0;

39}

46 unsigned AltIdx) const {

48}

62 switch (MI->getOpcode()) {

63 default: return false;

64 case SP::JMPLrr:

65 case SP::JMPLri: {

66 if (MI->getNumOperands() != 3)

67 return false;

68 if (->getOperand(0).isReg())

69 return false;

70 switch (MI->getOperand(0).getReg().id()) {

71 default: return false;

72 case SP::G0:

73 if (MI->getOperand(2).isImm() &&

74 MI->getOperand(2).getImm() == 8) {

75 switch (MI->getOperand(1).getReg().id()) {

76 default: break;

77 case SP::I7: O << "\tret"; return true;

78 case SP::O7: O << "\tretl"; return true;

79 }

80 }

82 return true;

83 case SP::O7:

85 return true;

86 }

87 }

88 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ:

89 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {

91 || (MI->getNumOperands() != 3)

92 || (->getOperand(0).isReg())

93 || (MI->getOperand(0).getReg() != SP::FCC0))

94 return false;

96 switch(MI->getOpcode()) {

97 default:

98 case SP::V9FCMPS: O << "\tfcmps "; break;

99 case SP::V9FCMPD: O << "\tfcmpd "; break;

100 case SP::V9FCMPQ: O << "\tfcmpq "; break;

101 case SP::V9FCMPES: O << "\tfcmpes "; break;

102 case SP::V9FCMPED: O << "\tfcmped "; break;

103 case SP::V9FCMPEQ: O << "\tfcmpeq "; break;

104 }

106 O << ", ";

108 return true;

109 }

110 }

111}

112

116 const MCOperand &MO = MI->getOperand (opNum);

117

118 if (MO.isReg()) {

120 if (isV9(STI))

122 else

124 return ;

125 }

126

127 if (MO.isImm()) {

128 switch (MI->getOpcode()) {

129 default:

131 return;

132

133 case SP::TICCri:

134 case SP::TICCrr:

135 case SP::TRAPri:

136 case SP::TRAPrr:

137 case SP::TXCCri:

138 case SP::TXCCrr:

139

140 O << ((int) MO.getImm() & 0x7f);

141 return;

142 }

143 }

144

145 assert(MO.isExpr() && "Unknown operand kind in printOperand");

147}

148

152 const MCOperand &Op1 = MI->getOperand(opNum);

153 const MCOperand &Op2 = MI->getOperand(opNum + 1);

154

155 bool PrintedFirstOperand = false;

156 if (Op1.isReg() && Op1.getReg() != SP::G0) {

158 PrintedFirstOperand = true;

159 }

160

161

162

163 const bool SkipSecondOperand =

164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) ||

166

167 if (!SkipSecondOperand) {

168 if (PrintedFirstOperand)

169 O << '+';

171 }

172}

173

177 int CC = (int)MI->getOperand(opNum).getImm();

178 switch (MI->getOpcode()) {

179 default: break;

180 case SP::FBCOND:

181 case SP::FBCONDA:

182 case SP::FBCOND_V9:

183 case SP::FBCONDA_V9:

184 case SP::BPFCC:

185 case SP::BPFCCA:

186 case SP::BPFCCNT:

187 case SP::BPFCCANT:

188 case SP::MOVFCCrr: case SP::V9MOVFCCrr:

189 case SP::MOVFCCri: case SP::V9MOVFCCri:

190 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:

191 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:

192 case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:

193

195 break;

196 case SP::CPBCOND:

197 case SP::CPBCONDA:

198

200 break;

201 case SP::BPR:

202 case SP::BPRA:

203 case SP::BPRNT:

204 case SP::BPRANT:

205 case SP::MOVRri:

206 case SP::MOVRrr:

207 case SP::FMOVRS:

208 case SP::FMOVRD:

209 case SP::FMOVRQ:

210

212 break;

213 }

215}

216

220 llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");

221 return true;

222}

223

227 static const char *const TagNames[] = {

228 "#LoadLoad", "#StoreLoad", "#LoadStore", "#StoreStore",

229 "#Lookaside", "#MemIssue", "#Sync"};

230

231 unsigned Imm = MI->getOperand(opNum).getImm();

232

233 if (Imm > 127) {

234 O << Imm;

235 return;

236 }

237

238 bool First = true;

239 for (unsigned i = 0; i < std::size(TagNames); i++) {

240 if (Imm & (1 << i)) {

241 O << (First ? "" : " | ") << TagNames[i];

243 }

244 }

245}

246

249 unsigned Imm = MI->getOperand(opNum).getImm();

250 auto ASITag = SparcASITag::lookupASITagByEncoding(Imm);

251 if (isV9(STI) && ASITag)

252 O << '#' << ASITag->Name;

253 else

254 O << Imm;

255}

256

260 unsigned Imm = MI->getOperand(opNum).getImm();

261 auto PrefetchTag = SparcPrefetchTag::lookupPrefetchTagByEncoding(Imm);

262 if (PrefetchTag)

263 O << '#' << PrefetchTag->Name;

264 else

265 O << Imm;

266}

267

272

273

274

275 if (Op.isImm()) {

276 int64_t Offset = Op.getImm();

280 Target &= 0xffffffff;

282 } else {

283 O << ".";

285 O << "+";

287 }

288 return;

289 }

290

291

292 MAI.printExpr(O, *Op.getExpr());

293}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

WithMarkup markup(raw_ostream &OS, Markup M)

format_object< int64_t > formatHex(int64_t Value) const

void printAnnotation(raw_ostream &OS, StringRef Annot)

Utility function for printing annotations.

format_object< int64_t > formatImm(int64_t Value) const

Utility function to print immediates in decimal or hex.

bool PrintBranchImmAsAddress

If true, a branch immediate (e.g.

Instances of this class represent a single low-level machine instruction.

Instances of this class represent operands of the MCInst class.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const Triple & getTargetTriple() const

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override

Print the specified MCInst to the specified raw_ostream.

Definition SparcInstPrinter.cpp:50

bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &OS)

Definition SparcInstPrinter.cpp:113

void printASITag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition SparcInstPrinter.cpp:247

bool isV9(const MCSubtargetInfo &STI) const

Definition SparcInstPrinter.cpp:37

void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &OS)

Definition SparcInstPrinter.cpp:149

static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=SP::NoRegAltName)

bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS)

Definition SparcInstPrinter.cpp:59

void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &OS)

Definition SparcInstPrinter.cpp:174

bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &OS)

Definition SparcInstPrinter.cpp:217

void printPrefetchTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition SparcInstPrinter.cpp:257

void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printCTILabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition SparcInstPrinter.cpp:268

void printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition SparcInstPrinter.cpp:224

void printRegName(raw_ostream &OS, MCRegister Reg) override

Print the assembler register name.

Definition SparcInstPrinter.cpp:41

StringRef - Represent a constant reference to a string, i.e.

bool isSPARC32() const

Tests whether the target is 32-bit SPARC (little and big endian).

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

static const char * SPARCCondCodeToString(SPCC::CondCodes CC)

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

DWARFExpression::Operation Op