SystemZISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H

15#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H

22#include

24namespace llvm {

36class SystemZSubtarget;

39public:

55 const override {

70 }

71 unsigned

73 std::optional RegisterVT) const override {

75 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)

76 return 1;

78 }

80 EVT VT) const override {

85 return MVT::v16i8;

87 }

93 return Mask && Mask->getValue().isIntN(16);

94 }

99 EVT) const override;

101 EVT VT) const override;

103 bool ForCodeSize) const override;

105

106

107 return VT != MVT::f64;

108 }

111

114

123 unsigned AS,

127 unsigned *Fast) const override;

128 bool

130 unsigned Limit, const MemOp &Op, unsigned DstAS,

131 unsigned SrcAS,

132 const AttributeList &FuncAttributes) const override;

134 const AttributeList &FuncAttributes) const override;

137

139 bool MathUsed) const override {

140

141

142 return VT == MVT::i32 || VT == MVT::i64 || VT == MVT::i128;

143 }

144

146

150

151

152 CondMergingParams

154 const Value *Rhs) const override;

155

156

159 const AsmOperandInfo &Constraint,

161

162 std::pair<unsigned, const TargetRegisterClass *>

164 StringRef Constraint, MVT VT) const override;

169 const char *constraint) const override;

171 std::vector &Ops,

173

176 if (ConstraintCode.size() == 1) {

177 switch(ConstraintCode[0]) {

178 default:

179 break;

180 case 'o':

182 case 'Q':

184 case 'R':

186 case 'S':

188 case 'T':

190 }

191 } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {

192 switch (ConstraintCode[1]) {

193 default:

194 break;

195 case 'Q':

197 case 'R':

199 case 'S':

201 case 'T':

203 }

204 }

206 }

207

210

211

212

215

216

217

220

221

225

239 unsigned NumParts, MVT PartVT, std::optionalCallingConv::ID CC)

240 const override;

243 unsigned NumParts, MVT PartVT, EVT ValueVT,

244 std::optionalCallingConv::ID CC) const override;

246 bool isVarArg,

252

253 std::pair<SDValue, SDValue>

256 bool IsSigned, SDLoc DL, bool DoesNotReturn,

257 bool IsReturnValueUsed) const;

258

261

263 bool isVarArg,

266 const Type *RetTy) const override;

272

273

274

277 const APInt &DemandedElts,

279 unsigned Depth = 0) const override;

280

281

283 const APInt &DemandedElts,

285 unsigned Depth) const override;

286

290

297

301

304

305private:

307

308

316 bool IsSignaling = false) const;

319 bool IsSignaling) const;

326 SDValue GOTOffset) const;

360 unsigned Opcode) const;

368 bool isVectorElementLoad(SDValue Op) const;

386

390

391 bool canTreatAsByteVector(EVT VT) const;

393 unsigned Index, DAGCombinerInfo &DCI,

394 bool Force) const;

396 DAGCombinerInfo &DCI) const;

397 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;

398 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;

399 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;

400 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;

401 bool canLoadStoreByteSwapped(EVT VT) const;

404 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;

405 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;

406 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;

409 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;

410 SDValue combineFCOPYSIGN(SDNode *N, DAGCombinerInfo &DCI) const;

411 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;

412 SDValue combineSETCC(SDNode *N, DAGCombinerInfo &DCI) const;

413 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;

414 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;

415 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;

416 SDValue combineShiftToMulAddHigh(SDNode *N, DAGCombinerInfo &DCI) const;

417 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;

418 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;

419 SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;

420

422

423

424

425

426

429 unsigned CCMask,

431

432

437 unsigned StoreOpcode, unsigned STOCOpcode,

438 bool Invert) const;

444 bool ClearEven) const;

447 unsigned BinOpcode,

448 bool Invert = false) const;

451 unsigned CompareOpcode,

452 unsigned KeepOldMask) const;

456 unsigned Opcode,

457 bool IsMemset = false) const;

459 unsigned Opcode) const;

462 unsigned Opcode, bool NoFloat) const;

465 unsigned Opcode) const;

468

470

472 getTargetMMOFlags(const Instruction &I) const override;

474

475private:

476 bool isInternal(const Function *Fn) const;

477 mutable std::map<const Function *, bool> IsInternalCache;

482 bool

484

485public:

486};

487

489private:

490 APInt IntBits;

491 APInt SplatBits;

492 APInt SplatUndef;

493 unsigned SplatBitSize = 0;

494 bool isFP128 = false;

495public:

506};

507

508}

509

510#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Function Alias Analysis Results

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static SDValue combineLOAD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &STI)

static SDValue combineSTORE(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &STI)

static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)

static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

This file describes how to lower LLVM code to machine code.

static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)

static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)

static SDValue combineFP_EXTEND(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)

static SDValue combineFP_ROUND(SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)

static const fltSemantics & IEEEquad()

const fltSemantics & getSemantics() const

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

an instruction that atomically reads a memory location, combines it with another value,...

A "pseudo-class" with methods for operating on BUILD_VECTORs.

This class represents a function call, abstracting a target machine's calling convention.

This is the shared class of boolean and integer constants.

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

uint64_t getScalarSizeInBits() const

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

constexpr size_t size() const

size - Get the string size.

bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override

Try to convert math with an overflow comparison into the corresponding DAG node operation.

Definition SystemZISelLowering.h:138

If a physical register, this returns the register that receives the exception typeid on entry to a la...

bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override

Return if the target supports combining a chain like:

Definition SystemZISelLowering.h:91

MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

Definition SystemZISelLowering.h:79

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override

Returns the target specific optimal type for load and store operations as a result of memset,...

ISD::NodeType getExtendForAtomicOps() const override

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...

Definition SystemZISelLowering.h:291

bool useLoadStackGuardNode(const Module &M) const override

Override to support customized stack guard loading.

Definition SystemZISelLowering.h:222

bool hasInlineStackProbe(const MachineFunction &MF) const override

Returns true if stack probing through inline assembly is requested.

bool findOptimalMemOpLowering(LLVMContext &Context, std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const override

Determines the optimal series of memory ops to replace the memset / memcpy.

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

bool convertSetCCLogicToBitwiseLogic(EVT VT) const override

Use bitwise logic to make pairs of compares more efficient.

Definition SystemZISelLowering.h:95

MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const

AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override

Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override

Return the ValueType of the result of SETCC operations.

bool allowTruncateForTailCall(Type *, Type *) const override

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...

SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override

bool preferSelectsOverBooleanArithmetic(EVT VT) const override

Should we prefer selects to doing arithmetic on boolean types.

Definition SystemZISelLowering.h:147

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

bool preferZeroCompareBranch() const override

Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.

Definition SystemZISelLowering.h:90

MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const

CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs) const override

bool useSoftFloat() const override

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

std::pair< SDValue, SDValue > makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, ArrayRef< SDValue > Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL, bool DoesNotReturn, bool IsReturnValueUsed) const

bool shouldConsiderGEPOffsetSplit() const override

Definition SystemZISelLowering.h:145

bool supportSwiftError() const override

Return true if the target supports swifterror attribute.

Definition SystemZISelLowering.h:298

bool mayBeEmittedAsTailCall(const CallInst *CI) const override

Return true if the target may be able emit the call instruction as a tail call.

bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override

Target-specific splitting of values into parts that fit a register storing a legal type.

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)

bool isCheapToSpeculateCtlz(Type *) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Definition SystemZISelLowering.h:88

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

bool isLegalICmpImmediate(int64_t Imm) const override

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override

Examine constraint string and operand type and determine a weight value.

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override

Determine if the target supports unaligned memory accesses.

const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override

Returns a 0 terminated array of registers that can be safely used as scratch registers.

TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override

Given a constraint, return the type of constraint it is for this target.

bool ShouldShrinkFPConstant(EVT VT) const override

If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...

Definition SystemZISelLowering.h:104

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

If a physical register, this returns the register that receives the exception address on entry to an ...

SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override

Target-specific combining of register parts into its original value.

unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT) const override

Return the number of registers that this ValueType will eventually require.

Definition SystemZISelLowering.h:72

bool isTruncateFree(Type *, Type *) const override

Return true if it's free to truncate a value of type FromTy to type ToTy.

SDValue useLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, MVT VT, SDValue Arg, SDLoc DL, SDValue Chain, bool IsStrict) const

unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override

Determine the number of bits in the operation that are sign bits.

ISD::NodeType getExtendForAtomicCmpSwapArg() const override

Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...

Definition SystemZISelLowering.h:294

void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override

Definition SystemZISelLowering.h:175

SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

bool isLegalAddImmediate(int64_t Imm) const override

Return true if the specified immediate is legal add immediate, that is the target has add instruction...

bool isCheapToSpeculateCttz(Type *) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

Definition SystemZISelLowering.h:89

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

This callback is invoked when a node result type is illegal for the target, and the operation was reg...

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

Lower the specified operand into the Ops vector.

bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const override

Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition SystemZISelLowering.h:46

void insertSSPDeclarations(Module &M) const override

Inserts necessary declarations for SSP (stack protection) purpose.

Definition SystemZISelLowering.h:223

AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override

Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.

Return the register ID of the name passed in.

bool hasAndNot(SDValue Y) const override

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override

Return the preferred vector type legalization action.

Definition SystemZISelLowering.h:54

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

unsigned getStackProbeSize(const MachineFunction &MF) const

unsigned getVectorIdxWidth(const DataLayout &DL) const override

Returns the type to be used for the index operand vector operations.

Definition SystemZISelLowering.h:49

virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const

Return the number of registers that this ValueType will eventually require.

virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const

Return the preferred vector type legalization action.

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const

TargetLowering(const TargetLowering &)=delete

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Target - Wrapper for Target specific information.

The instances of the Type class are immutable: once they are created, they are never changed.

Value * getOperand(unsigned i) const

LLVM Value Representation.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

@ Any

Definition SystemZISelLowering.h:30

@ UnsignedOnly

Definition SystemZISelLowering.h:31

@ SignedOnly

Definition SystemZISelLowering.h:32

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

This struct is a compact representation of a valid (non-zero power of two) alignment.

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

bool isVector() const

Return true if this is a vector value type.

bool isScalarInteger() const

Return true if this is an integer, but not a vector.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

MVT VecVT

Definition SystemZISelLowering.h:498

unsigned Opcode

Definition SystemZISelLowering.h:496

SystemZVectorConstantInfo(APFloat FPImm)

Definition SystemZISelLowering.h:500

SystemZVectorConstantInfo(APInt IntImm)

SmallVector< unsigned, 2 > OpVals

Definition SystemZISelLowering.h:497

bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)