SystemZMachineScheduler.cpp Source File (original) (raw)

20using namespace llvm;

22#define DEBUG_TYPE "machine-scheduler"

24#ifndef NDEBUG

26void SystemZPostRASchedStrategy::SUSet::

28 dbgs() << "{";

29 for (auto &SU : *this) {

31 if (SU != *rbegin())

32 dbgs() << ", ";

33 }

34 dbgs() << "}\n";

35}

36#endif

51 PredMBB = (Pred == MBB ? nullptr : Pred);

52 }

55 && "Loop MBB should not consider predecessor outside of loop.");

57 return PredMBB;

58}

60void SystemZPostRASchedStrategy::

64 ((LastEmittedMI != nullptr && LastEmittedMI->getParent() == MBB) ?

65 std::next(LastEmittedMI) : MBB->begin());

67 for (; I != NextBegin; ++I) {

68 if (I->isPosition() || I->isDebugInstr())

69 continue;

71 }

72}

75 Available.clear();

77}

80 assert ((SchedStates.find(NextMBB) == SchedStates.end()) &&

81 "Entering MBB twice?");

84 MBB = NextMBB;

91 dbgs() << ":\n";);

97 if (SinglePredMBB == nullptr ||

98 SchedStates.find(SinglePredMBB) == SchedStates.end())

99 return;

100

103

104 HazardRec->copyState(SchedStates[SinglePredMBB]);

106

107

108

109 for (MachineInstr &MI : SinglePredMBB->terminators()) {

111 bool TakenBranch = (MI.isBranch() &&

115 if (TakenBranch)

116 break;

117 }

118}

119

122

123

124

126}

127

130 : MLI(C->MLI),

132 (C->MF->getSubtarget().getInstrInfo())),

133 MBB(nullptr), HazardRec(nullptr) {

135 SchedModel.init(ST);

136}

137

139

140 for (auto I : SchedStates) {

142 delete hazrec;

143 }

144}

145

148 unsigned NumRegionInstrs) {

149

150 if (Begin->isTerminator())

151 return;

152

153

154 advanceTo(Begin);

155}

156

157

159

160 IsTopNode = true;

161

162 if (Available.empty())

163 return nullptr;

164

165

166 if (Available.size() == 1) {

168 HazardRec->dumpSU(*Available.begin(), dbgs()); dbgs() << "\n";);

169 return *Available.begin();

170 }

171

172

173 LLVM_DEBUG(dbgs() << "** Available: "; Available.dump(*HazardRec););

174

175 Candidate Best;

176 for (auto *SU : Available) {

177

178

179 Candidate c(SU, *HazardRec);

180

181

182 if (Best.SU == nullptr || c < Best) {

183 Best = c;

185 } else

188 dbgs() << " Height:" << c.SU->getHeight(); dbgs() << "\n";);

189

190

191

192 if (!SU->isScheduleHigh && Best.noCost())

193 break;

194 }

195

196 assert (Best.SU != nullptr);

197 return Best.SU;

198}

199

200SystemZPostRASchedStrategy::Candidate::

202 SU = SU_;

203

204

205

206

208

209

211}

212

213bool SystemZPostRASchedStrategy::Candidate::

214operator<(const Candidate &other) {

215

216

217 if (GroupingCost < other.GroupingCost)

218 return true;

219 if (GroupingCost > other.GroupingCost)

220 return false;

221

222

223 if (ResourcesCost < other.ResourcesCost)

224 return true;

225 if (ResourcesCost > other.ResourcesCost)

226 return false;

227

228

229 if (SU->getHeight() > other.SU->getHeight())

230 return true;

231 if (SU->getHeight() < other.SU->getHeight())

232 return false;

233

234

235 if (SU->NodeNum < other.SU->NodeNum)

236 return true;

237

238 return false;

239}

240

243 if (Available.size() == 1) dbgs() << "(only one) ";

244 Candidate c(SU, *HazardRec); c.dumpCosts(); dbgs() << "\n";);

245

246

247 Available.erase(SU);

249}

250

252

253

255 bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup));

257

258

259 Available.insert(SU);

260}

const HexagonInstrInfo * TII

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static MachineBasicBlock * getSingleSchedPred(MachineBasicBlock *MBB, const MachineLoop *Loop)

bool contains(const LoopT *L) const

Return true if the specified loop is contained within in this loop.

BlockT * getHeader() const

LoopT * getLoopFor(const BlockT *BB) const

Return the inner most loop that BB lives in.

Represents a single loop in the control flow graph.

unsigned pred_size() const

iterator getFirstTerminator()

Returns an iterator to the first terminator instruction of this basic block.

pred_iterator pred_begin()

iterator_range< pred_iterator > predecessors()

Representation of each machine instruction.

Scheduling unit. This is a node in the scheduling DAG.

unsigned NodeNum

Entry # of node in the node vector.

bool isUnbuffered

Uses an unbuffered resource.

bool isScheduleHigh

True if preferable to schedule high.

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

SystemZHazardRecognizer maintains the state for one MBB during scheduling.

int groupingCost(SUnit *SU) const

Return the cost of decoder grouping for SU.

void emitInstruction(MachineInstr *MI, bool TakenBranch=false)

Wrap a non-scheduled instruction in an SU and emit it.

const MCSchedClassDesc * getSchedClass(SUnit *SU) const

Resolves and cache a resolved scheduling class for an SUnit.

void copyState(SystemZHazardRecognizer *Incoming)

Copy counters from end of single predecessor.

void dumpSU(SUnit *SU, raw_ostream &OS) const

MachineBasicBlock::iterator getLastEmittedMI()

int resourcesCost(SUnit *SU)

Return the cost of SU in regards to processor resources usage.

void EmitInstruction(SUnit *SU) override

EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...

MachineBasicBlock * getMBBTarget()

SystemZII::Branch getBranchInfo(const MachineInstr &MI) const

SUnit * pickNode(bool &IsTopNode) override

Pick the next node to schedule, or return NULL.

void leaveMBB() override

Tell the strategy that current MBB is done.

void initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) override

Called for a region before scheduling.

void schedNode(SUnit *SU, bool IsTopNode) override

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it.

void initialize(ScheduleDAGMI *dag) override

Initialize the strategy after building the DAG for a new region.

void enterMBB(MachineBasicBlock *NextMBB) override

Tell the strategy that MBB is about to be processed.

virtual ~SystemZPostRASchedStrategy()

SystemZPostRASchedStrategy(const MachineSchedContext *C)

void releaseTopNode(SUnit *SU) override

SU has had all predecessor dependencies resolved.

void init(const TargetSubtargetInfo *TSInfo)

Initialize the machine model for instruction scheduling.

TargetSubtargetInfo - Generic base class for all target subtargets.

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

Summarize the scheduling resources required for an instruction of a particular scheduling class.

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...