LLVM: llvm::TargetSchedModel Class Reference (original) (raw)
Provide an instruction scheduling machine model to CodeGen passes. More...
#include "[llvm/CodeGen/TargetSchedule.h](TargetSchedule%5F8h%5Fsource.html)"
| Public Member Functions | |
|---|---|
| TargetSchedModel () | |
| void | init (const TargetSubtargetInfo *TSInfo) |
| Initialize the machine model for instruction scheduling. | |
| const MCSchedClassDesc * | resolveSchedClass (const MachineInstr *MI) const |
| Return the MCSchedClassDesc for this instruction. | |
| const TargetSubtargetInfo * | getSubtargetInfo () const |
| TargetSubtargetInfo getter. | |
| const TargetInstrInfo * | getInstrInfo () const |
| TargetInstrInfo getter. | |
| bool | hasInstrSchedModel () const |
| Return true if this machine model includes an instruction-level scheduling model. | |
| const MCSchedModel * | getMCSchedModel () const |
| bool | hasInstrItineraries () const |
| Return true if this machine model includes cycle-to-cycle itinerary data. | |
| const InstrItineraryData * | getInstrItineraries () const |
| bool | hasInstrSchedModelOrItineraries () const |
| Return true if this machine model includes an instruction-level scheduling model or cycle-to-cycle itinerary data. | |
| bool | enableIntervals () const |
| unsigned | getProcessorID () const |
| Identify the processor corresponding to the current subtarget. | |
| unsigned | getIssueWidth () const |
| Maximum number of micro-ops that may be scheduled per cycle. | |
| bool | mustBeginGroup (const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const |
| Return true if new group must begin. | |
| bool | mustEndGroup (const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const |
| Return true if current group must end. | |
| unsigned | getNumMicroOps (const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const |
| Return the number of issue slots required for this MI. | |
| unsigned | getNumProcResourceKinds () const |
| Get the number of kinds of resources for this target. | |
| const MCProcResourceDesc * | getProcResource (unsigned PIdx) const |
| Get a processor resource by ID for convenience. | |
| const char * | getResourceName (unsigned PIdx) const |
| ProcResIter | getWriteProcResBegin (const MCSchedClassDesc *SC) const |
| ProcResIter | getWriteProcResEnd (const MCSchedClassDesc *SC) const |
| unsigned | getResourceFactor (unsigned ResIdx) const |
| Multiply the number of units consumed for a resource by this factor to normalize it relative to other resources. | |
| unsigned | getMicroOpFactor () const |
| Multiply number of micro-ops by this factor to normalize it relative to other resources. | |
| unsigned | getLatencyFactor () const |
| Multiply cycle count by this factor to normalize it relative to other resources. | |
| unsigned | getMicroOpBufferSize () const |
| Number of micro-ops that may be buffered for OOO execution. | |
| int | getResourceBufferSize (unsigned PIdx) const |
| Number of resource units that may be buffered for OOO execution. | |
| unsigned | computeOperandLatency (const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const |
| Compute operand latency based on the available machine model. | |
| unsigned | computeInstrLatency (const MachineInstr *MI, bool UseDefaultDefLatency=true) const |
| Compute the instruction latency based on the available machine model. | |
| unsigned | computeInstrLatency (const MCInst &Inst) const |
| unsigned | computeInstrLatency (unsigned Opcode) const |
| unsigned | computeOutputLatency (const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const |
| Output dependency latency of a pair of defs of the same register. | |
| double | computeReciprocalThroughput (const MachineInstr *MI) const |
| Compute the reciprocal throughput of the given instruction. | |
| double | computeReciprocalThroughput (const MCInst &MI) const |
| double | computeReciprocalThroughput (unsigned Opcode) const |
Provide an instruction scheduling machine model to CodeGen passes.
Definition at line 30 of file TargetSchedule.h.
◆ ProcResIter
| llvm::TargetSchedModel::TargetSchedModel ( ) | inline |
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◆ computeInstrLatency() [1/3]
◆ computeInstrLatency() [2/3]
◆ computeInstrLatency() [3/3]
◆ computeOperandLatency()
Compute operand latency based on the available machine model.
Compute and return the latency of the given data dependent def and use when the operand indices are already known. UseMI may be NULL for an unknown user.
Definition at line 172 of file TargetSchedule.cpp.
References capLatency(), llvm::MCWriteLatencyEntry::Cycles, llvm::TargetInstrInfo::defaultDefLatency(), DefMI, llvm::errs(), findDefIdx(), findUseIdx(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), llvm::InstrItineraryData::getOperandCycle(), llvm::TargetInstrInfo::getOperandLatency(), llvm::MCSubtargetInfo::getReadAdvanceCycles(), llvm::MCInstrDesc::getSchedClass(), llvm::MCSubtargetInfo::getWriteLatencyEntry(), hasInstrItineraries(), hasInstrSchedModel(), llvm::MCSchedModel::isComplete(), llvm::MachineOperand::isImplicit(), llvm::MachineInstr::isTransient(), llvm::MCSchedClassDesc::isValid(), llvm::Latency, llvm_unreachable, llvm::MCSchedClassDesc::NumReadAdvanceEntries, llvm::MCInstrDesc::operands(), resolveSchedClass(), UseMI, and llvm::MCWriteLatencyEntry::WriteResourceID.
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::AArch64Subtarget::adjustSchedDependency(), llvm::GCNSubtarget::adjustSchedDependency(), pushDepHeight(), and updatePhysDepsUpwards().
◆ computeOutputLatency()
Output dependency latency of a pair of defs of the same register.
This is typically one cycle.
Definition at line 272 of file TargetSchedule.cpp.
References llvm::MCProcResourceDesc::BufferSize, DefMI, llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), llvm::MCSchedModel::getProcResource(), llvm::MachineOperand::getReg(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MCSubtargetInfo::getWriteProcResBegin(), llvm::MCSubtargetInfo::getWriteProcResEnd(), hasInstrSchedModel(), llvm::MCSchedModel::isOutOfOrder(), llvm::TargetInstrInfo::isPredicated(), llvm::MCSchedClassDesc::isValid(), llvm::MachineInstr::readsRegister(), resolveSchedClass(), and TRI.
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDeps(), and llvm::ScheduleDAGInstrs::addVRegDefDeps().
◆ computeReciprocalThroughput() [1/3]
| double TargetSchedModel::computeReciprocalThroughput | ( | const MachineInstr * | MI | ) | const |
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◆ computeReciprocalThroughput() [2/3]
| double TargetSchedModel::computeReciprocalThroughput | ( | const MCInst & | MI | ) | const |
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◆ computeReciprocalThroughput() [3/3]
| double TargetSchedModel::computeReciprocalThroughput | ( | unsigned | Opcode | ) | const |
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◆ enableIntervals()
| bool TargetSchedModel::enableIntervals | ( | ) | const |
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◆ getInstrInfo()
◆ getInstrItineraries()
◆ getIssueWidth()
| unsigned llvm::TargetSchedModel::getIssueWidth ( ) const | inline |
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◆ getLatencyFactor()
| unsigned llvm::TargetSchedModel::getLatencyFactor ( ) const | inline |
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◆ getMCSchedModel()
◆ getMicroOpBufferSize()
| unsigned llvm::TargetSchedModel::getMicroOpBufferSize ( ) const | inline |
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◆ getMicroOpFactor()
| unsigned llvm::TargetSchedModel::getMicroOpFactor ( ) const | inline |
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◆ getNumMicroOps()
◆ getNumProcResourceKinds()
| unsigned llvm::TargetSchedModel::getNumProcResourceKinds ( ) const | inline |
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◆ getProcessorID()
| unsigned llvm::TargetSchedModel::getProcessorID ( ) const | inline |
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◆ getProcResource()
Get a processor resource by ID for convenience.
Definition at line 117 of file TargetSchedule.h.
References llvm::MCSchedModel::getProcResource().
Referenced by llvm::SchedBoundary::bumpNode(), llvm::SystemZHazardRecognizer::dumpProcResourceCounters(), llvm::SchedBoundary::dumpReservedCycles(), llvm::SystemZHazardRecognizer::dumpSU(), llvm::SystemZHazardRecognizer::emitInstruction(), llvm::SystemZHazardRecognizer::EmitInstruction(), llvm::SchedBoundary::getNextResourceCycle(), llvm::SchedBoundary::init(), llvm::ScheduleDAGInstrs::initSUnits(), llvm::SchedBoundary::isUnbufferedGroup(), and llvm::GenericSchedulerBase::traceCandidate().
◆ getResourceBufferSize()
| int llvm::TargetSchedModel::getResourceBufferSize ( unsigned PIdx) const | inline |
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◆ getResourceFactor()
| unsigned llvm::TargetSchedModel::getResourceFactor ( unsigned ResIdx) const | inline |
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◆ getResourceName()
◆ getSubtargetInfo()
◆ getWriteProcResBegin()
Definition at line 133 of file TargetSchedule.h.
References llvm::MCSubtargetInfo::getWriteProcResBegin().
Referenced by llvm::SchedBoundary::bumpNode(), llvm::SchedBoundary::checkHazard(), llvm::ScheduleDAGMI::dumpScheduleTraceBottomUp(), llvm::ScheduleDAGMI::dumpScheduleTraceTopDown(), llvm::SystemZHazardRecognizer::dumpSU(), llvm::SystemZHazardRecognizer::emitInstruction(), llvm::SystemZHazardRecognizer::EmitInstruction(), llvm::SchedBoundary::getNextResourceCycle(), llvm::MachineTraceMetrics::getResources(), llvm::SchedRemainder::init(), llvm::GenericSchedulerBase::SchedCandidate::initResourceDelta(), llvm::ScheduleDAGInstrs::initSUnits(), and llvm::SystemZHazardRecognizer::resourcesCost().
◆ getWriteProcResEnd()
Definition at line 137 of file TargetSchedule.h.
References llvm::MCSubtargetInfo::getWriteProcResEnd().
Referenced by llvm::SchedBoundary::bumpNode(), llvm::SchedBoundary::checkHazard(), llvm::ScheduleDAGMI::dumpScheduleTraceBottomUp(), llvm::ScheduleDAGMI::dumpScheduleTraceTopDown(), llvm::SystemZHazardRecognizer::dumpSU(), llvm::SystemZHazardRecognizer::emitInstruction(), llvm::SystemZHazardRecognizer::EmitInstruction(), llvm::SchedBoundary::getNextResourceCycle(), llvm::MachineTraceMetrics::getResources(), llvm::SchedRemainder::init(), llvm::GenericSchedulerBase::SchedCandidate::initResourceDelta(), llvm::ScheduleDAGInstrs::initSUnits(), and llvm::SystemZHazardRecognizer::resourcesCost().
◆ hasInstrItineraries()
| bool TargetSchedModel::hasInstrItineraries | ( | ) | const |
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◆ hasInstrSchedModel()
| bool TargetSchedModel::hasInstrSchedModel | ( | ) | const |
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Return true if this machine model includes an instruction-level scheduling model.
This is more detailed than the course grain IssueWidth and default latency properties, but separate from the per-cycle itinerary data.
Definition at line 42 of file TargetSchedule.cpp.
References EnableSchedModel, and llvm::MCSchedModel::hasInstrSchedModel().
Referenced by llvm::SchedBoundary::bumpNode(), llvm::SchedBoundary::checkHazard(), computeInstrLatency(), computeOperandLatency(), computeOutputLatency(), computeReciprocalThroughput(), llvm::SchedBoundary::dumpReservedCycles(), llvm::ScheduleDAGMI::dumpScheduleTraceBottomUp(), llvm::ScheduleDAGMI::dumpScheduleTraceTopDown(), getNumMicroOps(), llvm::SchedBoundary::getOtherResourceCount(), llvm::MachineTraceMetrics::getResources(), llvm::ScheduleDAGInstrs::getSchedClass(), llvm::SystemZHazardRecognizer::getSchedClass(), hasInstrSchedModelOrItineraries(), llvm::SchedRemainder::init(), llvm::SchedBoundary::init(), llvm::ScheduleDAGInstrs::initSUnits(), mustBeginGroup(), mustEndGroup(), and llvm::GenericSchedulerBase::setPolicy().
◆ hasInstrSchedModelOrItineraries()
| bool llvm::TargetSchedModel::hasInstrSchedModelOrItineraries ( ) const | inline |
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◆ init()
Initialize the machine model for instruction scheduling.
The machine model API keeps a copy of the top-level MCSchedModel table indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve dynamic properties.
Definition at line 50 of file TargetSchedule.cpp.
References llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), llvm::MCSubtargetInfo::getSchedModel(), Idx, llvm::MCSubtargetInfo::initInstrItins(), llvm::MCSchedModel::IssueWidth, llvm::MCProcResourceDesc::NumUnits, and llvm::SmallVectorImpl< T >::resize().
Referenced by llvm::MachineTraceMetrics::init(), llvm::PPCTTIImpl::isHardwareLoopProfitable(), llvm::ScheduleDAGInstrs::ScheduleDAGInstrs(), llvm::SIInstrInfo::SIInstrInfo(), and llvm::SystemZPostRASchedStrategy::SystemZPostRASchedStrategy().
◆ mustBeginGroup()
◆ mustEndGroup()
◆ resolveSchedClass()
Return the MCSchedClassDesc for this instruction.
Some SchedClasses require evaluation of predicates that depend on instruction operands or flags.
Definition at line 119 of file TargetSchedule.cpp.
References assert(), llvm::MCSchedModel::getSchedClassDesc(), llvm::MCSchedClassDesc::isValid(), llvm::MCSchedClassDesc::isVariant(), MI, and llvm::TargetSubtargetInfo::resolveSchedClass().
Referenced by computeInstrLatency(), computeOperandLatency(), computeOutputLatency(), computeReciprocalThroughput(), llvm::SystemZHazardRecognizer::emitInstruction(), getNumMicroOps(), llvm::MachineTraceMetrics::getResources(), llvm::ScheduleDAGInstrs::getSchedClass(), llvm::SystemZHazardRecognizer::getSchedClass(), mustBeginGroup(), and mustEndGroup().
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/TargetSchedule.h
- lib/CodeGen/TargetSchedule.cpp