TargetInstrInfo.cpp Source File (original) (raw)

40using namespace llvm;

44 cl::desc("Disable hazard detection during preRA scheduling"));

48 cl::desc("Enable reassociation of accumulation chains"));

52 cl::desc("Minimum length of accumulator chains "

53 "required for the optimization to kick in"));

57 cl::desc("Maximum number of branches in the accumulator tree"));

62 unsigned OpNum) const {

63 if (OpNum >= MCID.getNumOperands())

64 return nullptr;

70 if (RegClass < 0)

71 return nullptr;

74 return TRI.getRegClass(RegClass);

75}

88 unsigned Quantity) const {

89 for (unsigned i = 0; i < Quantity; ++i)

91}

100

101

102

103

104

105

106

107

108

109

110

111

113 const char *Str,

115

116 bool AtInsnStart = true;

119 for (; *Str; ++Str) {

122 AtInsnStart = true;

124

125

126 AtInsnStart = false;

127 }

128

129 if (AtInsnStart && isSpace (static_cast<unsigned char>(*Str))) {

130 unsigned AddLength = MaxInstLength;

131 if (strncmp(Str, ".space", 6) == 0) {

132 char *EStr;

133 int SpaceSize;

134 SpaceSize = strtol(Str + 6, &EStr, 10);

135 SpaceSize = SpaceSize < 0 ? 0 : SpaceSize;

136 while (*EStr != '\n' && isSpace(static_cast<unsigned char>(*EStr)))

137 ++EStr;

138 if (*EStr == '\0' || *EStr == '\n' ||

139 isAsmComment(EStr, MAI))

140 AddLength = SpaceSize;

141 }

143 AtInsnStart = false;

144 }

145 }

146

148}

149

150

151

152void

156

157

158 while ( MBB ->succ_empty())

159 MBB->removeSuccessor(MBB->succ_begin());

160

161

163

164

165

166 while (Tail != MBB->end()) {

168 if (MI->shouldUpdateAdditionalCallInfo())

169 MBB->getParent()->eraseAdditionalCallInfo(&*MI);

171 }

172

173

176 MBB->addSuccessor(NewDest);

177}

178

180 bool NewMI, unsigned Idx1,

181 unsigned Idx2) const {

183 bool HasDef = MCID.getNumDefs();

184 if (HasDef && .getOperand(0).isReg())

185

186 return nullptr;

187

188 unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;

189 unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;

191 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&

192 "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");

193 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&

194 "This only knows how to commute register operands so far");

195

197 Register Reg1 = MI.getOperand(Idx1).getReg();

198 Register Reg2 = MI.getOperand(Idx2).getReg();

199 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;

200 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();

201 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();

202 bool Reg1IsKill = MI.getOperand(Idx1).isKill();

203 bool Reg2IsKill = MI.getOperand(Idx2).isKill();

204 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();

205 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();

206 bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();

207 bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();

208

209

210 bool Reg1IsRenamable =

211 Reg1.isPhysical() ? MI.getOperand(Idx1).isRenamable() : false;

212 bool Reg2IsRenamable =

213 Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false;

214

215

216

217

218

220 if (HasDef && MI.hasImplicitDef()) {

221 for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {

222 Register ImplReg = MO.getReg();

223 if ((ImplReg.isVirtual() && ImplReg == Reg0) ||

225 TRI.isSubRegisterEq(ImplReg, Reg0)))

226 UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());

227 }

228 }

229

230

231

232 if (HasDef && Reg0 == Reg1 &&

233 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {

234 Reg2IsKill = false;

235 Reg0 = Reg2;

236 SubReg0 = SubReg2;

237 } else if (HasDef && Reg0 == Reg2 &&

238 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {

239 Reg1IsKill = false;

240 Reg0 = Reg1;

241 SubReg0 = SubReg1;

242 }

243

245 if (NewMI) {

246

248 CommutedMI = MF.CloneMachineInstr(&MI);

249 } else {

250 CommutedMI = &MI;

251 }

252

253 if (HasDef) {

256 for (unsigned Idx : UpdateImplicitDefIdx)

258 }

269

270

275 return CommutedMI;

276}

277

279 unsigned OpIdx1,

280 unsigned OpIdx2) const {

281

282

283

287 "Precondition violation: MI must be commutable.");

288 return nullptr;

289 }

291}

292

294 unsigned &ResultIdx2,

295 unsigned CommutableOpIdx1,

296 unsigned CommutableOpIdx2) {

299 ResultIdx1 = CommutableOpIdx1;

300 ResultIdx2 = CommutableOpIdx2;

302 if (ResultIdx2 == CommutableOpIdx1)

303 ResultIdx1 = CommutableOpIdx2;

304 else if (ResultIdx2 == CommutableOpIdx2)

305 ResultIdx1 = CommutableOpIdx1;

306 else

307 return false;

309 if (ResultIdx1 == CommutableOpIdx1)

310 ResultIdx2 = CommutableOpIdx2;

311 else if (ResultIdx1 == CommutableOpIdx2)

312 ResultIdx2 = CommutableOpIdx1;

313 else

314 return false;

315 } else

316

317

318 return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||

319 (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);

320

321 return true;

322}

323

325 unsigned &SrcOpIdx1,

326 unsigned &SrcOpIdx2) const {

328 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");

329

331 if ( MCID .isCommutable())

332 return false;

333

334

335

336 unsigned CommutableOpIdx1 = MCID.getNumDefs();

337 unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;

339 CommutableOpIdx1, CommutableOpIdx2))

340 return false;

341

342 if (.getOperand(SrcOpIdx1).isReg() || .getOperand(SrcOpIdx2).isReg())

343

344 return false;

345 return true;

346}

347

349 if (.isTerminator()) return false;

350

351

352 if (MI.isBranch() && .isBarrier())

353 return true;

354 if (.isPredicable())

355 return true;

357}

358

361 bool MadeChange = false;

362

364 "TargetInstrInfo::PredicateInstruction() can't handle bundles");

365

367 if (.isPredicable())

368 return false;

369

370 for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {

371 if (MCID.operands()[i].isPredicate()) {

373 if (MO.isReg()) {

375 MadeChange = true;

376 } else if (MO.isImm()) {

378 MadeChange = true;

379 } else if (MO.isMBB()) {

380 MO.setMBB(Pred[j].getMBB());

381 MadeChange = true;

382 }

383 ++j;

384 }

385 }

386 return MadeChange;

387}

388

392 size_t StartSize = Accesses.size();

394 oe = MI.memoperands_end();

395 o != oe; ++o) {

396 if ((*o)->isLoad() &&

399 }

400 return Accesses.size() != StartSize;

401}

402

406 size_t StartSize = Accesses.size();

408 oe = MI.memoperands_end();

409 o != oe; ++o) {

410 if ((*o)->isStore() &&

413 }

414 return Accesses.size() != StartSize;

415}

416

418 unsigned SubIdx, unsigned &Size,

421 if (!SubIdx) {

422 Size = TRI.getSpillSize(*RC);

424 return true;

425 }

426 unsigned BitSize = TRI.getSubRegIdxSize(SubIdx);

427

428 if (BitSize % 8)

429 return false;

430

431 int BitOffset = TRI.getSubRegIdxOffset(SubIdx);

432 if (BitOffset < 0 || BitOffset % 8)

433 return false;

434

435 Size = BitSize / 8;

437

438 assert(TRI.getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");

439

442 }

443 return true;

444}

445

448 Register DestReg, unsigned SubIdx,

451 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);

453}

454

460

466

467

471 "Instruction cannot be duplicated");

472

473 return MF.cloneMachineInstrBundle(MBB, InsertBefore, Orig);

474}

475

476

477

480 unsigned FoldIdx) {

481 assert(TII.isCopyInstr(MI) && "MI must be a COPY instruction");

482 if (MI.getNumOperands() != 2)

483 return nullptr;

484 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");

485

488

490 return nullptr;

491

494

496

499

502

504 return RC;

505

506

507 return nullptr;

508}

509

511

512

513

514

515

520

521 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);

523 bool SawStore = false;

524 if ( DefMI ->isSafeToMove(SawStore))

525 return nullptr;

526

527

529 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {

532 continue;

534 if (Reg != FoldAsLoadDefReg)

535 continue;

536

538 return nullptr;

540 }

541 if (SrcOperandIds.empty())

542 return nullptr;

543

544

546 FoldAsLoadDefReg = 0;

547 return FoldMI;

548 }

549

550 return nullptr;

551}

552

553std::pair<unsigned, unsigned>

555 switch (MI.getOpcode()) {

556 case TargetOpcode::STACKMAP:

557

558 return std::make_pair(0, StackMapOpers(&MI).getVarIdx());

559 case TargetOpcode::PATCHPOINT:

560

561

563 case TargetOpcode::STATEPOINT:

564

565 return std::make_pair(MI.getNumDefs(), StatepointOpers(&MI).getVarIdx());

566 default:

568 }

569}

570

574 unsigned StartIdx = 0;

575 unsigned NumDefs = 0;

576

577 std::tie(NumDefs, StartIdx) = TII.getPatchpointUnfoldableRange(MI);

578

579 unsigned DefToFoldIdx = MI.getNumOperands();

580

581

582

583 for (unsigned Op : Ops) {

584 if (Op < NumDefs) {

585 assert(DefToFoldIdx == MI.getNumOperands() && "Folding multiple defs");

586 DefToFoldIdx = Op;

587 } else if (Op < StartIdx) {

588 return nullptr;

589 }

590 if (MI.getOperand(Op).isTied())

591 return nullptr;

592 }

593

595 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);

597

598

599 for (unsigned i = 0; i < StartIdx; ++i)

600 if (i != DefToFoldIdx)

601 MIB.add(MI.getOperand(i));

602

603 for (unsigned i = StartIdx, e = MI.getNumOperands(); i < e; ++i) {

605 unsigned TiedTo = e;

606 (void)MI.isRegTiedToDefOperand(i, &TiedTo);

607

609 assert(TiedTo == e && "Cannot fold tied operands");

610 unsigned SpillSize;

611 unsigned SpillOffset;

612

615 bool Valid =

616 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);

617 if (!Valid)

619 MIB.addImm(StackMaps::IndirectMemRefOp);

620 MIB.addImm(SpillSize);

622 MIB.addImm(SpillOffset);

623 } else {

624 MIB.add(MO);

625 if (TiedTo < e) {

626 assert(TiedTo < NumDefs && "Bad tied operand");

627 if (TiedTo > DefToFoldIdx)

628 --TiedTo;

630 }

631 }

632 }

633 return NewMI;

634}

635

638

639 if (MI->getOperand(OpNo).isTied()) {

640 unsigned TiedTo = MI->findTiedOperandIdx(OpNo);

641 MI->untieRegOperand(OpNo);

642

644 }

645

647 TII.getFrameIndexOperands(NewOps, FI);

648 assert(!NewOps.empty() && "getFrameIndexOperands didn't create any operands");

649 MI->removeOperand(OpNo);

650 MI->insert(MI->operands_begin() + OpNo, NewOps);

651

652

653

654

659}

660

661

665 assert(MI.isInlineAsm() && "wrong opcode");

666 if (Ops.size() > 1)

667 return nullptr;

668 unsigned Op = Ops[0];

669 assert(Op && "should never be first operand");

670 assert(MI.getOperand(Op).isReg() && "shouldn't be folding non-reg operands");

671

672 if (.mayFoldInlineAsmRegOp(Op))

673 return nullptr;

674

676

678

679

687 }

691 }

698

699 return &NewMI;

700}

701

710

712 assert(MBB && "foldMemoryOperand needs an inserted instruction");

714

715

716

717

718 int64_t MemSize = 0;

720

723 } else {

726

727 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {

728 unsigned SubRegSize = TRI.getSubRegIdxSize(SubReg);

729 if (SubRegSize > 0 && !(SubRegSize % 8))

730 OpSize = SubRegSize / 8;

731 }

732

733 MemSize = std::max(MemSize, OpSize);

734 }

735 }

736

737 assert(MemSize && "Did not expect a zero-sized stack slot");

738

740

741 if (MI.getOpcode() == TargetOpcode::STACKMAP ||

742 MI.getOpcode() == TargetOpcode::PATCHPOINT ||

743 MI.getOpcode() == TargetOpcode::STATEPOINT) {

744

746 if (NewMI)

747 MBB->insert(MI, NewMI);

748 } else if (MI.isInlineAsm()) {

750 } else {

751

753 }

754

755 if (NewMI) {

757

760 "Folded a def to a non-store!");

763 "Folded a use to a non-load!");

769

770

771

773

774 return NewMI;

775 }

776

777

779 return nullptr;

780

782 if (!RC)

783 return nullptr;

784

789

790

791 BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);

792 } else {

795 }

796 } else

798

799 return &*--Pos;

800}

801

807#ifndef NDEBUG

809 assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");

810#endif

811

814

815

817 int FrameIndex = 0;

818

819 if ((MI.getOpcode() == TargetOpcode::STACKMAP ||

820 MI.getOpcode() == TargetOpcode::PATCHPOINT ||

821 MI.getOpcode() == TargetOpcode::STATEPOINT) &&

823

825 if (NewMI)

826 NewMI = &*MBB.insert(MI, NewMI);

829 } else {

830

832 }

833

834 if (!NewMI)

835 return nullptr;

836

837

838 if (MI.memoperands_empty()) {

840 } else {

841

845 I != E; ++I) {

847 }

848 }

849 return NewMI;

850}

851

852

853

854

858 --CopyMI;

859

860 Register DstReg = MI->getOperand(0).getReg();

862 CopyMI->addOperand(MO);

863

864

865

866

867

868 if (MO.isKill() && TRI->regsOverlap(DstReg, MO.getReg()))

869 CopyMI->getOperand(CopyMI->getNumOperands() - 1).setIsKill(false);

870 }

871}

872

875 if (MI->allDefsAreDead()) {

876 MI->setDesc(get(TargetOpcode::KILL));

877 return;

878 }

879

882

883 bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());

884 if (IdentityCopy || SrcMO.isUndef()) {

885

886

887 if (SrcMO.isUndef() || MI->getNumOperands() > 2) {

888

889

890 MI->setDesc(get(TargetOpcode::KILL));

891 return;

892 }

893

894 MI->eraseFromParent();

895 return;

896 }

897

902

903 if (MI->getNumOperands() > 2)

905 MI->eraseFromParent();

906}

907

913

914

915

919 MI1 = MRI.getUniqueVRegDef(Op1.getReg());

921 MI2 = MRI.getUniqueVRegDef(Op2.getReg());

922

923

925}

926

928 unsigned Opcode2) const {

929 return Opcode1 == Opcode2 || getInverseOpcode(Opcode1) == Opcode2;

930}

931

933 bool &Commuted) const {

938 unsigned Opcode = Inst.getOpcode();

939

940

941

944 if (Commuted)

946

947

948

949

950

951

952

953

954

960}

961

962

963

964

965

966

968 bool &Commuted) const {

973}

974

975

976

977

978

980 unsigned CombineOpc = 0) {

983

986

987 if ( || MI->getParent() != &MBB ||

988 (MI->getOpcode() != CombineOpc && CombineOpc != 0))

989 return false;

990

991 if ( MRI .hasOneNonDBGUse(MO.getReg()))

992 return false;

993

994 return true;

995}

996

997

998

999

1000

1001

1002

1003

1006

1007

1010 unsigned AccumulatorOpcode = CurrentInstr->getOpcode();

1011 std::optional ChainStartOpCode =

1013

1014 if (!ChainStartOpCode.has_value())

1015 return;

1016

1017

1019

1020

1021 while (CurrentInstr &&

1024 CurrentInstr = MRI.getUniqueVRegDef(CurrentInstr->getOperand(1).getReg());

1025 }

1026

1027

1028 if (CurrentInstr->getOpcode() == AccumulatorOpcode &&

1031}

1032

1033

1034

1038 return false;

1039

1042 return false;

1043

1044

1048 return false;

1049

1051 if (User->getOpcode() == Opc)

1052 return false;

1053

1054

1057

1058

1060 return false;

1061

1062

1063

1065 for (const auto &I : MBB) {

1066 if (I.getOpcode() == Opc &&

1067 !ReductionChain.contains(I.getOperand(0).getReg()))

1068 return false;

1069 }

1070

1072 return true;

1073}

1074

1075

1084

1085

1086

1088

1089 for (unsigned int i = 1; i <= (RegistersToReduce.size() / 2); i += 2) {

1090 auto RHS = RegistersToReduce[i - 1];

1091 auto LHS = RegistersToReduce[i];

1093

1094 if (RegistersToReduce.size() == 2)

1095 Dest = ResultReg;

1096

1097 else {

1098 auto NewVR = MRI.createVirtualRegister(

1100 Dest = NewVR;

1102 InstrIdxForVirtReg.insert(std::make_pair(Dest, InsInstrs.size()));

1103 }

1104

1105

1110

1113 }

1114

1115

1116

1117 if (RegistersToReduce.size() % 2 != 0)

1118 NewRegs.push_back(RegistersToReduce[RegistersToReduce.size() - 1]);

1119

1120 RegistersToReduce = NewRegs;

1121}

1122

1123

1124

1125

1126

1127

1128

1129

1130

1131

1132

1133

1134

1135

1136

1137

1138

1139

1140

1141

1142

1143

1146 bool DoRegPressureReduce) const {

1147 bool Commute;

1149

1150

1151

1152

1153 if (Commute) {

1156 } else {

1159 }

1160 return true;

1161 }

1163 return true;

1164

1165 return false;

1166}

1167

1168

1172

1178 default:

1180 }

1181}

1182

1183std::pair<unsigned, unsigned>

1189

1190

1191

1192

1193 if (AssocCommutRoot && AssocCommutPrev) {

1196 }

1197

1198

1199

1200

1201

1203 "Incorrectly matched pattern");

1204 unsigned AssocCommutOpcode = Root.getOpcode();

1206 if (!AssocCommutRoot)

1207 std::swap(AssocCommutOpcode, InverseOpcode);

1208

1209

1210

1211

1212

1213

1214

1215

1216

1217

1218

1219

1220

1221

1222

1223

1224

1225

1226

1227

1228

1229

1230

1232 default:

1235 if (!AssocCommutRoot && AssocCommutPrev)

1236 return {AssocCommutOpcode, InverseOpcode};

1237 if (AssocCommutRoot && !AssocCommutPrev)

1238 return {InverseOpcode, InverseOpcode};

1239 if (!AssocCommutRoot && !AssocCommutPrev)

1240 return {InverseOpcode, AssocCommutOpcode};

1241 break;

1243 if (!AssocCommutRoot && AssocCommutPrev)

1244 return {AssocCommutOpcode, InverseOpcode};

1245 if (AssocCommutRoot && !AssocCommutPrev)

1246 return {InverseOpcode, AssocCommutOpcode};

1247 if (!AssocCommutRoot && !AssocCommutPrev)

1248 return {InverseOpcode, InverseOpcode};

1249 break;

1251 if (!AssocCommutRoot && AssocCommutPrev)

1252 return {InverseOpcode, InverseOpcode};

1253 if (AssocCommutRoot && !AssocCommutPrev)

1254 return {AssocCommutOpcode, InverseOpcode};

1255 if (!AssocCommutRoot && !AssocCommutPrev)

1256 return {InverseOpcode, AssocCommutOpcode};

1257 break;

1259 if (!AssocCommutRoot && AssocCommutPrev)

1260 return {InverseOpcode, InverseOpcode};

1261 if (AssocCommutRoot && !AssocCommutPrev)

1262 return {InverseOpcode, AssocCommutOpcode};

1263 if (!AssocCommutRoot && !AssocCommutPrev)

1264 return {AssocCommutOpcode, InverseOpcode};

1265 break;

1266 }

1268}

1269

1270

1271

1272

1275 default:

1278 return {false, false};

1280 return {true, false};

1282 return {true, true};

1284 return {true, true};

1285 }

1286}

1287

1294 break;

1297 break;

1300 break;

1303 break;

1304 default:

1306 }

1307}

1308

1309

1310

1321

1327

1329 unsigned SubRegA = OpA.getSubReg();

1332 unsigned SubRegX = OpX.getSubReg();

1334 unsigned SubRegY = OpY.getSubReg();

1336

1338 MRI.constrainRegClass(RegA, RC);

1340 MRI.constrainRegClass(RegB, RC);

1342 MRI.constrainRegClass(RegX, RC);

1344 MRI.constrainRegClass(RegY, RC);

1346 MRI.constrainRegClass(RegC, RC);

1347

1348

1349

1350

1351 Register NewVR = MRI.createVirtualRegister(RC);

1352 unsigned SubRegNewVR = 0;

1353 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));

1354

1356 bool KillA = OpA.isKill();

1357 bool KillX = OpX.isKill();

1358 bool KillY = OpY.isKill();

1359 bool KillNewVR = true;

1360

1362

1363 if (SwapPrevOperands) {

1367 }

1368

1369 unsigned PrevFirstOpIdx, PrevSecondOpIdx;

1370 unsigned RootFirstOpIdx, RootSecondOpIdx;

1377 break;

1383 break;

1389 break;

1395 break;

1396 default:

1398 }

1399

1400

1404 MF, MF.CreateMachineInstr(MCID, MIMD.getDL(), true))

1407 };

1408

1409

1411 buildMINoImplicit(*MF, MIMetadata(Prev), TII->get(NewPrevOpc), NewVR);

1413 unsigned Idx = MO.getOperandNo();

1414

1415 if (Idx == 0)

1416 continue;

1417 if (Idx == PrevFirstOpIdx)

1419 else if (Idx == PrevSecondOpIdx)

1421 else

1422 MIB1.add(MO);

1423 }

1425

1426 if (SwapRootOperands) {

1428 std::swap(SubRegA, SubRegNewVR);

1430 }

1431

1433 buildMINoImplicit(*MF, MIMetadata(Root), TII->get(NewRootOpc), RegC);

1435 unsigned Idx = MO.getOperandNo();

1436

1437 if (Idx == 0)

1438 continue;

1439 if (Idx == RootFirstOpIdx)

1441 else if (Idx == RootSecondOpIdx)

1443 else

1444 MIB2 = MIB2.add(MO);

1445 }

1447

1448

1449

1450

1452 MIB1->setFlags(IntersectedFlags);

1457

1458 MIB2->setFlags(IntersectedFlags);

1463

1465

1466

1471

1472

1473

1474

1475

1476

1477

1478

1479

1482}

1483

1493

1499

1500

1505

1506

1508 return;

1509

1511 InstIdxForVirtReg);

1512 break;

1513 }

1517 unsigned int Depth = ChainRegs.size();

1519 "Max accumulator width set to illegal value");

1523

1524

1526

1527 if (IndexedReg.index() == 0)

1528 continue;

1529

1530

1531 MachineInstr *Instr = MRI.getUniqueVRegDef(IndexedReg.value());

1534 if (IndexedReg.index() < MaxWidth) {

1535

1536 AccReg = Instr->getOperand(0).getReg();

1538

1540 .addReg(Instr->getOperand(2).getReg(),

1542 .addReg(Instr->getOperand(3).getReg(),

1544 } else {

1545

1546

1547 AccReg = Instr->getOperand(0).getReg() == Root.getOperand(0).getReg()

1548 ? MRI.createVirtualRegister(

1550 : Instr->getOperand(0).getReg();

1551 assert(IndexedReg.index() >= MaxWidth);

1552 auto AccumulatorInput =

1553 ChainRegs[Depth - (IndexedReg.index() - MaxWidth) - 1];

1555 AccReg)

1557 .addReg(Instr->getOperand(2).getReg(),

1559 .addReg(Instr->getOperand(3).getReg(),

1561 }

1562

1563 MIB->setFlags(Instr->getFlags());

1564 InstIdxForVirtReg.insert(std::make_pair(AccReg, InsInstrs.size()));

1567 }

1568

1570 for (unsigned i = (InsInstrs.size() - MaxWidth); i < InsInstrs.size();

1571 ++i) {

1572 auto Reg = InsInstrs[i]->getOperand(0).getReg();

1573 RegistersToReduce.push_back(Reg);

1574 }

1575

1576 while (RegistersToReduce.size() > 1)

1579

1580 break;

1581 }

1582 }

1583}

1584

1588

1593

1594

1595 if (.getNumOperands() || .getOperand(0).isReg())

1596 return false;

1597 Register DefReg = MI.getOperand(0).getReg();

1598

1599

1600

1601

1602

1603 if (DefReg.isVirtual() && MI.getOperand(0).getSubReg() &&

1604 MI.readsVirtualRegister(DefReg))

1605 return false;

1606

1607

1608

1609

1610 int FrameIdx = 0;

1613 return true;

1614

1615

1616 if (MI.isNotDuplicable() || MI.mayStore() || MI.mayRaiseFPException() ||

1617 MI.hasUnmodeledSideEffects())

1618 return false;

1619

1620

1621

1622 if (MI.isInlineAsm())

1623 return false;

1624

1625

1626 if (MI.mayLoad() && .isDereferenceableInvariantLoad())

1627 return false;

1628

1629

1630

1632 if (!MO.isReg()) continue;

1634 if (Reg == 0)

1635 continue;

1636

1637

1638 if (Reg.isPhysical()) {

1639 if (MO.isUse()) {

1640

1641

1642

1643 if ( MRI .isConstantPhysReg(Reg))

1644 return false;

1645 } else {

1646

1647 return false;

1648 }

1649 continue;

1650 }

1651

1652

1653

1654 if (MO.isDef() && Reg != DefReg)

1655 return false;

1656 }

1657

1658

1659 return true;

1660}

1661

1665 bool StackGrowsDown =

1667

1670

1672 return 0;

1673

1675

1676 if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||

1677 (StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))

1678 SPAdj = -SPAdj;

1679

1680 return SPAdj;

1681}

1682

1683

1684

1685

1689

1690 if (MI.isTerminator() || MI.isPosition())

1691 return true;

1692

1693

1694 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)

1695 return true;

1696

1697

1698

1699

1700

1701

1704}

1705

1706

1707

1711

1712

1719

1720

1725

1726

1732

1733

1736 bool &OffsetIsScalable, const TargetRegisterInfo * ) const {

1740 Width, &TRI) ||

1741 BaseOps.size() != 1)

1742 return false;

1743 BaseOp = BaseOps.front();

1744 return true;

1745}

1746

1747

1748

1749

1750

1751std::optional

1753 SDNode *DefNode, unsigned DefIdx,

1754 SDNode *UseNode, unsigned UseIdx) const {

1755 if (!ItinData || ItinData->isEmpty())

1756 return std::nullopt;

1757

1759 return std::nullopt;

1760

1765 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);

1766}

1767

1770 if (!ItinData || ItinData->isEmpty())

1771 return 1;

1772

1773 if (->isMachineOpcode())

1774 return 1;

1775

1777}

1778

1779

1780

1781

1782

1785 if (!ItinData || ItinData->isEmpty())

1786 return 1;

1787

1788 unsigned Class = MI.getDesc().getSchedClass();

1790 if (UOps >= 0)

1791 return UOps;

1792

1793

1794

1795 return 1;

1796}

1797

1798

1801 if (DefMI.isTransient())

1802 return 0;

1803 if (DefMI.mayLoad())

1807 return 1;

1808}

1809

1813

1816 unsigned *PredCost) const {

1817

1818

1819 if (!ItinData)

1820 return MI.mayLoad() ? 2 : 1;

1821

1823}

1824

1827 unsigned DefIdx) const {

1829 if (!ItinData || ItinData->isEmpty())

1830 return false;

1831

1832 unsigned DefClass = DefMI.getDesc().getSchedClass();

1833 std::optional DefCycle =

1835 return DefCycle && DefCycle <= 1U;

1836}

1837

1839

1840

1841

1842

1844 return false;

1845

1846

1847

1849 if (SectionPrefix &&

1850 (*SectionPrefix == "unlikely" || *SectionPrefix == "unknown")) {

1851 return false;

1852 }

1853

1854 return true;

1855}

1856

1857std::optional

1863 bool OffsetIsScalable;

1864

1865

1866

1868

1870 Register DestReg = DestSrc->Destination->getReg();

1871

1872

1873

1874

1875

1876

1877 if (Reg == DestReg)

1879

1880

1881 return std::nullopt;

1883 Register SrcReg = RegImm->Reg;

1884 Offset = RegImm->Imm;

1887 } else if (MI.hasOneMemOperand()) {

1888

1889

1890

1894

1895

1896

1897 if (!PSV || PSV->mayAlias(&MFI))

1898 return std::nullopt;

1899

1902 return std::nullopt;

1903

1904

1905 if (OffsetIsScalable)

1906 return std::nullopt;

1907

1908

1909

1910

1911

1912

1913

1914 if (MI.getNumExplicitDefs() != 1)

1915 return std::nullopt;

1916

1917

1918

1921 Ops.push_back(dwarf::DW_OP_deref_size);

1923 : ~UINT64_C(0));

1926 }

1927

1928 return std::nullopt;

1929}

1930

1931

1933

1939 return 0;

1940 }

1941

1942

1943

1944 return MBB->getCallFrameSize();

1945}

1946

1947

1948

1951 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {

1952 unsigned DefClass = DefMI.getDesc().getSchedClass();

1953 unsigned UseClass = UseMI.getDesc().getSchedClass();

1954 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);

1955}

1956

1960 assert((MI.isRegSequence() ||

1961 MI.isRegSequenceLike()) && "Instruction do not have the proper type");

1962

1963 if (.isRegSequence())

1965

1966

1967

1968 assert(DefIdx == 0 && "REG_SEQUENCE only has one def");

1969 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;

1973 continue;

1976 "One of the subindex of the reg_sequence is not an immediate");

1977

1979 (unsigned)MOSubIdx.getImm()));

1980 }

1981 return true;

1982}

1983

1987 assert((MI.isExtractSubreg() ||

1988 MI.isExtractSubregLike()) && "Instruction do not have the proper type");

1989

1990 if (.isExtractSubreg())

1992

1993

1994

1995 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");

1998 return false;

2001 "The subindex of the extract_subreg is not an immediate");

2002

2006 return true;

2007}

2008

2012 assert((MI.isInsertSubreg() ||

2013 MI.isInsertSubregLike()) && "Instruction do not have the proper type");

2014

2015 if (.isInsertSubreg())

2017

2018

2019

2020 assert(DefIdx == 0 && "INSERT_SUBREG only has one def");

2023 if (MOInsertedReg.isUndef())

2024 return false;

2027 "One of the subindex of the reg_sequence is not an immediate");

2028 BaseReg.Reg = MOBaseReg.getReg();

2029 BaseReg.SubReg = MOBaseReg.getSubReg();

2030

2031 InsertedReg.Reg = MOInsertedReg.getReg();

2034 return true;

2035}

2036

2037

2041

2042 if (.isInlineAsm())

2043 return "";

2044

2045 std::string Flags;

2047

2049

2050 unsigned ExtraInfo = Op.getImm();

2051 bool First = true;

2054 OS << " ";

2056 OS << Info;

2057 }

2058

2059 return Flags;

2060 }

2061

2062 int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);

2063 if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)

2064 return "";

2065

2066 assert(Op.isImm() && "Expected flag operand to be an immediate");

2067

2068 unsigned Flag = Op.getImm();

2070 OS << F.getKindName();

2071

2072 unsigned RCID;

2073 if (.isImmKind() && .isMemKind() && F.hasRegClassConstraint(RCID))

2074 OS << ':' << TRI.getRegClassName(TRI.getRegClass(RCID));

2075

2076 if (F.isMemKind()) {

2079 }

2080

2081 unsigned TiedTo;

2082 if (F.isUseOperandTiedToDef(TiedTo))

2083 OS << " tiedto:$" << TiedTo;

2084

2085 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isRegUseKind()) &&

2086 F.getRegMayBeFolded())

2087 OS << " foldable";

2088

2089 return Flags;

2090}

2091

2093

2095 Function &F, std::vectoroutliner::Candidate &Candidates) const {

2096

2097

2098

2099

2103 F.addFnAttr(ParentFn.getFnAttribute("target-features"));

2106

2107

2109 return C.getMF()->getFunction().hasFnAttribute(Attribute::NoUnwind);

2110 }))

2111 F.addFnAttr(Attribute::NoUnwind);

2112}

2113

2117 unsigned Flags) const {

2119

2120

2121

2122 if (MI.isCFIInstruction())

2123

2125

2126

2127 if (MI.isInlineAsm())

2129

2130

2131 if (MI.isLabel())

2133

2134

2135 if (MI.isDebugInstr())

2137

2138

2139 switch (MI.getOpcode()) {

2140 case TargetOpcode::IMPLICIT_DEF:

2141 case TargetOpcode::KILL:

2142 case TargetOpcode::LIFETIME_START:

2143 case TargetOpcode::LIFETIME_END:

2145 default:

2146 break;

2147 }

2148

2149

2150 if (MI.isTerminator()) {

2151

2152 if (.getParent()->succ_empty())

2154

2155

2158 }

2159

2160

2161

2162

2163

2164

2165

2166

2167

2168

2169

2170

2171

2173

2174

2175

2176

2177 assert(!MOP.isTargetIndex() && "This isn't used quite yet!");

2178

2179

2180 assert(!MOP.isCFIIndex() && "CFI instructions handled elsewhere!");

2181

2182

2183 assert(!MOP.isFI() && "FrameIndex instructions should be gone by now!");

2184

2185 if (MOP.isMBB() || MOP.isBlockAddress() || MOP.isCPI() || MOP.isJTI())

2187 }

2188

2189

2191}

2192

2194 unsigned &Flags) const {

2195

2196

2197 auto First = MBB.getFirstNonDebugInstr();

2199 return true;

2200

2201 if (First->getOpcode() == TargetOpcode::FENTRY_CALL ||

2202 First->getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_ENTER)

2203 return false;

2204

2205

2206

2207 auto Last = MBB.getLastNonDebugInstr();

2208 if (Last->getOpcode() == TargetOpcode::PATCHABLE_RET ||

2209 Last->getOpcode() == TargetOpcode::PATCHABLE_TAIL_CALL)

2210 return false;

2211

2214 if (Last->getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_EXIT ||

2215 Last->getOpcode() == TargetOpcode::PATCHABLE_TAIL_CALL)

2216 return false;

2217 }

2218 return true;

2219}

2220

2222 return MI->isCall() || MI->hasUnmodeledSideEffects() ||

2223 (MI->hasOrderedMemoryRef() && ->isDereferenceableInvariantLoad());

2224}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

SmallVector< int16_t, MAX_SRC_OPERANDS_NUM > OperandIndices

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

DXIL Forward Handle Accesses

This file contains constants used for implementing Dwarf debug support.

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Promote Memory to Register

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx

This file defines the SmallSet class.

static bool isAsmComment(const char *Str, const MCAsmInfo &MAI)

Definition TargetInstrInfo.cpp:93

static void transferImplicitOperands(MachineInstr *MI, const TargetRegisterInfo *TRI)

transferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...

Definition TargetInstrInfo.cpp:855

static cl::opt< bool > EnableAccReassociation("acc-reassoc", cl::Hidden, cl::init(true), cl::desc("Enable reassociation of accumulation chains"))

static std::pair< bool, bool > mustSwapOperands(unsigned Pattern)

Definition TargetInstrInfo.cpp:1273

static const TargetRegisterClass * canFoldCopy(const MachineInstr &MI, const TargetInstrInfo &TII, unsigned FoldIdx)

Definition TargetInstrInfo.cpp:478

static cl::opt< unsigned int > MinAccumulatorDepth("acc-min-depth", cl::Hidden, cl::init(8), cl::desc("Minimum length of accumulator chains " "required for the optimization to kick in"))

static void foldInlineAsmMemOperand(MachineInstr *MI, unsigned OpNo, int FI, const TargetInstrInfo &TII)

Definition TargetInstrInfo.cpp:636

static cl::opt< unsigned int > MaxAccumulatorWidth("acc-max-width", cl::Hidden, cl::init(3), cl::desc("Maximum number of branches in the accumulator tree"))

static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc=0)

Definition TargetInstrInfo.cpp:979

static cl::opt< bool > DisableHazardRecognizer("disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling"))

static MachineInstr * foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, const TargetInstrInfo &TII)

Definition TargetInstrInfo.cpp:571

This file describes how to lower LLVM code to machine code.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

static LLVM_ABI void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)

Append Ops with operations to apply the Offset.

static LLVM_ABI DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)

Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...

static LLVM_ABI DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)

Prepend DIExpr with the given opcodes and optionally turn it into a stack value.

bool isLittleEndian() const

Layout endianness...

std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)

Attribute getFnAttribute(Attribute::AttrKind Kind) const

Return the attribute for the given attribute kind.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

LLVM_ABI std::optional< StringRef > getSectionPrefix() const

Get the section prefix for this global object.

bool hasSection() const

Check if this global has a custom object file section.

static std::vector< StringRef > getExtraInfoNames(unsigned ExtraInfo)

static StringRef getMemConstraintName(ConstraintCode C)

Itinerary data supplied by a subtarget to be used by a target.

std::optional< unsigned > getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const

Return the cycle for the given class and operand.

unsigned getStageLatency(unsigned ItinClassIndx) const

Return the total stage latency of the given class.

std::optional< unsigned > getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const

Compute and return the use operand latency of a given itinerary class and operand index if the value ...

const InstrItinerary * Itineraries

Array of itineraries selected.

bool isEmpty() const

Returns true if there are no itineraries.

static LocationSize precise(uint64_t Value)

TypeSize getValue() const

This class is intended to be used as a base class for asm properties and features specific to the tar...

virtual unsigned getMaxInstLength(const MCSubtargetInfo *STI=nullptr) const

Returns the maximum possible encoded instruction size in bytes.

StringRef getCommentString() const

const char * getSeparatorString() const

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

unsigned getSchedClass() const

Return the scheduling class for this instruction.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

This holds information about one operand of a machine instruction, indicating the register class for ...

static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool isImmutableObjectIndex(int ObjectIdx) const

Returns true if the specified index corresponds to an immutable object.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Function & getFunction()

Return the LLVM function that this machine code represents.

BasicBlockListType::iterator iterator

const MachineFunctionProperties & getProperties() const

Get the function properties.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const

Copy all the implicit operands from OtherMI onto this one.

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

const MachineInstrBuilder & copyMIMetadata(const MIMetadata &MIMD) const

Representation of each machine instruction.

ArrayRef< MachineMemOperand * >::iterator mmo_iterator

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

void setFlags(unsigned flags)

unsigned getNumOperands() const

Retuns the total number of operands.

void setDebugInstrNum(unsigned Num)

Set instruction number of this MachineInstr.

mmo_iterator memoperands_end() const

Access to memory operands of the instruction.

unsigned peekDebugInstrNum() const

Examine the instruction number of this MachineInstr.

LLVM_ABI void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)

Assign this MachineInstr's memory reference descriptor list.

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

bool isCFIInstruction() const

bool isNotDuplicable(QueryType Type=AnyInBundle) const

Return true if this instruction cannot be safely duplicated.

void clearFlag(MIFlag Flag)

clearFlag - Clear a MI flag.

mop_range explicit_operands()

LLVM_ABI void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

mmo_iterator memoperands_begin() const

Access to memory operands of the instruction.

LLVM_ABI void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)

Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.

LLVM_ABI bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const

Return true if this instruction is identical to Other.

LLVM_ABI const MachineFunction * getMF() const

Return the function that contains the basic block that this instruction belongs to.

ArrayRef< MachineMemOperand * > memoperands() const

Access to memory operands of the instruction.

bool mayStore(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly modify memory.

const MachineOperand & getOperand(unsigned i) const

uint32_t getFlags() const

Return the MI flags bitvector.

bool canFoldAsLoad(QueryType Type=IgnoreBundle) const

Return true for instructions that can be folded as memory operands in other instructions.

LLVM_ABI const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const

Compute the static register class constraint for operand OpIdx.

LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)

Add a MachineMemOperand to the machine instruction.

A description of a memory reference used in the backend.

LocationSize getSize() const

Return the size in bytes of the memory reference.

const PseudoSourceValue * getPseudoValue() const

Flags

Flags values. These may be or'd together.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

This class contains meta information specific to a module.

MachineOperand class - Representation of each machine instruction operand.

void setSubReg(unsigned subReg)

unsigned getSubReg() const

void setIsInternalRead(bool Val=true)

void setImm(int64_t immVal)

LLVM_ABI void setIsRenamable(bool Val=true)

bool isReg() const

isReg - Tests if this is a MO_Register operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

void setIsKill(bool Val=true)

LLVM_ABI bool isRenamable() const

isRenamable - Returns true if this register may be renamed, i.e.

void setMBB(MachineBasicBlock *MBB)

void setIsUndef(bool Val=true)

getReg - Returns the register number.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

bool isMBB() const

isMBB - Tests if this is a MO_MachineBasicBlock operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

MI-level patchpoint operands.

Special value supplied for machine level alias analysis.

virtual bool mayAlias(const MachineFrameInfo *) const

Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

Represents one node in the SelectionDAG.

bool isMachineOpcode() const

Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.

unsigned getMachineOpcode() const

This may only be called if isMachineOpcode returns true.

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

bool contains(const T &V) const

Check if the SmallSet contains the given element.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

MI-level stackmap operands.

MI-level Statepoint operands.

StringRef - Represent a constant reference to a string, i.e.

constexpr size_t size() const

size - Get the string size.

constexpr const char * data() const

data - Get a pointer to the start of the string (which may not be null terminated).

Information about stack frame layout on the target.

StackDirection getStackGrowthDirection() const

getStackGrowthDirection - Return the direction the stack grows

int alignSPAdjust(int SPAdj) const

alignSPAdjust - This method aligns the stack adjustment to the correct alignment.

virtual ~PipelinerLoopInfo()

TargetInstrInfo - Interface to description of machine instruction set.

virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...

Definition TargetInstrInfo.cpp:1728

virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const

Target-dependent implementation for foldMemoryOperand.

virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const

Compute operand latency of a def of 'Reg'.

Definition TargetInstrInfo.cpp:1825

virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const

This is an architecture-specific helper function of reassociateOps.

const TargetRegisterInfo & TRI

virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const

Return the number of u-operations the given machine instruction will be decoded to on the target cpu.

Definition TargetInstrInfo.cpp:1783

virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum) const

Given a machine instruction descriptor, returns the register class constraint for OpNum,...

Definition TargetInstrInfo.cpp:61

virtual int getSPAdjust(const MachineInstr &MI) const

Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.

Definition TargetInstrInfo.cpp:1662

virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const

Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...

Definition TargetInstrInfo.cpp:153

virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const

Convert the instruction into a predicated instruction.

Definition TargetInstrInfo.cpp:359

int16_t getOpRegClassID(const MCOperandInfo &OpInfo) const

bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const

Return true when \P Opcode1 or its inversion is equal to \P Opcode2.

Definition TargetInstrInfo.cpp:927

virtual outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const

Target-dependent implementation for getOutliningTypeImpl.

virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const

Target-dependent implementation of getInsertSubregInputs.

outliner::InstrType getOutliningType(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const

Returns how or if MIT should be outlined.

Definition TargetInstrInfo.cpp:2115

virtual bool isThroughputPattern(unsigned Pattern) const

Return true when a code sequence can improve throughput.

Definition TargetInstrInfo.cpp:1169

bool getAccumulatorReassociationPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns) const

Find chains of accumulations that can be rewritten as a tree for increased ILP.

Definition TargetInstrInfo.cpp:1035

virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const

For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...

Definition TargetInstrInfo.cpp:554

virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const

Returns true iff the routine could find two commutable operands in the given machine instruction.

Definition TargetInstrInfo.cpp:324

virtual void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const

Optional target hook to create the LLVM IR attributes for the outlined function.

Definition TargetInstrInfo.cpp:2094

bool isUnpredicatedTerminator(const MachineInstr &MI) const

Returns true if the instruction is a terminator instruction that has not been predicated.

Definition TargetInstrInfo.cpp:348

virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const

Insert a noop into the instruction stream at the specified point.

Definition TargetInstrInfo.cpp:79

void getAccumulatorChain(MachineInstr *CurrentInstr, SmallVectorImpl< Register > &Chain) const

Find the chain of accumulator instructions in \P MBB and return them in \P Chain.

Definition TargetInstrInfo.cpp:1004

bool isFrameInstr(const MachineInstr &I) const

Returns true if the argument is a frame pseudo instruction.

virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const

Target-dependent implementation of getRegSequenceInputs.

virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const

Load the specified register of the given register class from the specified stack frame index.

virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const

Compute the size in bytes and offset within a stack slot of a spilled register or subregister.

Definition TargetInstrInfo.cpp:417

virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...

Definition TargetInstrInfo.cpp:1721

virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const

If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...

Definition TargetInstrInfo.cpp:403

virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const

Return true when \P Inst has reassociable operands in the same \P MBB.

Definition TargetInstrInfo.cpp:908

virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const

Store the specified register of the given register class to the specified stack frame index.

virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const

Measure the specified inline asm to determine an approximation of its length.

Definition TargetInstrInfo.cpp:112

virtual void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstIdxForVirtReg) const

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...

Definition TargetInstrInfo.cpp:1484

virtual std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const

Produce the expression describing the MI loading a value into the physical register Reg.

Definition TargetInstrInfo.cpp:1858

void lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const

This function defines the logic to lower COPY instruction to target specific instruction(s).

Definition TargetInstrInfo.cpp:873

virtual unsigned getReduceOpcodeForAccumulator(unsigned int AccumulatorOpCode) const

Returns the opcode that should be use to reduce accumulation registers.

virtual Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const

If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...

MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const

Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...

Definition TargetInstrInfo.cpp:702

virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const

Try to remove the load by folding it to a register operand at the use.

Definition TargetInstrInfo.cpp:516

virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...

Definition TargetInstrInfo.cpp:1714

TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u, const int16_t *const RegClassByHwModeTable=nullptr)

virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const

Insert branch code into the end of the specified MachineBasicBlock.

virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const

Emit instructions to copy a pair of physical registers.

virtual unsigned getAccumulationStartOpcode(unsigned Opcode) const

Returns an opcode which defines the accumulator used by \P Opcode.

unsigned getCallFrameSetupOpcode() const

These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).

virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

Definition TargetInstrInfo.cpp:1144

virtual bool isReMaterializableImpl(const MachineInstr &MI) const

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...

Definition TargetInstrInfo.cpp:1589

virtual MCInst getNop() const

Return the noop instruction to use for a noop.

Definition TargetInstrInfo.cpp:510

unsigned getCallFrameSizeAt(MachineInstr &MI) const

Definition TargetInstrInfo.cpp:1932

virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.

Definition TargetInstrInfo.cpp:462

std::pair< unsigned, unsigned > getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root, const MachineInstr &Prev) const

Reassociation of some instructions requires inverse operations (e.g.

Definition TargetInstrInfo.cpp:1184

virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const

Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...

Definition TargetInstrInfo.cpp:2193

virtual void getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const

The returned array encodes the operand index for each parameter because the operands may be commuted;...

Definition TargetInstrInfo.cpp:1288

int64_t getFrameTotalSize(const MachineInstr &I) const

Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...

MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const

This method commutes the operands of the given machine instruction MI.

Definition TargetInstrInfo.cpp:278

virtual std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const

Definition TargetInstrInfo.cpp:1752

virtual bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert=false) const

Return true when \P Inst is both associative and commutative.

virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig) const

Re-issue the specified 'original' instruction at the specific location targeting a new destination re...

Definition TargetInstrInfo.cpp:446

void reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, ArrayRef< unsigned > OperandIndices, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const

Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.

Definition TargetInstrInfo.cpp:1311

virtual std::optional< unsigned > getInverseOpcode(unsigned Opcode) const

Return the inverse operation opcode if it exists for \P Opcode (e.g.

virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const

Insert noops into the instruction stream at the specified point.

Definition TargetInstrInfo.cpp:86

unsigned getCallFrameDestroyOpcode() const

int64_t getFrameSize(const MachineInstr &I) const

Returns size of the frame associated with the given frame instruction.

virtual bool isPredicated(const MachineInstr &MI) const

Returns true if the instruction is already predicated.

bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

Definition TargetInstrInfo.cpp:2009

virtual ~TargetInstrInfo()

virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const

Compute the instruction latency of a given instruction.

Definition TargetInstrInfo.cpp:1814

virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const

Return true if two machine instructions would produce identical values.

Definition TargetInstrInfo.cpp:455

virtual bool isAccumulationOpcode(unsigned Opcode) const

Return true when \P OpCode is an instruction which performs accumulation into one of its operand regi...

std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const

If the specific machine instruction is a instruction that moves/copies value from one register to ano...

bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const

Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...

Definition TargetInstrInfo.cpp:967

void reduceAccumulatorTree(SmallVectorImpl< Register > &RegistersToReduce, SmallVectorImpl< MachineInstr * > &InsInstrs, MachineFunction &MF, MachineInstr &Root, MachineRegisterInfo &MRI, DenseMap< Register, unsigned > &InstrIdxForVirtReg, Register ResultReg) const

Reduces branches of the accumulator tree into a single register.

Definition TargetInstrInfo.cpp:1076

virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const

Test if the given instruction should be considered a scheduling boundary.

Definition TargetInstrInfo.cpp:1686

virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const

Get zero or more base operands and the byte offset of an instruction that reads/writes memory.

virtual unsigned getPredicationCost(const MachineInstr &MI) const

Definition TargetInstrInfo.cpp:1810

virtual CombinerObjective getCombinerObjective(unsigned Pattern) const

Return the objective of a combiner pattern.

Definition TargetInstrInfo.cpp:1174

virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const

This method commutes the operands of the given machine instruction MI.

Definition TargetInstrInfo.cpp:179

virtual bool isFunctionSafeToSplit(const MachineFunction &MF) const

Return true if the function is a viable candidate for machine function splitting.

Definition TargetInstrInfo.cpp:1838

virtual MachineTraceStrategy getMachineCombinerTraceStrategy() const

Return a strategy that MachineCombiner must use when creating traces.

Definition TargetInstrInfo.cpp:1585

bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

Definition TargetInstrInfo.cpp:1957

virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const

If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...

Definition TargetInstrInfo.cpp:389

virtual bool isGlobalMemoryObject(const MachineInstr *MI) const

Returns true if MI is an instruction we are unable to reason about (like a call or something with unm...

Definition TargetInstrInfo.cpp:2221

virtual std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const

If the specific machine instruction is an instruction that adds an immediate value and a register,...

unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const

Return the default expected latency for a def based on its opcode.

Definition TargetInstrInfo.cpp:1799

static const unsigned CommuteAnyOperandIndex

virtual bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const

Return true when \P Inst has reassociable sibling.

Definition TargetInstrInfo.cpp:932

virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const

Definition TargetInstrInfo.cpp:2038

virtual bool isHighLatencyDef(int opc) const

Return true if this opcode has high latency to its result.

static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)

Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...

Definition TargetInstrInfo.cpp:293

bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

Definition TargetInstrInfo.cpp:1984

virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const

Target-dependent implementation of getExtractSubregInputs.

bool usePreRAHazardRecognizer() const

Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.

Definition TargetInstrInfo.cpp:1708

bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const

Get the base operand and byte offset of an instruction that reads/writes memory.

Definition TargetInstrInfo.cpp:1734

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

const Triple & getTargetTriple() const

bool contains(Register Reg) const

Return true if the specified register is included in this register class.

bool hasSubClassEq(const TargetRegisterClass *RC) const

Returns true if RC is a sub-class of or equal to this class.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Provide an instruction scheduling machine model to CodeGen passes.

const InstrItineraryData * getInstrItineraries() const

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const TargetFrameLowering * getFrameLowering() const

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetLowering * getTargetLowering() const

bool isOSDarwin() const

Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, DriverKit, XROS, or bridgeOS).

A raw_ostream that writes to an std::string.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Tail

Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...

@ C

The default llvm calling convention, compatible with C.

@ Define

initializer< Ty > init(const Ty &Val)

InstrType

Represents how an instruction should be mapped by the outliner.

This is an optimization pass for GlobalISel generic memory operations.

MachineTraceStrategy

Strategies for selecting traces.

@ TS_MinInstrCount

Select the trace through a block that has the fewest instructions.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

auto enumerate(FirstRange &&First, RestRanges &&...Rest)

Given two or more input ranges, returns a new range whose values are tuples (A, B,...

constexpr from_range_t from_range

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

bool isa_and_nonnull(const Y &Val)

unsigned Log2_32(uint32_t Value)

Return the floor log base 2 of the specified value, -1 if the value is zero.

auto reverse(ContainerTy &&C)

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

CombinerObjective

The combiner's goal may differ based on which pattern it is attempting to optimize.

LLVM_ABI VirtRegInfo AnalyzeVirtRegInBundle(MachineInstr &MI, Register Reg, SmallVectorImpl< std::pair< MachineInstr *, unsigned > > *Ops=nullptr)

AnalyzeVirtRegInBundle - Analyze how the current instruction or bundle uses a virtual register.

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

unsigned getKillRegState(bool B)

DWARFExpression::Operation Op

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

bool isSpace(char C)

Checks whether character C is whitespace in the "C" locale.

std::pair< MachineOperand, DIExpression * > ParamLoadedValue

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

Machine model for scheduling, bundling, and heuristics.

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

A pair composed of a pair of a register and a sub-register index, and another sub-register index.

A pair composed of a register and a sub-register index.

VirtRegInfo - Information about a virtual register used by a set of operands.

bool Reads

Reads - One of the operands read the virtual register.

bool Writes

Writes - One of the operands writes the virtual register.

An individual sequence of instructions to be replaced with a call to an outlined function.

MachineFunction * getMF() const