LLVM: include/llvm/CodeGen/TargetInstrInfo.h Source File (original) (raw)
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13#ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14#define LLVM_CODEGEN_TARGETINSTRINFO_H
15
36#include
37#include
38#include
39#include
40#include
41#include
42
43namespace llvm {
44
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94
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112
113
115protected:
117
118
119
120
122
124 unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u,
125 unsigned ReturnOpcode = ~0u,
126 const int16_t *const RegClassByHwModeTable = nullptr)
128 CallFrameSetupOpcode(CFSetupOpcode),
129 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
130 ReturnOpcode(ReturnOpcode) {}
131
132public:
136
138
140 return Opc <= TargetOpcode::GENERIC_OP_END;
141 }
142
144 return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
145 Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
146 }
147
148
149
150
151
152
153
155 if (OpInfo.isLookupRegClassByHwMode())
157 return OpInfo.RegClass;
158 }
159
160
161
163 unsigned OpNum) const;
164
165
166
167 virtual bool isGlobalMemoryObject(const MachineInstr *MI) const;
168
169
170
171
172
173
176 return false;
178 if (MO.getReg().isVirtual())
179 return false;
180 }
181 return true;
182 }
183
184
185
186
188 return (MI.getOpcode() == TargetOpcode::IMPLICIT_DEF &&
189 MI.getNumOperands() == 1) ||
191 }
192
193
194
198
203
204
205
209
210protected:
211
212
213
214
215
216 virtual bool isReMaterializableImpl(const MachineInstr &MI) const;
217
218
219
220
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230
231
232
234 unsigned OpIdx1,
235 unsigned OpIdx2) const;
236
237
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241
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243
244
245
246
247 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
248 unsigned CommutableOpIdx1,
249 unsigned CommutableOpIdx2);
250
251public:
252
253
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260
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278
279
282 assert(I.getOperand(0).getImm() >= 0);
283 return I.getOperand(0).getImm();
284 }
285
286
287
288
291 assert(I.getOperand(1).getImm() >= 0 &&
292 "Frame size must not be negative");
294 }
296 }
297
300
301
302
303
304
305 virtual int getSPAdjust(const MachineInstr &MI) const;
306
307
308
309
310
311
313 Register &DstReg, unsigned &SubIdx) const {
314 return false;
315 }
316
317
318
319
320
321
323 int &FrameIndex) const {
324 return 0;
325 }
326
327
328
329
330
332 int &FrameIndex,
336 }
337
338
339
341 int &FrameIndex) const {
342 return 0;
343 }
344
345
346
347
348
349
350
351 virtual bool hasLoadFromStackSlot(
354
355
356
357
358
359
361 int &FrameIndex) const {
362 return 0;
363 }
364
365
366
367
368
370 int &FrameIndex,
374 }
375
376
377
379 int &FrameIndex) const {
380 return 0;
381 }
382
383
384
385
386
387
388
389 virtual bool hasStoreToStackSlot(
392
393
394
395
397 int &SrcFrameIndex) const {
398 return false;
399 }
400
401
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410
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412
413
414 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
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429
430
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432
433
435 return MI.isAsCheapAsAMove();
436 }
437
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463
466 unsigned SubIdx, const MachineInstr &Orig) const;
467
468
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493 return nullptr;
494 }
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541 unsigned &SrcOpIdx1,
542 unsigned &SrcOpIdx2) const;
543
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566
569
574 return !(*this == P);
575 }
576 };
577
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607 bool
608 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
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626 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
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646 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
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654
655 virtual bool produceSameValue(const MachineInstr &MI0,
658
659
660
662 int64_t BrOffset) const {
664 }
665
666
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672
673
674
678 const DebugLoc &DL, int64_t BrOffset = 0,
681 }
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713 bool AllowModify = false) const {
714 return true;
715 }
716
717
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719
720
721
722
729
736
737
738
739
741
743 };
744
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751
754 bool AllowModify = false) const {
755 return true;
756 }
757
758
759
760
761
762
764 int *BytesRemoved = nullptr) const {
765 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
766 }
767
768
769
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771
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785 int *BytesAdded = nullptr) const {
786 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
787 }
788
792 int *BytesAdded = nullptr) const {
794 BytesAdded);
795 }
796
797
798
799
801 public:
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826 virtual std::optional
829
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834
835
836
837
838
839
840
841
846 "Target didn't implement "
847 "PipelinerLoopInfo::createRemainingIterationsGreaterCondition!");
848 }
849
850
851
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854
856
857
858
859
860
861
863
864
865
867 };
868
869
870
871 virtual std::unique_ptr
873 return nullptr;
874 }
875
876
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887
893 unsigned Iter, unsigned MaxIter) const {
895 }
896
897
898
901
902
903
904
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911
912
913
914
916 unsigned ExtraPredCycles,
918 return false;
919 }
920
921
922
923
924
925
926
928 unsigned ExtraTCycles,
930 unsigned ExtraFCycles,
932 return false;
933 }
934
935
936
937
938
939
940
942 unsigned NumCycles,
944 return false;
945 }
946
947
948
950 unsigned NumInsts) const {
951 return 0;
952 }
953
954
955
959
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997 int &CondCycles, int &TrueCycles,
998 int &FalseCycles) const {
999 return false;
1000 }
1001
1002
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1006
1007
1008
1009
1010
1011
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1016
1021 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
1022 }
1023
1024
1025
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1034
1035
1036
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1038
1039
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1041
1044 unsigned &TrueOp, unsigned &FalseOp,
1045 bool &Optimizable) const {
1046 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
1047 return true;
1048 }
1049
1050
1051
1052
1053
1054
1055
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1057
1058
1059
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1064
1067 bool PreferFalse = false) const {
1068
1069 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
1070 }
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1088 bool RenamableDest = false,
1089 bool RenamableSrc = false) const {
1090 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
1091 }
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1103 return false;
1104 }
1105
1106
1107
1109
1110protected:
1111
1112
1113
1114
1115 virtual std::optional
1117 return std::nullopt;
1118 }
1119
1120 virtual std::optional
1122 return std::nullopt;
1123 }
1124
1125
1126
1127
1128
1129
1130
1131
1133 return false;
1134 }
1135
1136public:
1137
1138
1139
1140
1141
1142
1144 if (MI.isCopy()) {
1146 }
1148 }
1149
1150
1151
1154 return IsCopyInstr;
1156 }
1157
1160 if (!DestSrc)
1161 return false;
1162
1163 const MachineOperand *DestRegOp = DestSrc->Destination;
1166 }
1167
1168
1169
1170
1171
1174 return std::nullopt;
1175 }
1176
1177
1178
1179
1182 int64_t &ImmVal) const {
1183 return false;
1184 }
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1202 "TargetInstrInfo::storeRegToStackSlot!");
1203 }
1204
1205
1206
1207
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1210
1211
1212
1213
1214
1220 "TargetInstrInfo::loadRegFromStackSlot!");
1221 }
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1234
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1252 virtual std::pair<unsigned, unsigned>
1253 getPatchpointUnfoldableRange(const MachineInstr &MI) const;
1254
1255
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1262
1264 int FI,
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1283
1284
1285 virtual bool getMachineCombinerPatterns(MachineInstr &Root,
1287 bool DoRegPressureReduce) const;
1288
1289
1290
1291 virtual bool
1294 return false;
1295 }
1296
1297
1298 virtual void
1301
1302
1303
1304
1305 virtual bool isThroughputPattern(unsigned Pattern) const;
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1307
1308
1310
1311
1312
1313
1314
1315
1316 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1317
1318
1319
1321 bool Invert = false) const {
1322 return false;
1323 }
1324
1325
1326
1327 bool getAccumulatorReassociationPatterns(
1329
1330
1331
1332 void getAccumulatorChain(MachineInstr *CurrentInstr,
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1335
1336
1338
1339
1344
1345
1346 virtual unsigned
1351
1352
1359
1360
1361
1363 return std::nullopt;
1364 }
1365
1366
1367 bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
1368
1369
1370 virtual bool hasReassociableOperands(const MachineInstr &Inst,
1372
1373
1374 virtual bool hasReassociableSibling(const MachineInstr &Inst,
1375 bool &Commuted) const;
1376
1377
1378
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1383
1384
1385
1386
1387 virtual void genAlternativeCodeSequence(
1392
1393
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1400
1401
1402
1403
1404 virtual void
1405 getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern,
1407
1408
1409
1415
1416
1417
1418
1419
1420 std::pair<unsigned, unsigned>
1423
1424
1426
1427
1428
1432
1433
1435
1436
1438
1439
1440
1442
1443protected:
1444
1445
1446
1447
1448
1455 return nullptr;
1456 }
1457
1458
1459
1460
1461
1462
1467 return nullptr;
1468 }
1469
1470
1471
1472
1473
1474
1475
1476
1477
1481 return false;
1482 }
1483
1484
1485
1486
1487
1488
1489
1490
1491
1493 unsigned DefIdx,
1495 return false;
1496 }
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506 virtual bool
1510 return false;
1511 }
1512
1513public:
1514
1515
1516
1517 virtual bool
1519 bool UnfoldLoad, bool UnfoldStore,
1521 return false;
1522 }
1523
1526 return false;
1527 }
1528
1529
1530
1531
1532
1533
1534
1535 virtual unsigned
1537 unsigned *LoadRegIndex = nullptr) const {
1538 return 0;
1539 }
1540
1541
1542
1543
1544
1546 int64_t &Offset1,
1547 int64_t &Offset2) const {
1548 return false;
1549 }
1550
1551
1552
1553
1554
1555
1556
1557
1558
1560 int64_t Offset1, int64_t Offset2,
1561 unsigned NumLoads) const {
1562 return false;
1563 }
1564
1565
1566
1567
1568
1569
1570 bool getMemOperandWithOffset(const MachineInstr &MI,
1572 bool &OffsetIsScalable,
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1588 return false;
1589 }
1590
1591
1592
1593
1595 unsigned &BasePos,
1596 unsigned &OffsetPos) const {
1597 return false;
1598 }
1599
1600
1601
1602
1603
1604 virtual std::optional
1607 return std::nullopt;
1608 }
1609
1610
1611
1612
1613
1614
1615
1619 return false;
1620 }
1621
1622
1623
1624
1629
1630
1631
1632
1633
1634
1636 const Register NullValueReg,
1638 return false;
1639 }
1640
1641
1643 return false;
1644 }
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1663 int64_t Offset1, bool OffsetIsScalable1,
1665 int64_t Offset2, bool OffsetIsScalable2,
1666 unsigned ClusterSize,
1667 unsigned NumBytes) const {
1668 llvm_unreachable("target did not implement shouldClusterMemOps()");
1669 }
1670
1671
1672
1673 virtual bool
1677
1678
1681
1682
1685 unsigned Quantity) const;
1686
1687
1688 virtual MCInst getNop() const;
1689
1690
1692
1693
1695
1696
1697
1700 return false;
1701 }
1702
1703
1704 virtual std::string
1707
1708
1709
1710 bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1711
1712
1714 return false;
1715 }
1716
1717
1720 return false;
1721 }
1722
1723
1727 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1728 }
1729
1730
1731
1734
1735
1736
1739 return false;
1740 }
1741
1742
1743
1744
1745
1746
1747
1748
1750 std::vector &Pred,
1751 bool SkipDead) const {
1752 return false;
1753 }
1754
1755
1756
1757
1759 return MI.getDesc().isPredicable();
1760 }
1761
1762
1763
1767
1768
1769
1770
1771
1772
1778
1779
1780
1781 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1784
1785
1786
1787 virtual unsigned getInlineAsmLength(
1788 const char *Str, const MCAsmInfo &MAI,
1790
1791
1792
1796
1797
1798
1802
1803
1804
1808
1809
1810
1813 return nullptr;
1814 }
1815
1816
1817
1818 bool usePreRAHazardRecognizer() const;
1819
1820
1821
1822
1823
1825 Register &SrcReg2, int64_t &Mask,
1826 int64_t &Value) const {
1827 return false;
1828 }
1829
1830
1831
1832
1834 Register SrcReg2, int64_t Mask,
1837 return false;
1838 }
1840
1841
1842
1843
1844
1845
1846
1847
1852
1853
1854
1855
1856
1857
1858
1861 return false;
1862 }
1863
1864
1865
1866
1867
1870
1871
1872
1873
1874
1876 return Opcode <= TargetOpcode::COPY;
1877 }
1878
1879 virtual std::optional
1881 unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891 virtual std::optional
1895
1896
1897
1898
1899 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1901 unsigned *PredCost = nullptr) const;
1902
1903 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1904
1905 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1907
1908
1909 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1911
1912
1914
1915
1916
1917
1918
1919
1924 unsigned UseIdx) const {
1925 return false;
1926 }
1927
1928
1929
1930 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1932 unsigned DefIdx) const;
1933
1934
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
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1955
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1958
1959 virtual std::pair<uint16_t, uint16_t>
1961 return std::make_pair(0, 0);
1962 }
1963
1964
1965
1966
1967
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2001
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2009 virtual unsigned
2012
2013 return 0;
2014 }
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2032
2033 return 0;
2034 }
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2055
2056
2059 return nullptr;
2060 }
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073 virtual bool
2077 "MIa must load from or modify a memory location");
2079 "MIb must load from or modify a memory location");
2080 return false;
2081 }
2082
2083
2084
2086
2087
2088 return 5;
2089 }
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2105
2106
2107
2108
2109
2110
2115
2116
2117
2118 virtual std::pair<unsigned, unsigned>
2120 return std::make_pair(0u, 0u);
2121 }
2122
2123
2124
2125
2126
2127
2132
2133
2134
2135
2136
2137
2142
2143
2144
2145
2146
2147
2152
2153
2154
2155
2159
2160
2161
2162
2163
2166 return false;
2167 }
2168
2169
2170
2173 return TargetOpcode::COPY;
2174 }
2175
2176
2177
2178
2182 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
2183 .addReg(Src);
2184 }
2185
2186
2187
2188
2192 unsigned SrcSubReg,
2194 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
2195 .addReg(Src, 0, SrcSubReg);
2196 }
2197
2198
2199
2200
2201
2202 virtual std::optional<std::unique_ptroutliner::OutlinedFunction>
2205 std::vectoroutliner::Candidate &RepeatedSequenceLocs,
2206 unsigned MinRepeats) const {
2208 "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
2209 }
2210
2211
2212
2213
2214 virtual void mergeOutliningCandidateAttributes(
2215 Function &F, std::vectoroutliner::Candidate &Candidates) const;
2216
2217protected:
2218
2223 "Target didn't implement TargetInstrInfo::getOutliningTypeImpl!");
2224 }
2225
2226public:
2227
2228
2231 unsigned Flags) const;
2232
2233
2234
2236 unsigned &Flags) const;
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2252 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
2254 return {std::make_pair(MBB.begin(), MBB.end())};
2255 }
2256
2257
2261 "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
2262 }
2263
2264
2265
2266
2272 "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
2273 }
2274
2275
2276
2277
2281 bool AllowSideEffects = true) const {
2282#if 0
2283
2284
2286 "Target didn't implement TargetInstrInfo::buildClearRegister!");
2287#endif
2288 }
2289
2290
2291
2292
2293
2295 bool OutlineFromLinkOnceODRs) const {
2297 "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
2298 }
2299
2300
2302 return false;
2303 }
2304
2305
2306
2307 virtual bool isFunctionSafeToSplit(const MachineFunction &MF) const;
2308
2309
2310
2311
2315
2316
2317
2318
2319 virtual std::optional
2321
2322
2323
2324
2327 return false;
2328 }
2329
2330
2331
2333 if (!Formatter)
2334 Formatter = std::make_unique();
2335 return Formatter.get();
2336 }
2337
2338
2339
2340
2344
2345
2346
2350
2351
2353 return MI.getOperand(0);
2354 }
2355
2356
2361
2362
2363
2364
2365
2367 int64_t &Offset) const {
2368 return false;
2369 }
2370
2371
2372 unsigned getCallFrameSizeAt(MachineInstr &MI) const;
2373
2374
2375
2376
2377
2378
2380 int FI) const {
2382 }
2383
2384private:
2385 mutable std::unique_ptr Formatter;
2386 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
2387 unsigned CatchRetOpcode;
2388 unsigned ReturnOpcode;
2389};
2390
2391
2395
2398 SubRegInfo::getEmptyKey());
2399 }
2400
2403 SubRegInfo::getTombstoneKey());
2404 }
2405
2406
2407
2410 std::make_pair(Val.Reg, Val.SubReg));
2411 }
2412
2417};
2418
2419}
2420
2421#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
SmallVector< int16_t, MAX_SRC_OPERANDS_NUM > OperandIndices
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
DXIL Forward Handle Accesses
This file defines DenseMapInfo traits for DenseMap.
This file defines the DenseMap class.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Contains all data structures shared between the outliner implemented in MachineOutliner....
TargetInstrInfo::RegSubRegPair RegSubRegPair
Register const TargetRegisterInfo * TRI
Promote Memory to Register
MachineInstr unsigned OpIdx
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class is the base class for the comparison instructions.
Itinerary data supplied by a subtarget to be used by a target.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
This holds information about one operand of a machine instruction, indicating the register class for ...
MIRFormater - Interface to format MIR operand based on target.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
bool isReturn(QueryType Type=AnyInBundle) const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
bool isCall(QueryType Type=AnyInBundle) const
A description of a memory reference used in the backend.
This class contains meta information specific to a module.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
Represents one node in the SelectionDAG.
This class represents the scheduled code.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...
Object returned by analyzeLoopForPipelining.
Definition TargetInstrInfo.h:800
virtual bool isMVEExpanderSupported()
Return true if the target can expand pipelined schedule with modulo variable expansion.
Definition TargetInstrInfo.h:866
virtual ~PipelinerLoopInfo()
virtual void createRemainingIterationsGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, DenseMap< MachineInstr *, MachineInstr * > &LastStage0Insts)
Create a condition to determine if the remaining trip count for a phase is greater than TC.
Definition TargetInstrInfo.h:842
virtual void adjustTripCount(int TripCountAdjust)=0
Modify the loop such that the trip count is OriginalTC + TripCountAdjust.
virtual void disposed(LiveIntervals *LIS=nullptr)
Called when the loop is being removed.
Definition TargetInstrInfo.h:862
virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const =0
Return true if the given instruction should not be pipelined and should be ignored.
virtual void setPreheader(MachineBasicBlock *NewPreheader)=0
Called when the loop's preheader has been modified to NewPreheader.
virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS)
Return true if the proposed schedule should used.
Definition TargetInstrInfo.h:811
virtual std::optional< bool > createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond)=0
Create a condition to determine if the trip count of the loop is greater than TC, where TC is always ...
TargetInstrInfo - Interface to description of machine instruction set.
Definition TargetInstrInfo.h:114
virtual SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook which partitions MBB into outlinable ranges for instruction mapping purposes.
Definition TargetInstrInfo.h:2253
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
Definition TargetInstrInfo.h:915
virtual bool isBasicBlockPrologue(const MachineInstr &MI, Register Reg=Register()) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
Definition TargetInstrInfo.h:2164
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition TargetInstrInfo.h:1674
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
Definition TargetInstrInfo.h:763
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition TargetInstrInfo.h:872
virtual bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
Definition TargetInstrInfo.h:1749
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition TargetInstrInfo.h:1450
virtual bool canPredicatePredicatedInstr(const MachineInstr &MI) const
Assumes the instruction is already predicated and returns true if the instruction can be predicated a...
Definition TargetInstrInfo.h:1698
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Definition TargetInstrInfo.h:1429
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form.
Definition TargetInstrInfo.h:1875
virtual void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const
Insert an architecture-specific instruction to clear a register.
Definition TargetInstrInfo.h:2278
virtual void getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const
Fills in the necessary MachineOperands to refer to a frame index.
Definition TargetInstrInfo.h:2379
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition TargetInstrInfo.h:710
virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate f...
Definition TargetInstrInfo.h:2325
virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const
Definition TargetInstrInfo.h:199
const TargetRegisterInfo & TRI
Definition TargetInstrInfo.h:116
virtual std::optional< DestSourcePair > isCopyLikeInstrImpl(const MachineInstr &MI) const
Definition TargetInstrInfo.h:1121
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Definition TargetInstrInfo.h:2010
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
Definition TargetInstrInfo.h:1718
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
Definition TargetInstrInfo.h:2058
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
Definition TargetInstrInfo.h:888
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
Definition TargetInstrInfo.h:1691
bool isTriviallyReMaterializable(const MachineInstr &MI) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Definition TargetInstrInfo.h:174
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition TargetInstrInfo.h:312
virtual void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
Definition TargetInstrInfo.h:675
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
Definition TargetInstrInfo.h:2149
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
Definition TargetInstrInfo.h:1594
int16_t getOpRegClassID(const MCOperandInfo &OpInfo) const
Definition TargetInstrInfo.h:154
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
Definition TargetInstrInfo.h:1536
virtual outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const
Target-dependent implementation for getOutliningTypeImpl.
Definition TargetInstrInfo.h:2220
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
Definition TargetInstrInfo.h:752
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
Definition TargetInstrInfo.h:1507
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
Definition TargetInstrInfo.h:2301
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true,...
Definition TargetInstrInfo.h:1065
virtual bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const
Check if it's possible and beneficial to fold the addressing computation AddrI into the addressing mo...
Definition TargetInstrInfo.h:1616
virtual const MIRFormatter * getMIRFormatter() const
Return MIR formatter to format/parse MIR operands.
Definition TargetInstrInfo.h:2332
bool isReMaterializable(const MachineInstr &MI) const
Return true if the instruction would be materializable at a point in the containing function where al...
Definition TargetInstrInfo.h:187
virtual bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const
Return true if target supports reassociation of instructions in machine combiner pass to reduce regis...
Definition TargetInstrInfo.h:1292
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
Definition TargetInstrInfo.h:2112
bool isFullCopyInstr(const MachineInstr &MI) const
Definition TargetInstrInfo.h:1158
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register.
Definition TargetInstrInfo.h:2030
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
virtual bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.
Definition TargetInstrInfo.h:1635
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
Definition TargetInstrInfo.h:1935
virtual void finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const
Fix up the placeholder we may add in genAlternativeCodeSequence().
Definition TargetInstrInfo.h:1299
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
Definition TargetInstrInfo.h:1713
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of 'Reg' and a use in the current loop.
Definition TargetInstrInfo.h:1920
bool isUnspillableTerminator(const MachineInstr *MI) const
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...
Definition TargetInstrInfo.h:420
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
Definition TargetInstrInfo.h:971
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
Definition TargetInstrInfo.h:1434
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
Definition TargetInstrInfo.h:1737
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
Definition TargetInstrInfo.h:262
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
Definition TargetInstrInfo.h:2053
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
Definition TargetInstrInfo.h:1478
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const
Load the specified register of the given register class from the specified stack frame index.
Definition TargetInstrInfo.h:1215
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
Definition TargetInstrInfo.h:927
virtual int getExtendResourceLenLimit() const
The limit on resource length extension we accept in MachineCombiner Pass.
Definition TargetInstrInfo.h:1425
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Definition TargetInstrInfo.h:1812
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true,...
Definition TargetInstrInfo.h:1017
virtual bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const
For a "cheap" instruction which doesn't enable additional sinking, should MachineSink break a critica...
Definition TargetInstrInfo.h:206
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const
Sometimes, it is possible for the target to tell, even without aliasing information,...
Definition TargetInstrInfo.h:2074
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
Definition TargetInstrInfo.h:661
unsigned getReturnOpcode() const
Definition TargetInstrInfo.h:299
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const
Store the specified register of the given register class to the specified stack frame index.
Definition TargetInstrInfo.h:1197
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition TargetInstrInfo.h:195
virtual unsigned getReduceOpcodeForAccumulator(unsigned int AccumulatorOpCode) const
Returns the opcode that should be use to reduce accumulation registers.
Definition TargetInstrInfo.h:1347
virtual Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
Definition TargetInstrInfo.h:322
virtual bool shouldPostRASink(const MachineInstr &MI) const
Definition TargetInstrInfo.h:446
virtual bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const
Returns true if the two given memory operations should be scheduled adjacent.
Definition TargetInstrInfo.h:1662
virtual unsigned getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const
Allows targets to use appropriate copy instruction while spilitting live range of a register in regis...
Definition TargetInstrInfo.h:2171
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient.
Definition TargetInstrInfo.h:1833
virtual unsigned getMemOperandAACheckLimit() const
Return the maximal number of alias checks on memory operands.
Definition TargetInstrInfo.h:2104
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
Definition TargetInstrInfo.h:2294
virtual bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const
Return true if the MachineBasicBlock can safely be split to the cold section.
Definition TargetInstrInfo.h:2312
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
Definition TargetInstrInfo.h:2258
TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u, const int16_t *const RegClassByHwModeTable=nullptr)
Definition TargetInstrInfo.h:123
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
Definition TargetInstrInfo.h:1559
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
Definition TargetInstrInfo.h:781
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const
Emit instructions to copy a pair of physical registers.
Definition TargetInstrInfo.h:1085
virtual unsigned getAccumulationStartOpcode(unsigned Opcode) const
Returns an opcode which defines the accumulator used by \P Opcode.
Definition TargetInstrInfo.h:1340
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
Definition TargetInstrInfo.h:1441
virtual bool simplifyInstruction(MachineInstr &MI) const
If possible, converts the instruction to a simplified/canonical form.
Definition TargetInstrInfo.h:559
virtual std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const
Target dependent implementation to get the values constituting the address MachineInstr that is acces...
Definition TargetInstrInfo.h:1605
virtual std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const
Target-dependent implementation for IsCopyInstr.
Definition TargetInstrInfo.h:1116
virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition TargetInstrInfo.h:2179
virtual bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recor...
Definition TargetInstrInfo.h:1180
static bool isGenericOpcode(unsigned Opc)
Definition TargetInstrInfo.h:139
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
const TargetRegisterInfo & getRegisterInfo() const
Definition TargetInstrInfo.h:137
std::optional< DestSourcePair > isCopyLikeInstr(const MachineInstr &MI) const
Definition TargetInstrInfo.h:1152
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
Definition TargetInstrInfo.h:2139
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Definition TargetInstrInfo.h:258
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition TargetInstrInfo.h:1243
virtual bool isReMaterializableImpl(const MachineInstr &MI) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition TargetInstrInfo.h:378
virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition TargetInstrInfo.h:340
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
Definition TargetInstrInfo.h:1960
virtual bool optimizeCondBranch(MachineInstr &MI) const
Definition TargetInstrInfo.h:1839
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understood.
Definition TargetInstrInfo.h:879
unsigned getCatchReturnOpcode() const
Definition TargetInstrInfo.h:298
virtual unsigned getTailMergeSize(const MachineFunction &MF) const
Returns the target-specific default value for tail merging.
Definition TargetInstrInfo.h:2347
virtual InstructionUniformity getInstructionUniformity(const MachineInstr &MI) const
Return the uniformity behavior of the given instruction.
Definition TargetInstrInfo.h:2358
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition TargetInstrInfo.h:434
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
Definition TargetInstrInfo.h:2156
const int16_t *const RegClassByHwMode
Subtarget specific sub-array of MCInstrInfo's RegClassByHwModeTables (i.e.
Definition TargetInstrInfo.h:121
virtual const MachineOperand & getCalleeOperand(const MachineInstr &MI) const
Returns the callee operand from the given MI.
Definition TargetInstrInfo.h:2352
virtual Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition TargetInstrInfo.h:360
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Definition TargetInstrInfo.h:289
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
virtual bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
Definition TargetInstrInfo.h:1859
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
Definition TargetInstrInfo.h:396
virtual int getJumpTableIndex(const MachineInstr &MI) const
Return an index for MachineJumpTableInfo if insn is an indirect jump using a jump table,...
Definition TargetInstrInfo.h:1108
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert=false) const
Return true when \P Inst is both associative and commutative.
Definition TargetInstrInfo.h:1320
virtual bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index, int64_t &Offset) const
Returns true if the given MI defines a TargetIndex operand that can be tracked by their offset,...
Definition TargetInstrInfo.h:2366
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
Definition TargetInstrInfo.h:1518
virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part ...
Definition TargetInstrInfo.h:1102
virtual std::optional< std::unique_ptr< outliner::OutlinedFunction > > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Definition TargetInstrInfo.h:2203
virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition TargetInstrInfo.h:2189
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const
Insert a call to an outlined function into the program.
Definition TargetInstrInfo.h:2268
virtual std::optional< unsigned > getInverseOpcode(unsigned Opcode) const
Return the inverse operation opcode if it exists for \P Opcode (e.g.
Definition TargetInstrInfo.h:1362
unsigned getCallFrameDestroyOpcode() const
Definition TargetInstrInfo.h:259
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
Definition TargetInstrInfo.h:280
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
Definition TargetInstrInfo.h:667
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition TargetInstrInfo.h:1694
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
Definition TargetInstrInfo.h:1724
TargetInstrInfo(const TargetInstrInfo &)=delete
virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given ...
Definition TargetInstrInfo.h:956
virtual ~TargetInstrInfo()
virtual bool isAccumulationOpcode(unsigned Opcode) const
Return true when \P OpCode is an instruction which performs accumulation into one of its operand regi...
Definition TargetInstrInfo.h:1337
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
Definition TargetInstrInfo.h:268
virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
Definition TargetInstrInfo.h:949
virtual bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const
When calculate the latency of the root instruction, accumulate the latency of the sequence to the roo...
Definition TargetInstrInfo.h:1396
std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition TargetInstrInfo.h:1143
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
Definition TargetInstrInfo.h:1042
virtual Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
Definition TargetInstrInfo.h:369
virtual Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
Definition TargetInstrInfo.h:331
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Definition TargetInstrInfo.h:1584
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
Definition TargetInstrInfo.h:426
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
Definition TargetInstrInfo.h:941
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
Definition TargetInstrInfo.h:445
virtual MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
Definition TargetInstrInfo.h:490
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
Definition TargetInstrInfo.h:1968
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
Definition TargetInstrInfo.h:1758
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition TargetInstrInfo.h:2119
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it's safe to move a machine instruction that defines the specified register class.
Definition TargetInstrInfo.h:1764
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
Definition TargetInstrInfo.h:994
virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const
Return true if the given terminator MI is not expected to spill.
Definition TargetInstrInfo.h:1132
virtual std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a register,...
Definition TargetInstrInfo.h:1172
static bool isGenericAtomicRMWOpcode(unsigned Opc)
Definition TargetInstrInfo.h:143
virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const
Returns true if the target has a preference on the operands order of the given machine instruction.
Definition TargetInstrInfo.h:547
static const unsigned CommuteAnyOperandIndex
Definition TargetInstrInfo.h:500
virtual bool isSafeToMove(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Return true if it's safe to move a machine instruction.
Definition TargetInstrInfo.h:1773
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition TargetInstrInfo.h:1913
virtual MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const
Emit a load/store instruction with the same value register as MemI, but using the address from AM.
Definition TargetInstrInfo.h:1625
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
Definition TargetInstrInfo.h:1229
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
Definition TargetInstrInfo.h:2129
virtual bool shouldHoist(const MachineInstr &MI, const MachineLoop *FromLoop) const
Return false if the instruction should not be hoisted by MachineLICM.
Definition TargetInstrInfo.h:454
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Definition TargetInstrInfo.h:1492
virtual unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const
Returns the target-specific default value for tail duplication.
Definition TargetInstrInfo.h:2341
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
Definition TargetInstrInfo.h:789
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
Definition TargetInstrInfo.h:1642
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition TargetInstrInfo.h:1463
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
Definition TargetInstrInfo.h:1545
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
Definition TargetInstrInfo.h:1524
virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition TargetInstrInfo.h:1824
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...
Definition TargetInstrInfo.h:2085
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it's legal to split the given basic block at the specified instruction (i....
Definition TargetInstrInfo.h:905
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
static constexpr TypeSize getZero()
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
@ C
The default llvm calling convention, compatible with C.
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
MachineTraceStrategy
Strategies for selecting traces.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
CombinerObjective
The combiner's goal may differ based on which pattern it is attempting to optimize.
CodeGenOptLevel
Code generation optimization level.
DWARFExpression::Operation Op
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition TargetInstrInfo.h:73
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
@ Default
The result values are uniform if and only if all operands are uniform.
GenericCycleInfo< MachineSSAContext > MachineCycleInfo
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
Definition TargetInstrInfo.h:2408
DenseMapInfo< Register > RegInfo
Definition TargetInstrInfo.h:2393
DenseMapInfo< unsigned > SubRegInfo
Definition TargetInstrInfo.h:2394
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
Definition TargetInstrInfo.h:2401
static TargetInstrInfo::RegSubRegPair getEmptyKey()
Definition TargetInstrInfo.h:2396
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
Definition TargetInstrInfo.h:2413
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition TargetInstrInfo.h:75
const MachineOperand * Source
Definition TargetInstrInfo.h:77
DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
Definition TargetInstrInfo.h:79
const MachineOperand * Destination
Definition TargetInstrInfo.h:76
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
Definition TargetInstrInfo.h:95
Register BaseReg
Definition TargetInstrInfo.h:102
Register ScaledReg
Definition TargetInstrInfo.h:103
Formula Form
Definition TargetInstrInfo.h:106
int64_t Displacement
Definition TargetInstrInfo.h:105
int64_t Scale
Definition TargetInstrInfo.h:104
Formula
Definition TargetInstrInfo.h:96
@ Basic
Definition TargetInstrInfo.h:97
@ ZExtScaledReg
Definition TargetInstrInfo.h:99
@ SExtScaledReg
Definition TargetInstrInfo.h:98
Machine model for scheduling, bundling, and heuristics.
Register Reg
Definition TargetInstrInfo.h:85
RegImmPair(Register Reg, int64_t Imm)
Definition TargetInstrInfo.h:88
int64_t Imm
Definition TargetInstrInfo.h:86
Represents a predicate at the MachineFunction level.
Definition TargetInstrInfo.h:723
bool SingleUseCondition
SingleUseCondition is true if ConditionDef is dead except for the branch(es) at the end of the basic ...
Definition TargetInstrInfo.h:740
MachineBasicBlock * TrueDest
Definition TargetInstrInfo.h:733
MachineInstr * ConditionDef
Definition TargetInstrInfo.h:735
MachineOperand RHS
Definition TargetInstrInfo.h:732
MachineBranchPredicate()=default
MachineOperand LHS
Definition TargetInstrInfo.h:731
ComparePredicate Predicate
Definition TargetInstrInfo.h:730
MachineBasicBlock * FalseDest
Definition TargetInstrInfo.h:734
ComparePredicate
Definition TargetInstrInfo.h:724
@ PRED_INVALID
Definition TargetInstrInfo.h:727
@ PRED_EQ
Definition TargetInstrInfo.h:725
@ PRED_NE
Definition TargetInstrInfo.h:726
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
Definition TargetInstrInfo.h:581
unsigned SubIdx
Definition TargetInstrInfo.h:582
RegSubRegPairAndIdx(Register Reg=Register(), unsigned SubReg=0, unsigned SubIdx=0)
Definition TargetInstrInfo.h:584
A pair composed of a register and a sub-register index.
Definition TargetInstrInfo.h:563
bool operator==(const RegSubRegPair &P) const
Definition TargetInstrInfo.h:570
unsigned SubReg
Definition TargetInstrInfo.h:565
Register Reg
Definition TargetInstrInfo.h:564
RegSubRegPair(Register Reg=Register(), unsigned SubReg=0)
Definition TargetInstrInfo.h:567
bool operator!=(const RegSubRegPair &P) const
Definition TargetInstrInfo.h:573
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.