LLVM: include/llvm/CodeGen/TargetLowering.h Source File (original) (raw)
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22#ifndef LLVM_CODEGEN_TARGETLOWERING_H
23#define LLVM_CODEGEN_TARGETLOWERING_H
24
57#include
58#include
59#include
60#include
61#include
62#include
63#include
64#include
65
66namespace llvm {
67
100
116
117
119private:
120
122 bool DstAlignCanChange;
123
124 Align DstAlign;
125
126 bool AllowOverlap;
127
128 bool IsMemset;
129 bool ZeroMemset;
130
131 bool MemcpyStrSrc;
132
133 Align SrcAlign;
134
135public:
137 Align SrcAlign, bool IsVolatile,
138 bool MemcpyStrSrc = false) {
140 Op.Size = Size;
141 Op.DstAlignCanChange = DstAlignCanChange;
142 Op.DstAlign = DstAlign;
143 Op.AllowOverlap = !IsVolatile;
144 Op.IsMemset = false;
145 Op.ZeroMemset = false;
146 Op.MemcpyStrSrc = MemcpyStrSrc;
147 Op.SrcAlign = SrcAlign;
148 return Op;
149 }
150
152 bool IsZeroMemset, bool IsVolatile) {
154 Op.Size = Size;
155 Op.DstAlignCanChange = DstAlignCanChange;
156 Op.DstAlign = DstAlign;
157 Op.AllowOverlap = !IsVolatile;
158 Op.IsMemset = true;
159 Op.ZeroMemset = IsZeroMemset;
160 Op.MemcpyStrSrc = false;
161 return Op;
162 }
163
166 assert(!DstAlignCanChange);
167 return DstAlign;
168 }
171 bool isMemset() const { return IsMemset; }
172 bool isMemcpy() const { return !IsMemset; }
174 return isMemcpy() && !DstAlignCanChange;
175 }
179 return MemcpyStrSrc;
180 }
183 return SrcAlign;
184 }
194};
195
196
197
199public:
200
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302 public:
305
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326
333
336
338
340 };
342
344 switch (Content) {
346
349
352
354 }
356 }
357
363
364
368
369protected:
370
371 void initActions();
372
373public:
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412
413 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
414
415
416
417
418
420
421
422
425 return ShiftValueTy;
426 }
427
428
429
430
432 return DL.getPointerSizeInBits(0);
433 }
434
435
436
437
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463
468
478 getVPIntrinsicMemOperandFlags(const VPIntrinsic &VPIntrin) const;
479
483
484
485
489
491 bool IsScalable) const {
492 return true;
493 }
494
495
496
498
499
500
501 unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC,
502 bool ZeroIsPoison,
504
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570 virtual bool
572 unsigned DefinedValues) const {
573 return DefinedValues < 3;
574 }
575
576
577
578
579
580 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
581
582
586
587
589
590 return false;
591 }
592
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630 return BypassSlowDivWidths;
631 }
632
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667
668
671 const Value *) const {
672
673 return {-1, -1, -1};
674 }
675
676
677
681
685
686
687
688
689
690
691
692 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
695
696
697
704
705
706
707
709 unsigned NumElem,
710 unsigned AddrSpace) const {
711 return IsZero;
712 }
713
714
715
716
720
721
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731
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782 virtual bool
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843
844 return false;
845 }
846
847
848
849
850
854
855
856
857
858
859
860
861
863 unsigned KeptBits) const {
864
865 return false;
866 }
867
868
869
870
871
872
873
874
877 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
880
881
882
883
884
886 return false;
887
888
889 if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
890 return true;
891 }
892
893
894
895
896
897 return !XC;
898 }
899
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930 EVT VT, unsigned ShiftOpc, bool MayTransformRotate,
931 const APInt &ShiftOrRotateAmt,
932 const std::optional &AndMask) const {
933 return ShiftOpc;
934 }
935
936
937
938
939
940
942
943 return true;
944 }
945
946
947
951
952
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963
964
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967
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970
972 unsigned &Cost) const {
973 return false;
974 }
975
976
977
978
979
981 Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const {
982 return false;
983 }
984
985
986
990
991
992
993
995
996
997
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1000
1001
1003 EVT VT) const;
1004
1005
1006
1007
1008 virtual
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1025 if (isVec)
1026 return BooleanVectorContents;
1027 return isFloat ? BooleanFloatContents : BooleanContents;
1028 }
1029
1033
1034
1035
1036
1037
1038
1040 EVT ValVT) const {
1042 EVT BoolVT =
1045 return DAG.getNode(ExtendCode, dl, BoolVT, Bool);
1046 }
1047
1048
1050 return SchedPreferenceInfo;
1051 }
1052
1053
1054
1055
1059
1060
1061
1063 (void)isDivergent;
1065 assert(RC && "This value type is not natively supported!");
1066 return RC;
1067 }
1068
1069
1070
1071
1073 const Value *) const {
1074 return false;
1075 }
1076
1077
1078
1079
1080
1081
1082
1083
1088
1089
1090
1092 return RepRegClassCostForVT[VT.SimpleTy];
1093 }
1094
1095
1096
1102 virtual ShiftLegalizationStrategy
1104 unsigned ExpansionFactor) const {
1105 if (ExpansionFactor == 1)
1108 }
1109
1110
1111
1112
1118
1120
1121
1123
1124 public:
1126
1128 return ValueTypeActions[VT.SimpleTy];
1129 }
1130
1132 ValueTypeActions[VT.SimpleTy] = Action;
1133 }
1134 };
1135
1137 return ValueTypeActions;
1138 }
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1155
1156
1157
1158
1159
1164 return ValueTypeActions.getTypeAction(VT);
1165 }
1166
1167
1168
1169
1170
1171
1172
1176
1177
1178
1179
1180
1183 while (true) {
1186 return VT;
1189 break;
1190 default:
1191 llvm_unreachable("Type is not legal nor is it to be expanded!");
1192 }
1193 }
1194 }
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1205 EVT &IntermediateVT,
1206 unsigned &NumIntermediates,
1207 MVT &RegisterVT) const;
1208
1209
1210
1211
1214 unsigned &NumIntermediates, MVT &RegisterVT) const {
1216 RegisterVT);
1217 }
1218
1222
1223
1225
1226
1227
1229
1232
1234
1240 };
1241
1242
1243
1244
1245
1248 unsigned ) const {
1249 return false;
1250 }
1251
1252
1253
1254
1256 bool ForCodeSize = false) const {
1257 return false;
1258 }
1259
1260
1261
1262
1263
1267
1268
1269
1270
1271
1272 virtual bool canOpTrap(unsigned Op, EVT VT) const;
1273
1274
1275
1276
1278 EVT ) const {
1279 return false;
1280 }
1281
1282
1286
1287
1288
1289
1291
1292
1293 if (Op >= std::size(OpActions[0]))
1298 }
1299
1300
1301
1302
1304 unsigned Scale) const {
1305 return false;
1306 }
1307
1308
1309
1310
1311
1313 unsigned Scale) const {
1315 if (Action != Legal)
1316 return Action;
1317
1318
1319
1320 bool Supported;
1321 switch (Op) {
1322 default:
1333 break;
1334 }
1335
1336 return Supported ? Action : Expand;
1337 }
1338
1339
1340
1342 unsigned EqOpc;
1343 switch (Op) {
1345#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1346 case ISD::STRICT_##DAGN: EqOpc = ISD::DAGN; break;
1347#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1348 case ISD::STRICT_##DAGN: EqOpc = ISD::SETCC; break;
1349#include "llvm/IR/ConstrainedOps.def"
1350 }
1351
1353 }
1354
1355
1356
1357
1358
1360 bool LegalOnly = false) const {
1361 if (LegalOnly)
1363
1364 return (VT == MVT::Other || isTypeLegal(VT)) &&
1367 }
1368
1369
1370
1371
1372
1374 bool LegalOnly = false) const {
1375 if (LegalOnly)
1377
1378 return (VT == MVT::Other || isTypeLegal(VT)) &&
1381 }
1382
1383
1384
1385
1386
1388 bool LegalOnly = false) const {
1389 if (LegalOnly)
1391
1392 return (VT == MVT::Other || isTypeLegal(VT)) &&
1396 }
1397
1398
1399
1403
1404
1407 return false;
1408
1411 }
1412
1413
1416
1417 uint64_t BW = DL.getIndexSizeInBits(0u);
1419 return Range <= BW;
1420 }
1421
1422
1423
1424 virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
1427
1428
1429 virtual MVT getPreferredSwitchConditionType(LLVMContext &Context,
1430 EVT ConditionVT) const;
1431
1432
1433
1434
1435
1436
1440
1441
1442
1443
1444
1445
1446
1448 return false;
1449
1450 unsigned NumDests = DestCmps.size();
1451 unsigned NumCmps = 0;
1452 unsigned int MaxBitTestEntry = 0;
1453 for (auto &DestCmp : DestCmps) {
1454 NumCmps += DestCmp.second;
1455 if (DestCmp.second > MaxBitTestEntry)
1456 MaxBitTestEntry = DestCmp.second;
1457 }
1458
1459
1460
1462 return false;
1463
1464
1465
1466
1467
1468
1469 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1470 (NumDests == 3 && NumCmps >= 6);
1471 }
1472
1473
1474
1475
1479
1480
1482 return (VT == MVT::Other || isTypeLegal(VT)) &&
1484 }
1485
1486
1487
1488
1490 EVT MemVT) const {
1496 unsigned Shift = 4 * ExtType;
1497 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1498 }
1499
1500
1504
1505
1506
1511
1512
1514 EVT MemVT) const {
1520 unsigned Shift = 4 * ExtType;
1522 (LegalizeAction)((AtomicLoadExtActions[ValI][MemI] >> Shift) & 0xf);
1524 "Unsupported atomic load extension action.");
1525 return Action;
1526 }
1527
1528
1529
1533
1534
1535
1536
1542 "Table isn't big enough!");
1543 return TruncStoreActions[ValI][MemI];
1544 }
1545
1546
1547
1551
1552
1553
1559
1561 bool LegalOnly) const {
1562 if (LegalOnly)
1564
1566 }
1567
1568
1569
1570
1572 return getIndexedModeAction(IdxMode, VT, IMAB_Load);
1573 }
1574
1575
1581
1582
1583
1584
1586 return getIndexedModeAction(IdxMode, VT, IMAB_Store);
1587 }
1588
1589
1595
1596
1597
1598
1600 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad);
1601 }
1602
1603
1609
1610
1611
1612
1614 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedStore);
1615 }
1616
1617
1623
1624
1625
1627
1628
1629
1631 return false;
1632 }
1633
1634
1635
1636
1639
1640
1641 if (Scale != ElemSize && Scale != 1)
1642 return false;
1643 return true;
1644 }
1645
1646
1647
1648
1651 assert((unsigned)CC < std::size(CondCodeActions) &&
1652 ((unsigned)VT.SimpleTy >> 3) < std::size(CondCodeActions[0]) &&
1653 "Table isn't big enough!");
1654
1658 assert(Action != Promote && "Can't promote condition code!");
1659 return Action;
1660 }
1661
1662
1663
1667
1668
1669
1674
1675
1676
1677
1678
1680 EVT InputVT) const {
1681 assert(Opc == ISD::PARTIAL_REDUCE_SMLA || Opc == ISD::PARTIAL_REDUCE_UMLA ||
1682 Opc == ISD::PARTIAL_REDUCE_SUMLA || Opc == ISD::PARTIAL_REDUCE_FMLA);
1685 auto It = PartialReduceMLAActions.find(Key);
1686 return It != PartialReduceMLAActions.end() ? It->second : Expand;
1687 }
1688
1689
1690
1692 EVT InputVT) const {
1694 return Action == Legal || Action == Custom;
1695 }
1696
1697
1698
1701 "This operation isn't promoted!");
1702
1703
1704 std::map<std::pair<unsigned, MVT::SimpleValueType>,
1706 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1707 if (PTTI != PromoteToType.end()) return PTTI->second;
1708
1710 "Cannot autopromote this type, add it with AddPromotedToType.");
1711
1713 MVT NVT = VT;
1714 do {
1718 "Didn't find type to promote to!");
1721 return NVT;
1722 }
1723
1725 bool AllowUnknown = false) const {
1727 }
1728
1729
1730
1731
1732
1734 bool AllowUnknown = false) const {
1735
1738
1740 Type *EltTy = VTy->getElementType();
1741
1744 EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1745 }
1747 VTy->getElementCount());
1748 }
1749
1751 }
1752
1754 bool AllowUnknown = false) const {
1755
1758
1760 Type *EltTy = VTy->getElementType();
1763 EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1764 }
1766 VTy->getElementCount());
1767 }
1768
1770 }
1771
1772
1773
1775 bool AllowUnknown = false) const {
1776 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1777 }
1778
1779
1780
1782
1783
1785 assert((unsigned)VT.SimpleTy < std::size(RegisterTypeForVT));
1786 return RegisterTypeForVT[VT.SimpleTy];
1787 }
1788
1789
1794 EVT VT1;
1795 MVT RegisterVT;
1796 unsigned NumIntermediates;
1798 NumIntermediates, RegisterVT);
1799 return RegisterVT;
1800 }
1803 }
1805 }
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818 virtual unsigned
1820 std::optional RegisterVT = std::nullopt) const {
1823 std::size(NumRegistersForVT));
1825 }
1827 EVT VT1;
1828 MVT VT2;
1829 unsigned NumIntermediates;
1831 }
1834 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1835 return (BitWidth + RegWidth - 1) / RegWidth;
1836 }
1838 }
1839
1840
1841
1842
1847
1848
1849
1850
1853 EVT VT) const {
1855 }
1856
1857
1858
1861 return DL.getABITypeAlign(ArgTy);
1862 }
1863
1864
1865
1866
1868
1869
1870
1871
1872
1873
1876 std::optional ByteOffset = std::nullopt) const {
1877
1878
1880 return false;
1881
1882 return true;
1883 }
1884
1885
1886
1888
1889
1890
1891
1895
1896
1897
1898
1900 return DL.isBigEndian() || VT == MVT::ppcf128;
1901 }
1902
1903
1904
1906 assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
1907 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1908 }
1909
1913
1914
1918
1919
1920
1921
1922
1923
1924
1928
1929
1930
1931
1932
1933
1934
1938
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1953
1957
1958
1959
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1962
1963
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1979 EVT, unsigned AddrSpace = 0, Align Alignment = Align(1),
1981 unsigned * = nullptr) const {
1982 return false;
1983 }
1984
1985
1987 LLT, unsigned AddrSpace = 0, Align Alignment = Align(1),
1989 unsigned * = nullptr) const {
1990 return false;
1991 }
1992
1993
1994
1995
1996
1997 bool allowsMemoryAccessForAlignment(
1999 unsigned AddrSpace = 0, Align Alignment = Align(1),
2001 unsigned *Fast = nullptr) const;
2002
2003
2004
2005
2006
2007 bool allowsMemoryAccessForAlignment(LLVMContext &Context,
2010 unsigned *Fast = nullptr) const;
2011
2012
2013
2014
2015
2016 virtual bool
2018 unsigned AddrSpace = 0, Align Alignment = Align(1),
2020 unsigned *Fast = nullptr) const;
2021
2022
2023
2024
2025
2028 unsigned *Fast = nullptr) const;
2029
2030
2033 unsigned *Fast = nullptr) const;
2034
2035
2036
2037
2038
2039 virtual EVT
2041 const AttributeList & ) const {
2042 return MVT::Other;
2043 }
2044
2045
2046 virtual LLT
2048 const AttributeList & ) const {
2049 return LLT();
2050 }
2051
2052
2053
2054
2055
2056
2057
2058
2060
2061
2062 virtual unsigned getMinimumJumpTableEntries() const;
2063
2064
2065 unsigned getMinimumJumpTableDensity(bool OptForSize) const;
2066
2067
2068
2069 unsigned getMaximumJumpTableSize() const;
2070
2071 virtual bool isJumpTableRelative() const;
2072
2073
2074 unsigned getMinimumBitTestCmps() const;
2075
2076
2077
2079 return StackPointerRegisterToSaveRestore;
2080 }
2081
2082
2083
2088
2089
2090
2095
2099
2100
2102 return MinStackArgumentAlignment;
2103 }
2104
2105
2107
2108
2110
2111
2112 virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const;
2113
2114
2115
2116 virtual unsigned
2118
2119
2120
2122
2123
2124
2125
2126
2128
2129
2130
2131 virtual void insertSSPDeclarations(Module &M) const;
2132
2133
2134
2135
2136 virtual Value *getSDagStackGuard(const Module &M) const;
2137
2138
2139
2140
2141
2143
2144
2145
2146
2147
2148 Function *getSSPStackGuardCheck(const Module &M) const;
2149
2150protected:
2152 bool UseTLS) const;
2153
2154public:
2155
2156 virtual Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const;
2157
2158
2159
2161
2163
2167
2168
2169
2170
2171 virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const;
2172
2173
2174
2175
2176
2178 Align & ) const {
2179 return false;
2180 }
2181
2182
2183
2184
2185
2186
2187 int InstructionOpcodeToISD(unsigned Opcode) const;
2188
2189
2190
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2204 return MaxAtomicSizeInBitsSupported;
2205 }
2206
2207
2208
2210 return MaxDivRemBitWidthSupported;
2211 }
2212
2213
2214
2216 return MaxLargeFPConvertBitWidthSupported;
2217 }
2218
2219
2220
2221
2222
2223
2224
2225
2227
2228
2230
2231
2232
2233
2235 return false;
2236 }
2237
2238
2239
2240
2245
2246
2247
2248 virtual bool
2250 return false;
2251 }
2252
2253
2254
2255
2256
2261
2262
2263
2268
2269
2270
2271
2272
2278 llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
2279 }
2280
2281
2282
2283
2286 "Generic atomicrmw expansion unimplemented on this target");
2287 }
2288
2289
2292 "Generic atomic store expansion unimplemented on this target");
2293 }
2294
2295
2298 "Generic atomic load expansion unimplemented on this target");
2299 }
2300
2301
2303 llvm_unreachable("Generic cmpxchg expansion unimplemented on this target");
2304 }
2305
2306
2307
2308
2311 "Bit test atomicrmw expansion unimplemented on this target");
2312 }
2313
2314
2315
2316
2319 "Compare arith atomicrmw expansion unimplemented on this target");
2320 }
2321
2322
2323
2324
2325
2329 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
2330 }
2331
2332
2333
2334
2335
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2366
2370
2371
2372
2373
2374
2375
2376
2377
2379
2380
2382 return IsSigned;
2383 }
2384
2385
2389
2390
2391
2395
2396
2397
2403
2404
2405
2406
2410
2411
2412
2413
2415 if (SI->getValueOperand()->getType()->isFloatingPointTy())
2418 }
2419
2420
2421
2422 virtual AtomicExpansionKind
2426
2427
2428
2433
2434
2435
2436 virtual AtomicExpansionKind
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2459 return nullptr;
2460 }
2461
2462
2463
2467
2468
2469
2470
2471
2472
2473
2474
2475
2479
2480
2481
2485
2486
2487
2488
2489
2490
2491
2492
2494 EVT VT) const {
2495
2496
2498 return false;
2499
2500
2504 }
2505
2507
2508
2509
2510
2512 return false;
2513 }
2514
2515
2516
2517
2518
2519
2522 return false;
2523 }
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2535 SDValue ConstNode) const {
2536 return true;
2537 }
2538
2539
2540
2541
2542
2543
2545 bool IsSigned) const {
2546 return false;
2547 }
2548
2549
2550
2551
2552
2553
2560
2561
2562
2563
2564
2565protected:
2566
2567
2569 BooleanContents = Ty;
2570 BooleanFloatContents = Ty;
2571 }
2572
2573
2574
2576 BooleanContents = IntTy;
2577 BooleanFloatContents = FloatTy;
2578 }
2579
2580
2581
2583 BooleanVectorContents = Ty;
2584 }
2585
2586
2588 SchedPreferenceInfo = Pref;
2589 }
2590
2591
2592 void setMinimumJumpTableEntries(unsigned Val);
2593
2594
2595
2596 void setMaximumJumpTableSize(unsigned);
2597
2598
2599 void setMinimumBitTestCmps(unsigned Val);
2600
2601
2602
2604 StackPointerRegisterToSaveRestore = R;
2605 }
2606
2607
2608
2609
2610
2612 HasExtractBitsInsn = hasExtractInsn;
2613 }
2614
2615
2616
2617
2618 void setJumpIsExpensive(bool isExpensive = true);
2619
2620
2621 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
2622 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
2623 }
2624
2625
2626
2627
2632
2633
2634
2635 virtual std::pair<const TargetRegisterClass *, uint8_t>
2637
2638
2639
2641
2642
2643
2644
2646 assert(Op < std::size(OpActions[0]) && "Table isn't big enough!");
2648 }
2653 }
2656 for (auto VT : VTs)
2658 }
2659
2660
2661
2665 MemVT.isValid() && "Table isn't big enough!");
2666 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2667 unsigned Shift = 4 * ExtType;
2670 }
2673 for (auto ExtType : ExtTypes)
2675 }
2678 for (auto MemVT : MemVTs)
2680 }
2681
2682
2683
2687 MemVT.isValid() && "Table isn't big enough!");
2688 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2689 unsigned Shift = 4 * ExtType;
2693 ((uint16_t)Action << Shift);
2694 }
2697 for (auto ExtType : ExtTypes)
2699 }
2702 for (auto MemVT : MemVTs)
2704 }
2705
2706
2707
2712
2713
2714
2715
2716
2717
2720 for (auto IdxMode : IdxModes)
2721 setIndexedModeAction(IdxMode, VT, IMAB_Load, Action);
2722 }
2723
2726 for (auto VT : VTs)
2728 }
2729
2730
2731
2732
2733
2734
2737 for (auto IdxMode : IdxModes)
2738 setIndexedModeAction(IdxMode, VT, IMAB_Store, Action);
2739 }
2740
2743 for (auto VT : VTs)
2745 }
2746
2747
2748
2749
2750
2751
2754 setIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad, Action);
2755 }
2756
2757
2758
2759
2760
2761
2764 setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action);
2765 }
2766
2767
2768
2771 for (auto CC : CCs) {
2772 assert(VT.isValid() && (unsigned)CC < std::size(CondCodeActions) &&
2773 "Table isn't big enough!");
2774 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2775
2776
2777
2779 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2780 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2781 }
2782 }
2785 for (auto VT : VTs)
2787 }
2788
2789
2790
2791
2792
2795 assert(Opc == ISD::PARTIAL_REDUCE_SMLA || Opc == ISD::PARTIAL_REDUCE_UMLA ||
2796 Opc == ISD::PARTIAL_REDUCE_SUMLA || Opc == ISD::PARTIAL_REDUCE_FMLA);
2798 "setPartialReduceMLAAction types aren't valid");
2800 PartialReduceMLAActions[Key] = Action;
2801 }
2804 for (unsigned Opc : Opcodes)
2806 }
2807
2808
2809
2810
2811
2815
2816
2817
2823 MVT DestVT) {
2827 }
2828 }
2829
2830
2831
2832
2834 for (auto NT : NTs) {
2835 assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
2836 TargetDAGCombineArray[NT >> 3] |= 1 << (NT & 7);
2837 }
2838 }
2839
2840
2842 MinFunctionAlignment = Alignment;
2843 }
2844
2845
2846
2848 PrefFunctionAlignment = Alignment;
2849 }
2850
2851
2852
2853
2856 MaxBytesForAlignment = MaxBytes;
2857 }
2858
2859
2861 MinStackArgumentAlignment = Alignment;
2862 }
2863
2864
2865
2866
2867
2869 MaxAtomicSizeInBitsSupported = SizeInBits;
2870 }
2871
2872
2873
2875 MaxDivRemBitWidthSupported = SizeInBits;
2876 }
2877
2878
2879
2881 MaxLargeFPConvertBitWidthSupported = SizeInBits;
2882 }
2883
2884
2886 MinCmpXchgSizeInBits = SizeInBits;
2887 }
2888
2889
2891 SupportsUnalignedAtomics = UnalignedSupported;
2892 }
2893
2894public:
2895
2896
2897
2898
2899
2900
2901
2902
2903
2906 Type *& ) const {
2907 return false;
2908 }
2909
2910
2911
2912
2913
2914
2915
2916
2917
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2938 Type *Ty, unsigned AddrSpace,
2940
2941
2942
2944 return false;
2945 }
2946
2947
2949 int64_t MaxOffset) const {
2950 return 0;
2951 }
2952
2953
2954
2955
2959
2960
2961
2962
2966
2967
2968
2969
2970
2972
2973
2974
2976
2977
2978 return Value == 0;
2979 }
2980
2981
2982
2983
2984
2985
2987 return nullptr;
2988 }
2989
2990
2991
2992
2997
2998
3000
3001 switch (Opcode) {
3023 case ISD::FMINNUM:
3024 case ISD::FMAXNUM:
3025 case ISD::FMINNUM_IEEE:
3026 case ISD::FMAXNUM_IEEE:
3027 case ISD::FMINIMUM:
3028 case ISD::FMAXIMUM:
3029 case ISD::FMINIMUMNUM:
3030 case ISD::FMAXIMUMNUM:
3037 return true;
3038 default: return false;
3039 }
3040 }
3041
3042
3043 virtual bool isBinOp(unsigned Opcode) const {
3044
3046 return true;
3047
3048 switch (Opcode) {
3064 return true;
3065 default:
3066 return false;
3067 }
3068 }
3069
3070
3071
3072
3073
3075 return false;
3076 }
3077
3078
3079
3080
3081
3082
3084 return false;
3085 }
3086
3092
3093
3098
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3111 switch (I->getOpcode()) {
3112 case Instruction::FPExt:
3115 return true;
3116 break;
3117 case Instruction::ZExt:
3118 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
3119 return true;
3120 break;
3121 case Instruction::SExt:
3122 break;
3123 default:
3125 }
3127 }
3128
3129
3130
3131
3132
3133
3134
3139
3140
3141
3144 return false;
3145
3146
3147 unsigned LType;
3150 else {
3153 }
3154
3156 }
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3169 return false;
3170 }
3171
3177
3178
3179
3180
3184
3185
3186
3188 return false;
3189 }
3190
3191
3192
3194
3195
3196
3197 virtual bool
3200 return false;
3201 }
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3225 Align & ) const {
3226 return false;
3227 }
3228
3229
3231
3232
3233
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3252 const APInt &GapMask) const {
3253 return false;
3254 }
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3270 const APInt &GapMask) const {
3271 return false;
3272 }
3273
3274
3275
3276
3277
3278
3279
3280
3283 return false;
3284 }
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296 virtual bool
3299 return false;
3300 }
3301
3302
3303
3304
3307 "invalid fpext types");
3308 return false;
3309 }
3310
3311
3312
3313
3315 LLT DestTy, LLT SrcTy) const {
3316 return false;
3317 }
3318
3319
3320
3321
3323 EVT DestVT, EVT SrcVT) const {
3325 "invalid fpext types");
3327 }
3328
3329
3330
3332
3333
3334
3337 return false;
3338 }
3339
3340
3341
3344 return false;
3345 }
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3359 EVT) const {
3360 return false;
3361 }
3362
3363
3364
3365
3366
3367
3368
3369
3370
3372 LLT) const {
3373 return false;
3374 }
3375
3376
3378 return false;
3379 }
3380
3381
3382
3383
3384
3386 assert((MI.getOpcode() == TargetOpcode::G_FADD ||
3387 MI.getOpcode() == TargetOpcode::G_FSUB ||
3388 MI.getOpcode() == TargetOpcode::G_FMUL) &&
3389 "unexpected node in FMAD forming combine");
3390 switch (Ty.getScalarSizeInBits()) {
3391 case 16:
3393 case 32:
3395 case 64:
3397 default:
3398 break;
3399 }
3400
3401 return false;
3402 }
3403
3404
3405
3406
3410 "unexpected node in FMAD forming combine");
3412 }
3413
3414
3415
3418 return false;
3419 }
3420
3421
3422
3423
3425 return false;
3426 }
3427
3428
3429
3430
3432 unsigned SelectOpcode,
3435 return false;
3436 }
3437
3438
3439
3440
3441
3442
3444 Type *Ty) const {
3445 return false;
3446 }
3447
3448
3449
3450
3451
3453 unsigned Index) const {
3454 return false;
3455 }
3456
3457
3458
3460 return false;
3461 }
3462
3463
3464
3465
3466
3468 return false;
3469 }
3470
3471
3472
3473
3474
3476 bool MathUsed) const {
3477
3479 return true;
3480
3481
3482
3484 return false;
3485
3486
3487
3488
3489
3490
3492 return false;
3494 }
3495
3496
3497
3499 EVT VT) const {
3500 return false;
3501 }
3502
3503
3504
3506 return false;
3507 }
3508
3509
3510
3511
3513
3514
3515
3517 return false;
3518 }
3519
3520
3521
3523 const APInt &AndMask) const {
3524 unsigned ShCt = AndMask.getBitWidth() - 1;
3526 }
3527
3528
3529
3531
3532
3533
3537
3538
3540 return false;
3541 }
3542
3543
3544
3545
3546
3547
3549 return false;
3550 }
3551
3552
3553
3555 EVT PtrVT) const {
3556 return false;
3557 }
3558
3559
3561
3562
3563
3566 return false;
3567 }
3568
3569
3570
3571
3572
3573
3575 EVT ToVT) const {
3577 return Op;
3578 switch (Op) {
3582 break;
3586 break;
3587 case ISD::VP_FP_TO_UINT:
3589 return ISD::VP_FP_TO_SINT;
3590 break;
3591 default:
3592 break;
3593 }
3594 return Op;
3595 }
3596
3597
3598
3599
3604 return nullptr;
3605 }
3606
3608 return RuntimeLibcallInfo;
3609 }
3610
3612 Libcalls.setLibcallImpl(Call, Impl);
3613 }
3614
3615
3617 return Libcalls.getLibcallImpl(Call);
3618 }
3619
3620
3621
3623 return Libcalls.getLibcallName(Call);
3624 }
3625
3626
3630
3631 RTLIB::LibcallImpl getMemcpyImpl() const { return Libcalls.getMemcpyImpl(); }
3632
3633
3634
3636 return RuntimeLibcallInfo.getSupportedLibcallImpl(FuncName);
3637 }
3638
3639
3640
3641
3642 ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const;
3643
3644
3645
3647 return Libcalls.getLibcallImplCallingConv(Call);
3648 }
3649
3650
3651
3653 return Libcalls.getLibcallCallingConv(Call);
3654 }
3655
3656
3657
3658
3659
3660 virtual void finalizeLowering(MachineFunction &MF) const;
3661
3662
3663
3665
3666
3667
3668
3669
3671
3672
3673private:
3675
3676
3677
3678
3679
3680 bool HasExtractBitsInsn;
3681
3682
3683
3684
3685
3686 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
3687
3688
3689
3690
3691 bool JumpIsExpensive;
3692
3693
3694
3695 BooleanContent BooleanContents;
3696
3697
3698
3699 BooleanContent BooleanFloatContents;
3700
3701
3702
3703 BooleanContent BooleanVectorContents;
3704
3705
3706
3708
3709
3710 Align MinStackArgumentAlignment;
3711
3712
3713
3714 Align MinFunctionAlignment;
3715
3716
3717
3718 Align PrefFunctionAlignment;
3719
3720
3721 Align PrefLoopAlignment;
3722
3723 unsigned MaxBytesForAlignment;
3724
3725
3726
3727 unsigned MaxAtomicSizeInBitsSupported;
3728
3729
3730
3731 unsigned MaxDivRemBitWidthSupported;
3732
3733
3734
3735
3736 unsigned MaxLargeFPConvertBitWidthSupported;
3737
3738
3739
3740 unsigned MinCmpXchgSizeInBits;
3741
3742
3743 unsigned MinimumBitTestCmps;
3744
3745
3746 bool SupportsUnalignedAtomics;
3747
3748
3749
3750 Register StackPointerRegisterToSaveRestore;
3751
3752
3753
3757
3758
3759
3760
3761
3762
3763
3765
3766
3767
3768
3769 uint8_t RepRegClassCostForVT[MVT::VALUETYPE_SIZE];
3770
3771
3772
3773
3774
3775
3776 MVT TransformToType[MVT::VALUETYPE_SIZE];
3777
3778
3779
3780
3781
3782
3783 LegalizeAction OpActions[MVT::VALUETYPE_SIZE][ISD::BUILTIN_OP_END];
3784
3785
3786
3787
3788
3789 uint16_t LoadExtActions[MVT::VALUETYPE_SIZE][MVT::VALUETYPE_SIZE];
3790
3791
3792
3793 uint16_t AtomicLoadExtActions[MVT::VALUETYPE_SIZE][MVT::VALUETYPE_SIZE];
3794
3795
3796
3797 LegalizeAction TruncStoreActions[MVT::VALUETYPE_SIZE][MVT::VALUETYPE_SIZE];
3798
3799
3800
3801
3802
3803
3804
3805 uint16_t IndexedModeActions[MVT::VALUETYPE_SIZE][ISD::LAST_INDEXED_MODE];
3806
3807
3808
3809
3810
3811
3812
3813 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::VALUETYPE_SIZE + 7) / 8];
3814
3815 using PartialReduceActionTypes =
3816 std::tuple<unsigned, MVT::SimpleValueType, MVT::SimpleValueType>;
3817
3818
3819
3820 DenseMap<PartialReduceActionTypes, LegalizeAction> PartialReduceMLAActions;
3821
3822 ValueTypeActionImpl ValueTypeActions;
3823
3824private:
3825
3826
3827
3828 unsigned char
3829 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
3830
3831
3832
3833
3834
3835
3836
3837 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
3838 PromoteToType;
3839
3840
3841 const RTLIB::RuntimeLibcallsInfo RuntimeLibcallInfo;
3842
3843
3844 LibcallLoweringInfo Libcalls;
3845
3846
3847
3848 enum IndexedModeActionsBits {
3849 IMAB_Store = 0,
3850 IMAB_Load = 4,
3851 IMAB_MaskedStore = 8,
3852 IMAB_MaskedLoad = 12
3853 };
3854
3855 void setIndexedModeAction(unsigned IdxMode, MVT VT, unsigned Shift,
3856 LegalizeAction Action) {
3857 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
3858 (unsigned)Action < 0xf && "Table isn't big enough!");
3859 unsigned Ty = (unsigned)VT.SimpleTy;
3860 IndexedModeActions[Ty][IdxMode] &= ~(0xf << Shift);
3861 IndexedModeActions[Ty][IdxMode] |= ((uint16_t)Action) << Shift;
3862 }
3863
3864 LegalizeAction getIndexedModeAction(unsigned IdxMode, MVT VT,
3865 unsigned Shift) const {
3866 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
3867 "Table isn't big enough!");
3868 unsigned Ty = (unsigned)VT.SimpleTy;
3869 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] >> Shift) & 0xf);
3870 }
3871
3872protected:
3873
3874
3875
3877
3878
3879
3880
3881
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3895
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3910
3912
3913
3914
3915
3916
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3931
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3945
3947
3948
3949
3951
3952
3954
3955
3956
3959
3960
3961
3964
3966};
3967
3968
3969
3970
3971
3972
3974public:
3977
3980
3984
3986
3990 return false;
3991 }
3992
3993
3994
3995
3996
3997
3998
4003
4004
4005
4006
4007
4008
4009
4012 return MRI.hasOneNonDBGUse(N0);
4013 }
4014
4016 return false;
4017 }
4018
4019
4020
4021
4026 return false;
4027 }
4028
4029
4030
4031
4037 return false;
4038 }
4039
4040
4041
4042
4045 return false;
4046 }
4047
4048
4049
4050 virtual unsigned getJumpTableEncoding() const;
4051
4055
4056 virtual const MCExpr *
4060 llvm_unreachable("Need to implement this hook if target has custom JTIs");
4061 }
4062
4063
4064 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
4066
4067
4068
4069 virtual const MCExpr *
4071 unsigned JTI, MCContext &Ctx) const;
4072
4073
4074
4076
4077
4078
4079
4080
4081
4082
4083
4084 virtual bool
4086 unsigned OpNo) const {
4087 return false;
4088 }
4089
4092
4096 const SDValue OldRHS) const;
4097
4102 bool IsSignaling = false) const;
4103
4110
4117
4118
4119
4120 std::pair<SDValue, SDValue>
4121 makeLibCall(SelectionDAG &DAG, RTLIB::LibcallImpl LibcallImpl, EVT RetVT,
4124
4125
4129 const SDLoc &dl,
4132 Chain);
4133 }
4134
4135
4136
4137
4139 const uint32_t *CallerPreservedMask,
4142
4143
4144
4145
4146
4147
4148
4149
4156
4160
4163
4165 Old = O;
4167 return true;
4168 }
4169 };
4170
4171
4172
4173
4174
4175
4176 virtual bool
4177 findOptimalMemOpLowering(LLVMContext &Context, std::vector &MemOps,
4178 unsigned Limit, const MemOp &Op, unsigned DstAS,
4179 unsigned SrcAS,
4180 const AttributeList &FuncAttributes) const;
4181
4182
4183
4184
4185
4187 const APInt &DemandedElts,
4188 TargetLoweringOpt &TLO) const;
4189
4190
4192 TargetLoweringOpt &TLO) const;
4193
4194
4195
4196
4199 const APInt &DemandedElts,
4201 return false;
4202 }
4203
4204
4205
4206
4207
4210 TargetLoweringOpt &TLO) const;
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4227 TargetLoweringOpt &TLO, unsigned Depth = 0,
4228 bool AssumeSingleUse = false) const;
4229
4230
4231
4233 KnownBits &Known, TargetLoweringOpt &TLO,
4234 unsigned Depth = 0,
4235 bool AssumeSingleUse = false) const;
4236
4237
4238
4240 DAGCombinerInfo &DCI) const;
4241
4242
4243
4245 const APInt &DemandedElts,
4246 DAGCombinerInfo &DCI) const;
4247
4248
4249
4250
4252 const APInt &DemandedElts,
4254 unsigned Depth = 0) const;
4255
4256
4257
4260 unsigned Depth = 0) const;
4261
4262
4263
4265 const APInt &DemandedElts,
4267 unsigned Depth = 0) const;
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
4284 APInt &KnownUndef, APInt &KnownZero,
4285 TargetLoweringOpt &TLO, unsigned Depth = 0,
4286 bool AssumeSingleUse = false) const;
4287
4288
4289
4290 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
4291 DAGCombinerInfo &DCI) const;
4292
4293
4294
4295 virtual bool
4300
4301
4302
4303
4304
4305 virtual void computeKnownBitsForTargetNode(const SDValue Op,
4307 const APInt &DemandedElts,
4309 unsigned Depth = 0) const;
4310
4311
4312
4313
4314
4317 const APInt &DemandedElts,
4319 unsigned Depth = 0) const;
4320
4324 const APInt &DemandedElts,
4326 unsigned Depth = 0) const;
4327
4328
4329
4330
4331
4335 unsigned Depth = 0) const;
4336
4337
4338
4339
4340 virtual void computeKnownBitsForFrameIndex(int FIOp,
4343
4344
4345
4346
4347
4348 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
4349 const APInt &DemandedElts,
4351 unsigned Depth = 0) const;
4352
4353
4354
4355
4356
4357 virtual unsigned computeNumSignBitsForTargetInstr(
4360
4361
4362
4363
4364
4365
4366 virtual bool SimplifyDemandedVectorEltsForTargetNode(
4368 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
4369
4370
4371
4372
4373
4374
4375 virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
4377 const APInt &DemandedElts,
4379 TargetLoweringOpt &TLO,
4380 unsigned Depth = 0) const;
4381
4382
4383
4384
4385 virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
4388
4389
4390
4391
4392 virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(
4395
4396
4397
4398
4399 virtual bool
4400 canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts,
4402 bool ConsiderFlags, unsigned Depth) const;
4403
4404
4405
4406
4407
4411
4412
4413
4414 virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;
4415
4416
4417
4418
4419 virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
4420 const APInt &DemandedElts,
4422 bool SNaN = false,
4423 unsigned Depth = 0) const;
4424
4425
4426
4427 virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts,
4428 APInt &UndefElts,
4430 unsigned Depth = 0) const;
4431
4432
4433
4438
4439
4440
4441
4443
4448
4449 public:
4451
4454
4460
4463 bool AddTo = true);
4466 bool AddTo = true);
4467
4469
4471 };
4472
4473
4474
4476
4477
4478
4480
4481
4482 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
4483
4484
4485
4487 bool foldBooleans, DAGCombinerInfo &DCI,
4488 const SDLoc &dl) const;
4489
4490
4492
4493
4494
4495 virtual bool
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
4512
4513
4514
4515
4516
4517
4518
4519
4520
4523 SDValue ShiftLHS = N->getOperand(0);
4525 return false;
4528 return false;
4529 return true;
4530 }
4531
4532
4533
4534
4535
4536
4537
4538
4539
4541 bool IsAfterLegal) const {
4542 return true;
4543 }
4544
4545
4546
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4573
4574
4575
4576
4577
4581
4582
4583
4584
4585
4590
4591
4592
4593
4595 EVT ) const {
4596 return false;
4597 }
4598
4599
4600
4601
4603 return false;
4604 }
4605
4606
4607
4609 return false;
4610 }
4611
4612
4613
4615 return false;
4616 }
4617
4618
4620
4621
4623
4624
4625
4626
4630
4631
4632
4633
4634
4640
4641
4642
4643
4645 bool LegalOps, bool OptForSize,
4646 NegatibleCost &Cost,
4647 unsigned Depth = 0) const;
4648
4652 unsigned Depth = 0) const {
4656 if (!Neg)
4658
4660 return Neg;
4661
4662
4666 }
4667
4668
4669
4671 bool LegalOps, bool OptForSize,
4672 unsigned Depth = 0) const {
4675 }
4676
4677
4678
4680 bool OptForSize, unsigned Depth = 0) const {
4683 }
4684
4685
4686
4687
4688
4689
4690
4691
4694 unsigned NumParts, MVT PartVT, std::optionalCallingConv::ID CC) const {
4695 return false;
4696 }
4697
4698
4701 const SDValue *Parts, unsigned NumParts,
4703 std::optionalCallingConv::ID CC) const {
4705 }
4706
4707
4708
4709
4710
4717
4718
4719
4724
4727
4728
4729
4730
4735
4736
4737
4738
4739
4742
4744
4756
4757
4758
4760
4761
4763
4778
4780
4786
4788 DL = dl;
4789 return *this;
4790 }
4791
4793 Chain = InChain;
4794 return *this;
4795 }
4796
4797
4801 std::move(ArgsList));
4802 }
4803
4808 RetTy = ResultType;
4812 Args = std::move(ArgsList);
4813
4814 DAG.getTargetLoweringInfo().markLibCallAttributes(
4815 &(DAG.getMachineFunction()), CC, Args);
4816 return *this;
4817 }
4818
4822 RetTy = OrigRetTy = ResultType;
4823 IsInReg = ResultAttrs.hasAttribute(Attribute::InReg);
4824 RetSExt = ResultAttrs.hasAttribute(Attribute::SExt);
4825 RetZExt = ResultAttrs.hasAttribute(Attribute::ZExt);
4826 NoMerge = ResultAttrs.hasAttribute(Attribute::NoMerge);
4827
4829 CallConv = CC;
4830 NumFixedArgs = ArgsList.size();
4831 Args = std::move(ArgsList);
4832 return *this;
4833 }
4834
4839
4840 IsInReg = Call.hasRetAttr(Attribute::InReg);
4842 Call.doesNotReturn() ||
4846 RetSExt = Call.hasRetAttr(Attribute::SExt);
4847 RetZExt = Call.hasRetAttr(Attribute::ZExt);
4848 NoMerge = Call.hasFnAttr(Attribute::NoMerge);
4849
4851
4854 Args = std::move(ArgsList);
4855
4857
4858 return *this;
4859 }
4860
4863 return *this;
4864 }
4865
4868 return *this;
4869 }
4870
4873 return *this;
4874 }
4875
4878 return *this;
4879 }
4880
4883 return *this;
4884 }
4885
4888 return *this;
4889 }
4890
4893 return *this;
4894 }
4895
4898 return *this;
4899 }
4900
4903 return *this;
4904 }
4905
4908 return *this;
4909 }
4910
4913 return *this;
4914 }
4915
4918 return *this;
4919 }
4920
4923 return *this;
4924 }
4925
4928 return *this;
4929 }
4930
4933 return *this;
4934 }
4935
4939 };
4940
4941
4943
4944
4948
4954
4958
4961 return *this;
4962 }
4963
4966 return *this;
4967 }
4968
4971 return *this;
4972 }
4973
4976 return *this;
4977 }
4978
4983 return *this;
4984 }
4985
4986
4987
4990 return *this;
4991 }
4992 };
4993
4994
4995
4996
4997
4998 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
4999
5000
5001
5002
5003
5004
5010
5011
5013
5014
5015
5016
5021 {
5022
5023 return true;
5024 }
5025
5026
5027
5028
5030 bool ,
5033 const SDLoc & ,
5036 }
5037
5038
5039
5040
5041
5042
5044 return false;
5045 }
5046
5047
5048
5049
5051 return false;
5052 }
5053
5054
5055
5056
5061
5062
5063
5064
5065
5066
5067
5071 return VT.bitsLT(MinVT) ? MinVT : VT;
5072 }
5073
5074
5075
5076
5077 virtual bool
5079 bool isVarArg,
5081 return false;
5082 }
5083
5084
5085
5086
5087
5088 virtual bool
5090 return DL.isLittleEndian();
5091 }
5092
5093
5094
5096 return nullptr;
5097 }
5098
5099
5100
5104
5105
5106
5107
5108
5109
5110
5111
5114 return Chain;
5115 }
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130 virtual void LowerOperationWrapper(SDNode *N,
5133
5134
5135
5136
5137
5138
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5153 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
5154 }
5155
5156
5157 virtual const char *getTargetNodeName(unsigned Opcode) const;
5158
5159
5160
5163 return nullptr;
5164 }
5165
5166
5167
5168
5169
5179
5195
5196
5198
5199
5200
5202
5203
5204
5206
5207
5208
5209
5211
5212
5214
5215
5218
5219
5220
5221 LLVM_ABI bool isMatchingInputConstraint() const;
5222
5223
5224
5225 LLVM_ABI unsigned getMatchedOperand() const;
5226 };
5227
5229
5230
5231
5232
5233
5237
5238
5239
5242
5243
5244
5247
5248
5249
5250
5251
5255
5256
5258
5259 using ConstraintPair = std::pair<StringRef, TargetLowering::ConstraintType>;
5261
5262
5263
5264
5265
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277 virtual std::pair<unsigned, const TargetRegisterClass *>
5280
5283 if (ConstraintCode == "m")
5285 if (ConstraintCode == "o")
5287 if (ConstraintCode == "X")
5289 if (ConstraintCode == "p")
5292 }
5293
5294
5295
5296
5297 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
5298
5299
5300
5301 virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
5302 std::vector &Ops,
5304
5305
5308 const AsmOperandInfo &OpInfo,
5310
5311
5312
5313 virtual void CollectTargetIntrinsicOperands(const CallInst &I,
5316
5317
5318
5319
5320
5322 bool IsAfterLegalTypes,
5325 bool IsAfterLegalTypes,
5327
5331
5332
5333
5334
5335
5339
5340
5341
5342
5343
5347
5348
5349
5350
5351
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5375 int Enabled, int &RefinementSteps,
5376 bool &UseOneConstNR, bool Reciprocal) const {
5378 }
5379
5380
5381
5382
5383
5384
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5398 int Enabled, int &RefinementSteps) const {
5400 }
5401
5402
5403
5404
5405
5408
5409
5410
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430 bool expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS,
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5469
5470
5471
5472
5474
5475
5476
5477
5478
5479
5481
5482
5483
5484
5485
5488
5489
5490
5491
5492
5494
5495
5496
5497
5498
5499
5502
5503
5504
5505
5506
5507
5510
5511
5513
5514
5516
5517
5519
5520
5521
5522
5524
5525
5526
5527
5528
5529
5532
5533
5534
5535
5537
5538
5539
5540
5541
5542
5543
5547
5548
5549
5550
5551
5553
5554
5555
5557
5558
5559
5560
5561
5563
5564
5565
5566
5568
5569
5570
5571
5573 SDValue Op, unsigned NumBitsPerElt) const;
5574
5575
5576
5577
5578
5580
5581
5582
5583
5585
5586
5587
5588
5590
5591
5592
5593
5595
5596
5597
5598
5599
5600
5601
5603 bool IsNegative = false) const;
5604
5605
5606
5607
5609
5610
5611
5612
5614
5615
5616
5617
5618
5620
5621
5622
5623
5625
5626
5627
5628
5629
5631
5632
5633
5634
5636
5637
5638
5639
5640 std::pair<SDValue, SDValue> scalarizeVectorLoad(LoadSDNode *LD,
5642
5643
5644
5645
5647
5648
5649
5650 std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
5652
5653
5654
5656
5657
5658
5659
5660
5661
5662
5663
5666 bool IsCompressedMemory) const;
5667
5668
5669
5670
5671
5672
5673 SDValue getVectorElementPointer(
5676
5677
5678
5679
5680
5681
5688
5689
5690
5691
5692
5693
5694
5695
5700
5701
5702
5704
5705
5706
5708
5709
5710
5712
5713
5714
5716
5717
5718
5720
5721
5722
5723
5724
5725 SDValue expandFixedPointDiv(unsigned Opcode, const SDLoc &dl,
5728
5729
5730
5733
5734
5735
5738
5739
5740
5743
5744
5745
5746
5747
5752
5753
5754
5755
5756
5760
5761
5762
5764
5765
5767
5768
5769
5771
5772
5773
5775
5776
5777
5779
5780
5781
5783
5784
5785
5786
5787
5788
5789 bool expandMultipleResultFPLibCall(
5792 std::optional CallRetResNo = {}) const;
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816 bool LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS,
5818 SDValue EVL, bool &NeedInvert, const SDLoc &dl,
5819 SDValue &Chain, bool IsSignaling = false) const;
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833 virtual MachineBasicBlock *
5834 EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
5835
5836
5837
5838
5839
5840 virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
5841 SDNode *Node) const;
5842
5843
5844
5846
5850 }
5851
5852
5855
5856
5857
5861
5862
5863
5864
5865
5867
5868
5872
5873
5874
5876
5877
5878
5879
5880
5881
5882
5883
5884 SDValue scalarizeExtractedVectorLoad(EVT ResultVT, const SDLoc &DL,
5888
5889private:
5891 const SDLoc &DL, DAGCombinerInfo &DCI) const;
5893 const SDLoc &DL, DAGCombinerInfo &DCI) const;
5895 const SDLoc &DL, DAGCombinerInfo &DCI) const;
5896
5897 SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
5899 DAGCombinerInfo &DCI,
5901
5902
5903 SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
5905 DAGCombinerInfo &DCI, const SDLoc &DL) const;
5906
5909 DAGCombinerInfo &DCI, const SDLoc &DL,
5914
5917 DAGCombinerInfo &DCI, const SDLoc &DL,
5922};
5923
5924
5925
5926
5928 AttributeList attr,
5929 SmallVectorImplISD::OutputArg &Outs,
5930 const TargetLowering &TLI, const DataLayout &DL);
5931
5932}
5933
5934#endif
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
Atomic ordering constants.
This file contains the simple types necessary to represent the attributes associated with functions a...
block Block Frequency Analysis
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
This file defines the DenseMap class.
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Implement a low-level type suitable for MachineInstr level instruction selection.
Register const TargetRegisterInfo * TRI
Promote Memory to Register
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
static Type * getValueType(Value *V)
Returns the type of the given value/instruction V.
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
static SymbolRef::Type getType(const Symbol *Sym)
static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT, SelectionDAG &DAG)
Scalarize a vector store, bitcasting to TargetVT to determine the scalar type.
Class for arbitrary precision integers.
unsigned getBitWidth() const
Return the number of bits in the APInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
an instruction that atomically reads a memory location, combines it with another value,...
bool isFloatingPointOperation() const
BinOp getOperation() const
This class holds the attributes for a particular argument, parameter, function, or return value.
LLVM_ABI bool getValueAsBool() const
Return the attribute's value as a boolean.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
This class represents a range of values.
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
constexpr bool isScalar() const
Exactly one element.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Class to represent function types.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Common base class shared among various IRBuilders.
A wrapper class for inspecting calls to intrinsic functions.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
Represents a single loop in the control flow graph.
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
@ INVALID_SIMPLE_VALUE_TYPE
uint64_t getScalarSizeInBits() const
bool isInteger() const
Return true if this is an integer or a vector integer type.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
ElementCount getVectorElementCount() const
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
Representation of each machine instruction.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is an abstract virtual class for memory operations.
A Module instance is used to store all the information related to an LLVM module.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool hasOneUse() const
Return true if there is exactly one use of this node.
bool use_empty() const
Return true if there are no uses of this node.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
LLVM_ABI SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
const DataLayout & getDataLayout() const
LLVM_ABI void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
LLVMContext * getContext() const
This instruction constructs a fixed permutation of two input vectors.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
bool IsNoExt
Definition TargetLowering.h:311
Value * Val
Definition TargetLowering.h:303
bool IsSwiftAsync
Definition TargetLowering.h:321
bool IsSRet
Definition TargetLowering.h:313
bool IsInAlloca
Definition TargetLowering.h:317
bool IsNest
Definition TargetLowering.h:314
ArgListEntry(Value *Val, SDValue Node=SDValue())
Definition TargetLowering.h:334
Type * IndirectType
Definition TargetLowering.h:325
bool IsSExt
Definition TargetLowering.h:309
MaybeAlign Alignment
Definition TargetLowering.h:324
ArgListEntry(Value *Val, SDValue Node, Type *Ty)
Definition TargetLowering.h:327
bool IsReturned
Definition TargetLowering.h:319
bool IsZExt
Definition TargetLowering.h:310
bool IsCFGuardTarget
Definition TargetLowering.h:323
bool IsPreallocated
Definition TargetLowering.h:318
bool IsSwiftSelf
Definition TargetLowering.h:320
ArgListEntry(SDValue Node, Type *Ty)
Definition TargetLowering.h:337
SDValue Node
Definition TargetLowering.h:304
bool IsInReg
Definition TargetLowering.h:312
Type * Ty
Same as OrigTy, or partially legalized for soft float libcalls.
Definition TargetLowering.h:308
Type * OrigTy
Original unlegalized argument type.
Definition TargetLowering.h:306
bool IsByVal
Definition TargetLowering.h:315
bool IsSwiftError
Definition TargetLowering.h:322
bool IsByRef
Definition TargetLowering.h:316
Definition TargetLowering.h:1119
ValueTypeActionImpl()
Definition TargetLowering.h:1125
LegalizeTypeAction getTypeAction(MVT VT) const
Definition TargetLowering.h:1127
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition TargetLowering.h:1131
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition TargetLowering.h:198
virtual Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
Definition TargetLowering.h:2264
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition TargetLowering.h:3358
bool isOperationExpand(unsigned Op, EVT VT) const
Return true if the specified operation is illegal on this target or unlikely to be made legal with cu...
Definition TargetLowering.h:1476
EVT getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Definition TargetLowering.h:1753
virtual bool enableAggressiveFMAFusion(LLT Ty) const
Return true if target always benefits from combining into FMA for a given value type.
Definition TargetLowering.h:999
virtual void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const
Perform a bit test atomicrmw using a target-specific intrinsic.
Definition TargetLowering.h:2309
void setOperationAction(ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action)
Definition TargetLowering.h:2654
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *) const
Allows target to decide about the register class of the specific value that is live outside the defin...
Definition TargetLowering.h:1072
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition TargetLowering.h:2582
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const
Returns the size of the platform's va_list object.
Definition TargetLowering.h:1915
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition TargetLowering.h:2645
virtual bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const
Definition TargetLowering.h:959
virtual bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition TargetLowering.h:2520
void setMaxDivRemBitWidthSupported(unsigned SizeInBits)
Set the size in bits of the maximum div/rem the backend supports.
Definition TargetLowering.h:2874
virtual bool hasAndNot(SDValue X) const
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition TargetLowering.h:825
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
Definition TargetLowering.h:594
@ Enabled
Definition TargetLowering.h:597
@ Disabled
Definition TargetLowering.h:596
@ Unspecified
Definition TargetLowering.h:595
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
Definition TargetLowering.h:3950
virtual bool isShuffleMaskLegal(ArrayRef< int >, EVT) const
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition TargetLowering.h:1264
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always benefits from combining into FMA for a given value type.
Definition TargetLowering.h:994
virtual bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const
Does this target support complex deinterleaving with the given operation and type.
Definition TargetLowering.h:3564
virtual bool shouldRemoveRedundantExtend(SDValue Op) const
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...
Definition TargetLowering.h:1887
bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
Definition TargetLowering.h:1590
SDValue promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool, EVT ValVT) const
Promote the given target boolean to a target boolean of the given type.
Definition TargetLowering.h:1039
virtual bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const
Returns true if be combined with to form an ISD::FMAD.
Definition TargetLowering.h:3407
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, std::optional< unsigned > ByteOffset=std::nullopt) const
Return true if it is profitable to reduce a load to a smaller type.
Definition TargetLowering.h:1874
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
Definition TargetLowering.h:583
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
Definition TargetLowering.h:3876
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition TargetLowering.h:1733
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition TargetLowering.h:202
@ Custom
Definition TargetLowering.h:207
@ Expand
Definition TargetLowering.h:205
@ Promote
Definition TargetLowering.h:204
@ Legal
Definition TargetLowering.h:203
@ LibCall
Definition TargetLowering.h:206
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
Definition TargetLowering.h:571
LegalizeAction getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
Definition TargetLowering.h:1613
virtual bool canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOnly) const
Definition TargetLowering.h:1560
virtual bool isSelectSupported(SelectSupportKind) const
Definition TargetLowering.h:480
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition TargetLowering.h:3652
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition TargetLowering.h:3911
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual bool isEqualityCmpFoldedWithSignedCmp() const
Return true if instruction generated for equality comparison is folded with instruction generated for...
Definition TargetLowering.h:755
virtual bool preferSelectsOverBooleanArithmetic(EVT VT) const
Should we prefer selects to doing arithmetic on boolean types.
Definition TargetLowering.h:3539
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
Definition TargetLowering.h:2142
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition TargetLowering.h:2956
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
Definition TargetLowering.h:793
void setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)
Definition TargetLowering.h:2700
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition TargetLowering.h:1062
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition TargetLowering.h:3475
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
Definition TargetLowering.h:1097
@ ExpandToParts
Definition TargetLowering.h:1098
@ LowerToLibcall
Definition TargetLowering.h:1100
@ ExpandThroughStack
Definition TargetLowering.h:1099
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition TargetLowering.h:3331
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
Definition TargetLowering.h:777
virtual Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const
Create the IR node for the given complex deinterleaving operation.
Definition TargetLowering.h:3600
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition TargetLowering.h:3443
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
Definition TargetLowering.h:1303
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
Definition TargetLowering.h:2671
virtual bool shouldOptimizeMulOverflowWithZeroHighBits(LLVMContext &Context, EVT VT) const
Definition TargetLowering.h:3498
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
Definition TargetLowering.h:1056
virtual MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const
Definition TargetLowering.h:2336
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
Definition TargetLowering.h:2860
bool isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const
Return true if Load and Ext can form an ExtLoad.
Definition TargetLowering.h:3135
LegalizeTypeAction getTypeAction(MVT VT) const
Definition TargetLowering.h:1163
virtual bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const
Definition TargetLowering.h:1637
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition TargetLowering.h:1181
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition TargetLowering.h:3187
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition TargetLowering.h:2234
virtual AtomicOrdering atomicOperationOrderAfterFenceSplit(const Instruction *I) const
Definition TargetLowering.h:2242
MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition TargetLowering.h:438
virtual bool allowsMisalignedMemoryAccesses(LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
LLT handling variant.
Definition TargetLowering.h:1986
virtual bool isSafeMemOpType(MVT) const
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
Definition TargetLowering.h:2059
virtual void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const
Perform a cmpxchg expansion using a target-specific method.
Definition TargetLowering.h:2302
virtual CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) const
Definition TargetLowering.h:670
virtual ISD::NodeType getExtendForAtomicRMWArg(unsigned Op) const
Returns how the platform's atomic rmw operations expect their input argument to be extended (ZERO_EXT...
Definition TargetLowering.h:2482
const TargetMachine & getTargetMachine() const
Definition TargetLowering.h:374
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
Definition TargetLowering.h:3930
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition TargetLowering.h:1851
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.
Definition TargetLowering.h:1414
virtual bool isCtpopFast(EVT VT) const
Return true if ctpop instruction is fast.
Definition TargetLowering.h:743
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition TargetLowering.h:458
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
Definition TargetLowering.h:3917
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
Definition TargetLowering.h:3168
bool isPaddedAtMostSignificantBitsWhenStored(EVT VT) const
Indicates if any padding is guaranteed to go at the most significant bits when storing the type to me...
Definition TargetLowering.h:1892
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition TargetLowering.h:1843
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call.
Definition TargetLowering.h:2818
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition TargetLowering.h:212
@ TypePromoteInteger
Definition TargetLowering.h:214
@ TypeSoftenFloat
Definition TargetLowering.h:216
@ TypeSplitVector
Definition TargetLowering.h:219
@ TypeExpandFloat
Definition TargetLowering.h:217
@ TypeWidenVector
Definition TargetLowering.h:220
@ TypeExpandInteger
Definition TargetLowering.h:215
@ TypeScalarizeScalableVector
Definition TargetLowering.h:223
@ TypeSoftPromoteHalf
Definition TargetLowering.h:222
@ TypePromoteFloat
Definition TargetLowering.h:221
@ TypeScalarizeVector
Definition TargetLowering.h:218
@ TypeLegal
Definition TargetLowering.h:213
unsigned getMinCmpXchgSizeInBits() const
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
Definition TargetLowering.h:2226
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
Definition TargetLowering.h:2273
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
Definition TargetLowering.h:1405
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(....
Definition TargetLowering.h:966
virtual bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const
Return true if an fpext operation input to an Opcode operation is free (for instance,...
Definition TargetLowering.h:3314
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
Definition TargetLowering.h:2752
void setMaxBytesForAlignment(unsigned MaxBytes)
Definition TargetLowering.h:2855
bool isOperationLegalOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal using promotion.
Definition TargetLowering.h:1373
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
Definition TargetLowering.h:2611
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
Definition TargetLowering.h:2621
virtual bool hasBitTest(SDValue X, SDValue Y) const
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition TargetLowering.h:835
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition TargetLowering.h:1790
virtual bool needsFixedCatchObjects() const
Definition TargetLowering.h:2096
virtual Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition TargetLowering.h:2257
void setMaxLargeFPConvertBitWidthSupported(unsigned SizeInBits)
Set the size in bits of the maximum fp to/from int conversion the backend supports.
Definition TargetLowering.h:2880
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
Definition TargetLowering.h:1819
virtual bool isCheapToSpeculateCttz(Type *Ty) const
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition TargetLowering.h:728
unsigned getMinimumBitTestCmps() const
Retuen the minimum of largest number of comparisons in BitTest.
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
Definition TargetLowering.h:638
virtual bool useFPRegsForHalfType() const
Definition TargetLowering.h:559
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
Definition TargetLowering.h:1650
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
Definition TargetLowering.h:534
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
Definition TargetLowering.h:1548
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
Definition TargetLowering.h:1585
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition TargetLowering.h:2718
CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const
Get the CallingConv that should be used for the specified libcall implementation.
Definition TargetLowering.h:3646
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
Definition TargetLowering.h:1935
void setPrefLoopAlignment(Align Alignment)
Set the target's preferred loop alignment.
Definition TargetLowering.h:2854
virtual bool softPromoteHalfType() const
Definition TargetLowering.h:553
virtual bool areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const
Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
Definition TargetLowering.h:783
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
Definition TargetLowering.h:2999
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Definition TargetLowering.h:2868
virtual bool isFPImmLegal(const APFloat &, EVT, bool ForCodeSize=false) const
Returns true if the target can instruction select the specified FP immediate natively.
Definition TargetLowering.h:1255
virtual unsigned getPreferredFPToIntOpcode(unsigned Op, EVT FromVT, EVT ToVT) const
Definition TargetLowering.h:3574
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap.
Definition TargetLowering.h:3467
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Definition TargetLowering.h:2649
virtual bool optimizeFMulOrFDivAsShiftAddBitcast(SDNode *N, SDValue FPConst, SDValue IntPow2) const
Definition TargetLowering.h:912
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition TargetLowering.h:244
@ ScalarCondVectorVal
Definition TargetLowering.h:246
@ VectorMaskSelect
Definition TargetLowering.h:248
@ ScalarValSelect
Definition TargetLowering.h:245
RTLIB::LibcallImpl getMemcpyImpl() const
Definition TargetLowering.h:3631
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
Definition TargetLowering.h:1571
virtual bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
Definition TargetLowering.h:862
virtual bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance,...
Definition TargetLowering.h:3322
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition TargetLowering.h:538
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition TargetLowering.h:3083
void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Let target indicate that an extending atomic load of the specified type is legal.
Definition TargetLowering.h:2684
virtual bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const
Returns true if the index type for a masked gather/scatter requires extending.
Definition TargetLowering.h:1626
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition TargetLowering.h:1212
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X,...
Definition TargetLowering.h:2493
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition TargetLowering.h:2078
virtual StringRef getStackProbeSymbolName(const MachineFunction &MF) const
Definition TargetLowering.h:2164
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales.
Definition TargetLowering.h:1312
virtual bool preferScalarizeSplat(SDNode *N) const
Definition TargetLowering.h:953
bool isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
Definition TargetLowering.h:1604
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition TargetLowering.h:2464
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition TargetLowering.h:1049
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition TargetLowering.h:1978
virtual LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &) const
LLT returning variant.
Definition TargetLowering.h:2047
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition TargetLowering.h:2841
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
Definition TargetLowering.h:1400
virtual void emitExpandAtomicRMW(AtomicRMWInst *AI) const
Perform a atomicrmw expansion using a target-specific way.
Definition TargetLowering.h:2284
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition TargetLowering.h:3896
virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
Definition TargetLowering.h:522
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?
Definition TargetLowering.h:1899
virtual bool hasStackProbeSymbol(const MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Definition TargetLowering.h:2160
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
Definition TargetLowering.h:625
virtual Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const
Certain targets have context sensitive alignment requirements, where one type has the alignment requi...
Definition TargetLowering.h:1859
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Definition TargetLowering.h:3452
virtual bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition TargetLowering.h:2534
virtual bool shouldExtendTypeInLibCall(EVT Type) const
Returns true if arguments should be extended in lib calls.
Definition TargetLowering.h:2386
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition TargetLowering.h:2568
bool isPartialReduceMLALegalOrCustom(unsigned Opc, EVT AccVT, EVT InputVT) const
Return true if a PARTIAL_REDUCE_U/SMLA node with the specified types is legal or custom for this targ...
Definition TargetLowering.h:1691
virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
Definition TargetLowering.h:588
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition TargetLowering.h:3944
bool isSuitableForBitTests(const DenseMap< const BasicBlock *, unsigned int > &DestCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
Definition TargetLowering.h:1437
virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
Definition TargetLowering.h:486
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
Definition TargetLowering.h:980
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition TargetLowering.h:3074
virtual bool hasMultipleConditionRegisters(EVT VT) const
Does the target have multiple (allocatable) condition registers that can be used to store the results...
Definition TargetLowering.h:531
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallBase &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition TargetLowering.h:1246
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
Definition TargetLowering.h:1954
bool isStrictFPEnabled() const
Return true if the target support strict float operation.
Definition TargetLowering.h:365
virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const
Return true if creating a shift of the type by the given amount is not profitable.
Definition TargetLowering.h:3516
virtual bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const
True if target has some particular form of dealing with pointer arithmetic semantics for pointers wit...
Definition TargetLowering.h:3548
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
Definition TargetLowering.h:3305
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
virtual bool lowerInterleavedStore(Instruction *Store, Value *Mask, ShuffleVectorInst *SVI, unsigned Factor, const APInt &GapMask) const
Lower an interleaved store to target specific intrinsics.
Definition TargetLowering.h:3268
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition TargetLowering.h:1173
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition TargetLowering.h:3946
virtual bool shouldFoldSelectWithSingleBitTest(EVT VT, const APInt &AndMask) const
Definition TargetLowering.h:3522
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
Definition TargetLowering.h:1774
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
Definition TargetLowering.h:1024
virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const
Definition TargetLowering.h:514
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition TargetLowering.h:2628
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal for a comparison of the specified types on this ...
Definition TargetLowering.h:1664
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy,Idx).
Definition TargetLowering.h:971
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition TargetLowering.h:1113
LegalizeAction getAtomicLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Same as getLoadExtAction, but for atomic loads.
Definition TargetLowering.h:1513
bool EnableExtLdPromotion
Definition TargetLowering.h:3953
virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N) const
Return true if it is profitable to fold a pair of shifts into a mask.
Definition TargetLowering.h:851
MVT getProgramPointerTy(const DataLayout &DL) const
Return the type for code pointers, which is determined by the program address space specified through...
Definition TargetLowering.h:400
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition TargetLowering.h:2735
virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const
Definition TargetLowering.h:2378
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition TargetLowering.h:2890
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)
Definition TargetLowering.h:2676
virtual void emitExpandAtomicStore(StoreInst *SI) const
Perform a atomic store using a target-specific way.
Definition TargetLowering.h:2290
virtual bool preferIncOfAddToSubOfNot(EVT VT) const
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition TargetLowering.h:941
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition TargetLowering.h:1867
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition TargetLowering.h:381
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
Definition TargetLowering.h:2847
unsigned getMaxDivRemBitWidthSupported() const
Returns the size in bits of the maximum div/rem the backend supports.
Definition TargetLowering.h:2209
virtual bool isLegalAddImmediate(int64_t) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition TargetLowering.h:2963
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
Definition TargetLowering.h:3234
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition TargetLowering.h:1481
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
Definition TargetLowering.h:1537
virtual bool shouldKeepZExtForFP16Conv() const
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...
Definition TargetLowering.h:3530
virtual AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *RMWI) const
Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.
Definition TargetLowering.h:2437
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
Definition TargetLowering.h:2762
virtual bool canTransformPtrArithOutOfBounds(const Function &F, EVT PtrVT) const
True if the target allows transformations of in-bounds pointer arithmetic that cause out-of-bounds in...
Definition TargetLowering.h:3554
virtual bool shouldConsiderGEPOffsetSplit() const
Definition TargetLowering.h:3512
const ValueTypeActionImpl & getValueTypeActions() const
Definition TargetLowering.h:1136
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition TargetLowering.h:2423
TargetLoweringBase(const TargetMachine &TM, const TargetSubtargetInfo &STI)
NOTE: The TargetMachine owns TLOF.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition TargetLowering.h:3894
virtual bool isTruncateFree(SDValue Val, EVT VT2) const
Return true if truncating the specific node Val to type VT2 is free.
Definition TargetLowering.h:3094
virtual bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const
Return true if the @llvm.experimental.vector.match intrinsic should be expanded for vector type ‘VT’ ...
Definition TargetLowering.h:508
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
Definition TargetLowering.h:2506
virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const
Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a cust...
Definition TargetLowering.h:749
virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <>...
Definition TargetLowering.h:875
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
Definition TargetLowering.h:3335
void setPartialReduceMLAAction(unsigned Opc, MVT AccVT, MVT InputVT, LegalizeAction Action)
Indicate how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input type InputVT should be treate...
Definition TargetLowering.h:2793
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
Definition TargetLowering.h:1489
virtual bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...
Definition TargetLowering.h:2249
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition TargetLowering.h:2392
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition TargetLowering.h:2708
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
Definition TargetLowering.h:3110
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
Definition TargetLowering.h:406
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
Definition TargetLowering.h:2326
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
Definition TargetLowering.h:3172
virtual ISD::NodeType getExtendForAtomicCmpSwapArg() const
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition TargetLowering.h:2476
virtual bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT, unsigned SelectOpcode, SDValue X, SDValue Y) const
Return true if pulling a binary operation into a select with an identity constant is profitable.
Definition TargetLowering.h:3431
BooleanContent
Enum that describes how the target represents true/false values.
Definition TargetLowering.h:237
@ ZeroOrOneBooleanContent
Definition TargetLowering.h:239
@ UndefinedBooleanContent
Definition TargetLowering.h:238
@ ZeroOrNegativeOneBooleanContent
Definition TargetLowering.h:240
virtual bool shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) const
Definition TargetLowering.h:490
virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition TargetLowering.h:580
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
Definition TargetLowering.h:1103
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the 'representative' register class for the specified value type.
Definition TargetLowering.h:1091
virtual bool isZExtFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const
Definition TargetLowering.h:3173
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
Definition TargetLowering.h:1359
LegalizeAction getPartialReduceMLAAction(unsigned Opc, EVT AccVT, EVT InputVT) const
Return how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input type InputVT should be treated.
Definition TargetLowering.h:1679
bool isPredictableSelectExpensive() const
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right...
Definition TargetLowering.h:678
virtual bool mergeStoresAfterLegalization(EVT MemVT) const
Allow store merging for the specified type after legalization in addition to before legalization.
Definition TargetLowering.h:717
virtual bool shouldMergeStoreOfLoadsOverCall(EVT, EVT) const
Returns true if it's profitable to allow merging store of loads when there are functions calls betwee...
Definition TargetLowering.h:3664
RTLIB::LibcallImpl getSupportedLibcallImpl(StringRef FuncName) const
Check if this is valid libcall for the current module, otherwise RTLIB::Unsupported.
Definition TargetLowering.h:3635
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
Definition TargetLowering.h:1964
virtual bool isProfitableToHoist(Instruction *I) const
Definition TargetLowering.h:3099
unsigned getGatherAllAliasesMaxDepth() const
Definition TargetLowering.h:1910
virtual LegalizeAction getCustomOperationAction(SDNode &Op) const
How to legalize this custom operation?
Definition TargetLowering.h:1283
virtual bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *) const
IR version.
Definition TargetLowering.h:3377
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) !...
Definition TargetLowering.h:818
virtual bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
Definition TargetLowering.h:708
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
Definition TargetLowering.h:3932
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
Definition TargetLowering.h:801
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the 'representative' register class for the specified value type.
Definition TargetLowering.h:1084
virtual bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const
Return true if it's profitable to narrow operations of type SrcVT to DestVT.
Definition TargetLowering.h:3424
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
Definition TargetLowering.h:763
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
Definition TargetLowering.h:1507
TargetLoweringBase(const TargetLoweringBase &)=delete
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
Definition TargetLowering.h:1944
bool isAtomicLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified atomic load with extension is legal on this target.
Definition TargetLowering.h:1530
virtual bool isBinOp(unsigned Opcode) const
Return true if the node is a math/logic binary operator.
Definition TargetLowering.h:3043
virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
Definition TargetLowering.h:842
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Definition TargetLowering.h:2121
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
Definition TargetLowering.h:2203
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
Definition TargetLowering.h:1576
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Definition TargetLowering.h:2885
virtual ~TargetLoweringBase()
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const
Returns if it's reasonable to merge stores to MemVT size.
Definition TargetLowering.h:722
void setPartialReduceMLAAction(ArrayRef< unsigned > Opcodes, MVT AccVT, MVT InputVT, LegalizeAction Action)
Definition TargetLowering.h:2802
LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const
Definition TargetLowering.h:1341
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition TargetLowering.h:2603
virtual bool preferABDSToABSWithNSW(EVT VT) const
Definition TargetLowering.h:948
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition TargetLowering.h:2812
virtual bool getAddrModeArguments(const IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
Definition TargetLowering.h:2904
bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal on this target.
Definition TargetLowering.h:1501
virtual bool hasInlineStackProbe(const MachineFunction &MF) const
Definition TargetLowering.h:2162
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition TargetLowering.h:256
@ LLSC
Definition TargetLowering.h:260
@ CmpArithIntrinsic
Definition TargetLowering.h:268
@ CmpXChg
Definition TargetLowering.h:264
@ CastToInteger
Definition TargetLowering.h:258
@ LLOnly
Definition TargetLowering.h:262
@ BitTestIntrinsic
Definition TargetLowering.h:266
@ NotAtomic
Definition TargetLowering.h:275
@ None
Definition TargetLowering.h:257
@ CustomExpand
Definition TargetLowering.h:271
@ MaskedIntrinsic
Definition TargetLowering.h:265
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
Definition TargetLowering.h:2769
void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition TargetLowering.h:2575
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
Definition TargetLowering.h:629
void setOperationPromotedToType(ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT)
Definition TargetLowering.h:2822
unsigned getMaxLargeFPConvertBitWidthSupported() const
Returns the size in bits of the maximum fp to/from int conversion the backend supports.
Definition TargetLowering.h:2215
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, LLT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition TargetLowering.h:3371
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
Definition TargetLowering.h:3087
virtual bool isCheapToSpeculateCtlz(Type *Ty) const
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition TargetLowering.h:733
virtual bool shouldExpandCttzElements(EVT VT) const
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
Definition TargetLowering.h:497
virtual bool signExtendConstant(const ConstantInt *C) const
Return true if this constant should be sign extended when promoting to a larger type.
Definition TargetLowering.h:3193
virtual bool lowerInterleaveIntrinsicToStore(Instruction *Store, Value *Mask, ArrayRef< Value * > InterleaveValues) const
Lower an interleave intrinsic to a target specific store intrinsic.
Definition TargetLowering.h:3297
virtual bool isTruncateFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const
Definition TargetLowering.h:3088
AndOrSETCCFoldKind
Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ....
Definition TargetLowering.h:294
@ NotAnd
Definition TargetLowering.h:297
@ ABS
Definition TargetLowering.h:298
@ AddAnd
Definition TargetLowering.h:296
@ None
Definition TargetLowering.h:295
virtual bool shouldScalarizeBinop(SDValue VecOp) const
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
Definition TargetLowering.h:3459
Align getPrefFunctionAlignment() const
Return the preferred function alignment.
Definition TargetLowering.h:2109
RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const
Get the libcall impl routine name for the specified libcall.
Definition TargetLowering.h:3616
virtual void emitExpandAtomicLoad(LoadInst *LI) const
Perform a atomic load using a target-specific way.
Definition TargetLowering.h:2296
Align getMinFunctionAlignment() const
Return the minimum function alignment.
Definition TargetLowering.h:2106
virtual AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
Definition TargetLowering.h:2407
static StringRef getLibcallImplName(RTLIB::LibcallImpl Call)
Get the libcall routine name for the specified libcall implementation.
Definition TargetLowering.h:3627
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition TargetLowering.h:2833
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
Definition TargetLowering.h:738
virtual bool useSoftFloat() const
Definition TargetLowering.h:376
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x,...
Definition TargetLowering.h:698
BooleanContent getBooleanContents(EVT Type) const
Definition TargetLowering.h:1030
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition TargetLowering.h:2429
bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
Definition TargetLowering.h:1618
virtual int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const
Return the prefered common base offset.
Definition TargetLowering.h:2948
virtual bool isVectorClearMaskLegal(ArrayRef< int >, EVT) const
Similar to isShuffleMaskLegal.
Definition TargetLowering.h:1277
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
Definition TargetLowering.h:2101
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
Definition TargetLowering.h:2544
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition TargetLowering.h:2662
bool hasTargetDAGCombine(ISD::NodeType NT) const
If true, the target has custom DAG combine transformations that it can perform for the specified node...
Definition TargetLowering.h:1905
void setLibcallImpl(RTLIB::Libcall Call, RTLIB::LibcallImpl Impl)
Definition TargetLowering.h:3611
virtual bool fallBackToDAGISel(const Instruction &Inst) const
Definition TargetLowering.h:682
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...
Definition TargetLowering.h:3882
virtual bool shouldSplatInsEltVarIndex(EVT) const
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
Definition TargetLowering.h:987
LegalizeAction getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
Definition TargetLowering.h:1599
NegatibleCost
Enum that specifies when a float negation is beneficial.
Definition TargetLowering.h:286
@ Cheaper
Definition TargetLowering.h:287
@ Expensive
Definition TargetLowering.h:289
@ Neutral
Definition TargetLowering.h:288
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation has solution on this target.
Definition TargetLowering.h:1554
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
Definition TargetLowering.h:1160
virtual unsigned preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const
Definition TargetLowering.h:929
virtual void emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const
Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.
Definition TargetLowering.h:2317
virtual bool shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
Definition TargetLowering.h:2381
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition TargetLowering.h:2085
bool IsStrictFPEnabled
Definition TargetLowering.h:3965
virtual bool isFMADLegal(const MachineInstr &MI, LLT Ty) const
Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD.
Definition TargetLowering.h:3385
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action)
Definition TargetLowering.h:2783
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
Definition TargetLowering.h:2229
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition TargetLowering.h:3622
virtual bool isLegalAddScalableImmediate(int64_t) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
Definition TargetLowering.h:2971
std::vector< ArgListEntry > ArgListTy
Definition TargetLowering.h:341
virtual bool shouldAlignPointerArgs(CallInst *, unsigned &, Align &) const
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
Definition TargetLowering.h:2177
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
Definition TargetLowering.h:3230
virtual AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
Definition TargetLowering.h:2414
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)
Definition TargetLowering.h:2741
virtual bool isVScaleKnownToBeAPowerOfTwo() const
Return true only if vscale must be a power of two.
Definition TargetLowering.h:634
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
Definition TargetLowering.h:3505
virtual MachineMemOperand::Flags getTargetMMOFlags(const MemSDNode &Node) const
This callback is used to inspect load/store SDNode.
Definition TargetLowering.h:465
virtual EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &) const
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition TargetLowering.h:2040
virtual Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
Definition TargetLowering.h:2986
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition TargetLowering.h:3181
void setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
Definition TargetLowering.h:2695
virtual bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const
Definition TargetLowering.h:1630
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
Definition TargetLowering.h:1925
virtual LLVM_READONLY LLT getPreferredShiftAmountTy(LLT ShiftValueTy) const
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
Definition TargetLowering.h:424
bool isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) const
Return true if it is beneficial to expand an @llvm.powi.
Definition TargetLowering.h:2554
LLT getVectorIdxLLT(const DataLayout &DL) const
Returns the type to be used for the index operand of: G_INSERT_VECTOR_ELT, G_EXTRACT_VECTOR_ELT,...
Definition TargetLowering.h:445
virtual EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Definition TargetLowering.h:1724
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)
Definition TargetLowering.h:2724
virtual AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
Definition TargetLowering.h:2398
bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal or custom for a comparison of the specified type...
Definition TargetLowering.h:1670
virtual bool isComplexDeinterleavingSupported() const
Does this target support complex deinterleaving.
Definition TargetLowering.h:3560
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition TargetLowering.h:3909
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
Definition TargetLowering.h:394
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition TargetLowering.h:2092
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
Definition TargetLowering.h:388
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition TargetLowering.h:2587
virtual bool addressingModeSupportsTLS(const GlobalValue &) const
Returns true if the targets addressing mode can target thread local storage (TLS).
Definition TargetLowering.h:2943
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition TargetLowering.h:1784
virtual bool shouldConvertPhiType(Type *From, Type *To) const
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
Definition TargetLowering.h:2993
virtual bool isFAbsFree(EVT VT) const
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
Definition TargetLowering.h:3342
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
Definition TargetLowering.h:2975
virtual bool preferZeroCompareBranch() const
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition TargetLowering.h:759
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
Definition TargetLowering.h:1290
virtual bool lowerInterleavedLoad(Instruction *Load, Value *Mask, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor, const APInt &GapMask) const
Lower an interleaved load to target specific intrinsics.
Definition TargetLowering.h:3249
virtual unsigned getVectorIdxWidth(const DataLayout &DL) const
Returns the type to be used for the index operand vector operations.
Definition TargetLowering.h:431
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
Definition TargetLowering.h:1699
virtual bool generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const
Definition TargetLowering.h:3416
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
Definition TargetLowering.h:2458
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
virtual bool hasPairedLoad(EVT, Align &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
Definition TargetLowering.h:3224
virtual bool convertSelectOfConstantsToMath(EVT VT) const
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition TargetLowering.h:2511
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
Definition TargetLowering.h:1387
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
virtual bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
Definition TargetLowering.h:3198
virtual MVT getVPExplicitVectorLengthTy() const
Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB,...
Definition TargetLowering.h:453
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition TargetLowering.h:234
TargetLoweringBase & operator=(const TargetLoweringBase &)=delete
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
Definition TargetLowering.h:279
@ Always
Definition TargetLowering.h:280
@ OnlyLegalOrCustom
Definition TargetLowering.h:281
static ISD::NodeType getExtendForContent(BooleanContent Content)
Definition TargetLowering.h:343
const RTLIB::RuntimeLibcallsInfo & getRuntimeLibcallsInfo() const
Definition TargetLowering.h:3607
virtual bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition TargetLowering.h:3534
virtual bool lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask, IntrinsicInst *DI) const
Lower a deinterleave intrinsic to a target specific load intrinsic.
Definition TargetLowering.h:3281
virtual bool supportKCFIBundles() const
Return true if the target supports kcfi operand bundles.
Definition TargetLowering.h:4619
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
Examine constraint type and operand type and determine a weight value.
ConstraintType
Definition TargetLowering.h:5170
@ C_RegisterClass
Definition TargetLowering.h:5172
@ C_Memory
Definition TargetLowering.h:5173
@ C_Immediate
Definition TargetLowering.h:5175
@ C_Register
Definition TargetLowering.h:5171
@ C_Other
Definition TargetLowering.h:5176
@ C_Address
Definition TargetLowering.h:5174
@ C_Unknown
Definition TargetLowering.h:5177
SmallVector< ConstraintPair > ConstraintGroup
Definition TargetLowering.h:5260
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
Definition TargetLowering.h:5374
virtual bool isDesirableToCommuteWithShift(const MachineInstr &MI, bool IsAfterLegal) const
GlobalISel - return true if it is profitable to move this shift by a constant amount through its oper...
Definition TargetLowering.h:4540
virtual bool supportPtrAuthBundles() const
Return true if the target supports ptrauth operand bundles.
Definition TargetLowering.h:4622
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition TargetLowering.h:5150
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
Definition TargetLowering.h:5043
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
Definition TargetLowering.h:4608
virtual SDValue visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const
Definition TargetLowering.h:4104
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
Definition TargetLowering.h:5847
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
This is the helper function to return the newly negated expression if the cost is not expensive.
Definition TargetLowering.h:4679
virtual bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const
Definition TargetLowering.h:3999
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Definition TargetLowering.h:5068
SDValue getCheaperOrNeutralNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) const
Definition TargetLowering.h:4649
virtual Register getRegisterByName(const char *RegName, LLT Ty, const MachineFunction &MF) const
Return the register ID of the name passed in.
Definition TargetLowering.h:5057
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition TargetLowering.h:5282
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const
Definition TargetLowering.h:4197
std::vector< AsmOperandInfo > AsmOperandInfoVector
Definition TargetLowering.h:5228
virtual bool isTargetCanonicalConstantNode(SDValue Op) const
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
Definition TargetLowering.h:4434
virtual bool isTargetCanonicalSelect(SDNode *N) const
Return true if the given select/vselect should be considered canonical and not be transformed.
Definition TargetLowering.h:4442
SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
This is the helper function to return the newly negated expression only when the cost is cheaper.
Definition TargetLowering.h:4670
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Definition TargetLowering.h:5112
virtual SDValue lowerEHPadEntry(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
Optional target hook to add target-specific actions when entering EH pad blocks.
Definition TargetLowering.h:4720
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue unwrapAddress(SDValue N) const
Definition TargetLowering.h:4491
virtual bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition TargetLowering.h:4692
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node.
Definition TargetLowering.h:4602
virtual SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const
Target-specific combining of register parts into its original value.
Definition TargetLowering.h:4700
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const
Insert explicit copies in entry and exit blocks.
Definition TargetLowering.h:4635
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
Definition TargetLowering.h:5006
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition TargetLowering.h:4586
ConstraintWeight
Definition TargetLowering.h:5180
@ CW_Invalid
Definition TargetLowering.h:5182
@ CW_Better
Definition TargetLowering.h:5185
@ CW_Memory
Definition TargetLowering.h:5191
@ CW_Constant
Definition TargetLowering.h:5192
@ CW_Good
Definition TargetLowering.h:5184
@ CW_SpecificReg
Definition TargetLowering.h:5189
@ CW_Register
Definition TargetLowering.h:5190
@ CW_Okay
Definition TargetLowering.h:5183
@ CW_Default
Definition TargetLowering.h:5193
@ CW_Best
Definition TargetLowering.h:5186
~TargetLowering() override
TargetLowering & operator=(const TargetLowering &)=delete
virtual bool isDesirableToPullExtFromShl(const MachineInstr &MI) const
GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x),...
Definition TargetLowering.h:4547
bool isPositionIndependent() const
std::pair< StringRef, TargetLowering::ConstraintType > ConstraintPair
Definition TargetLowering.h:5259
virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) const
Returns true if the specified base+offset is a legal indexed addressing mode for this target.
Definition TargetLowering.h:4043
ConstraintGroup getConstraintPreferences(AsmOperandInfo &OpInfo) const
Given an OpInfo with list of constraints codes as strings, return a sorted Vector of pairs of constra...
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition TargetLowering.h:4627
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const
Definition TargetLowering.h:3987
virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
Return a reciprocal estimate value for the input operand.
Definition TargetLowering.h:5397
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const
Definition TargetLowering.h:4015
virtual bool isDesirableToCommuteXorWithShift(const SDNode *N) const
Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT...
Definition TargetLowering.h:4578
TargetLowering(const TargetLowering &)=delete
virtual bool shouldSimplifyDemandedVectorElts(SDValue Op, const TargetLoweringOpt &TLO) const
Return true if the target supports simplifying demanded vector elements by converting them to undefs.
Definition TargetLowering.h:4296
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition TargetLowering.h:4711
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual SDValue getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) const
Return a target-dependent result if the input operand is not suitable for use with a square root esti...
Definition TargetLowering.h:5411
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition TargetLowering.h:4032
virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const
For most targets, an LLVM type must be broken down into multiple smaller types.
Definition TargetLowering.h:5089
virtual ArrayRef< MCPhysReg > getRoundingControlRegisters() const
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
Definition TargetLowering.h:5101
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition TargetLowering.h:5029
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Definition TargetLowering.h:5078
virtual bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const
Return true if it is profitable to move this shift by a constant amount through its operand,...
Definition TargetLowering.h:4521
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual SDValue visitMaskedStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const
Definition TargetLowering.h:4111
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
Definition TargetLowering.h:4057
virtual bool useLoadStackGuardNode(const Module &M) const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition TargetLowering.h:5845
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
It is an error to pass RTLIB::UNKNOWN_LIBCALL as LC.
Definition TargetLowering.h:4126
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Definition TargetLowering.h:5352
virtual AndOrSETCCFoldKind isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const
Definition TargetLowering.h:4569
virtual void HandleByVal(CCState *, unsigned &, Align) const
Target-specific cleanup for formal ByVal parameters.
Definition TargetLowering.h:5012
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition TargetLowering.h:5095
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Definition TargetLowering.h:4022
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index, const SDNodeFlags PtrArithFlags=SDNodeFlags()) const
Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base a...
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Definition TargetLowering.h:5161
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::LibcallImpl LibcallImpl, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition TargetLowering.h:4614
virtual bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) const
Definition TargetLowering.h:4010
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
Definition TargetLowering.h:5050
virtual bool isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const
On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use eithe...
Definition TargetLowering.h:4085
SDValue getInboundsVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const
Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base a...
Definition TargetLowering.h:5682
virtual MVT getJumpTableRegTy(const DataLayout &DL) const
Definition TargetLowering.h:4052
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
Definition TargetLowering.h:4725
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &, const Type *RetTy) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition TargetLowering.h:5017
virtual bool isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode, EVT) const
Definition TargetLowering.h:5869
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Definition TargetLowering.h:4594
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
bool isPointerTy() const
True if this is an instance of PointerType.
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
bool isIntegerTy() const
True if this is an instance of IntegerType.
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FADD
Simple binary floating point operators.
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ ABDS
ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...
static const int LAST_LOADEXT_TYPE
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition TargetLowering.h:101
Preference
Definition TargetLowering.h:103
@ Linearize
Definition TargetLowering.h:111
@ Fast
Definition TargetLowering.h:110
@ Last
Definition TargetLowering.h:112
@ RegPressure
Definition TargetLowering.h:106
@ Hybrid
Definition TargetLowering.h:107
@ None
Definition TargetLowering.h:104
@ VLIW
Definition TargetLowering.h:109
@ Source
Definition TargetLowering.h:105
@ ILP
Definition TargetLowering.h:108
@ System
Synchronized with respect to all concurrently executing threads.
This namespace contains all of the command line option processing machinery.
This is an optimization pass for GlobalISel generic memory operations.
GenericUniformityInfo< SSAContext > UniformityInfo
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
void fill(R &&Range, T &&Value)
Provide wrappers to std::fill which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
constexpr int popcount(T Value) noexcept
Count the number of set bits in a value.
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
LLVM_ABI bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
ComplexDeinterleavingOperation
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
CodeGenOptLevel
Code generation optimization level.
bool isa(const From &Val)
isa - Return true if the parameter to the template is an instance of one of the template type argu...
LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key
AtomicOrdering
Atomic ordering for LLVM's memory model.
LLVM_ABI EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx)
ComplexDeinterleavingRotation
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM, bool ReturnsFirstArg=false)
Test if the given instruction is in a position to be optimized with a tail-call.
DWARFExpression::Operation Op
LLVM_ABI bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
static cl::opt< unsigned > CostThreshold("dfa-cost-threshold", cl::desc("Maximum cost accepted for the transformation"), cl::Hidden, cl::init(50))
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
constexpr uint64_t value() const
This is a hole in the type system and should not be abused.
Represent subnormal handling kind for floating point instruction inputs and outputs.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isByteSized() const
Return true if the bit size is a multiple of 8.
static LLVM_ABI EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool isVector() const
Return true if this is a vector value type.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
bool isInteger() const
Return true if this is an integer or a vector integer type.
ConstraintInfo()=default
Default constructor.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition TargetLowering.h:118
bool isDstAligned(Align AlignCheck) const
Definition TargetLowering.h:188
bool allowOverlap() const
Definition TargetLowering.h:170
bool isFixedDstAlign() const
Definition TargetLowering.h:169
uint64_t size() const
Definition TargetLowering.h:164
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
Definition TargetLowering.h:151
Align getDstAlign() const
Definition TargetLowering.h:165
bool isMemcpyStrSrc() const
Definition TargetLowering.h:177
bool isAligned(Align AlignCheck) const
Definition TargetLowering.h:191
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
Definition TargetLowering.h:136
bool isSrcAligned(Align AlignCheck) const
Definition TargetLowering.h:185
bool isMemset() const
Definition TargetLowering.h:171
bool isMemcpy() const
Definition TargetLowering.h:172
bool isMemcpyWithFixedDstAlign() const
Definition TargetLowering.h:173
bool isZeroMemset() const
Definition TargetLowering.h:176
Align getSrcAlign() const
Definition TargetLowering.h:181
A simple container for information about the supported runtime calls.
static StringRef getLibcallImplName(RTLIB::LibcallImpl CallImpl)
Get the libcall routine name for the specified libcall implementation.
These are IR-level optimization flags that may be propagated to SDNodes.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
Definition TargetLowering.h:2918
int64_t BaseOffs
Definition TargetLowering.h:2920
GlobalValue * BaseGV
Definition TargetLowering.h:2919
bool HasBaseReg
Definition TargetLowering.h:2921
int64_t Scale
Definition TargetLowering.h:2922
int64_t ScalableOffset
Definition TargetLowering.h:2923
Definition TargetLowering.h:659
int BaseCost
Definition TargetLowering.h:660
int LikelyBias
Definition TargetLowering.h:661
int UnlikelyBias
Definition TargetLowering.h:662
Definition TargetLowering.h:1219
SyncScope::ID ssid
Definition TargetLowering.h:1236
std::optional< unsigned > fallbackAddressSpace
Definition TargetLowering.h:1228
MaybeAlign align
Definition TargetLowering.h:1233
MachineMemOperand::Flags flags
Definition TargetLowering.h:1235
int offset
Definition TargetLowering.h:1230
AtomicOrdering order
Definition TargetLowering.h:1237
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
Definition TargetLowering.h:1224
uint64_t size
Definition TargetLowering.h:1231
AtomicOrdering failureOrder
Definition TargetLowering.h:1238
EVT memVT
Definition TargetLowering.h:1221
unsigned opc
Definition TargetLowering.h:1220
This contains information for each constraint that we are lowering.
Definition TargetLowering.h:5197
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
Definition TargetLowering.h:5216
MVT ConstraintVT
The ValueType for the operand value.
Definition TargetLowering.h:5213
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
Definition TargetLowering.h:5205
std::string ConstraintCode
This contains the actual string for the code, like "m".
Definition TargetLowering.h:5201
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
Definition TargetLowering.h:5210
This structure contains all information that is necessary for lowering calls.
Definition TargetLowering.h:4740
CallLoweringInfo & setConvergent(bool Value=true)
Definition TargetLowering.h:4886
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Definition TargetLowering.h:4916
bool IsInReg
Definition TargetLowering.h:4749
CallLoweringInfo & setDeactivationSymbol(GlobalValue *Sym)
Definition TargetLowering.h:4931
ArgListTy Args
Definition TargetLowering.h:4767
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, const CallBase &Call)
Definition TargetLowering.h:4835
CallLoweringInfo & setCFIType(const ConstantInt *Type)
Definition TargetLowering.h:4921
bool IsTailCall
Definition TargetLowering.h:4759
CallLoweringInfo & setInRegister(bool Value=true)
Definition TargetLowering.h:4861
SDValue Callee
Definition TargetLowering.h:4766
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
Definition TargetLowering.h:4798
SDLoc DL
Definition TargetLowering.h:4769
bool IsVarArg
Definition TargetLowering.h:4748
SDValue ConvergenceControlToken
Definition TargetLowering.h:4776
SmallVector< ISD::InputArg, 32 > Ins
Definition TargetLowering.h:4773
bool IsPreallocated
Definition TargetLowering.h:4754
CallLoweringInfo & setVarArg(bool Value=true)
Definition TargetLowering.h:4871
bool IsPostTypeLegalization
Definition TargetLowering.h:4762
SmallVector< SDValue, 4 > InVals
Definition TargetLowering.h:4774
const ConstantInt * CFIType
Definition TargetLowering.h:4775
Type * OrigRetTy
Original unlegalized return type.
Definition TargetLowering.h:4743
bool RetZExt
Definition TargetLowering.h:4747
std::optional< PtrAuthInfo > PAI
Definition TargetLowering.h:4779
CallLoweringInfo & setDiscardResult(bool Value=true)
Definition TargetLowering.h:4881
bool IsPatchPoint
Definition TargetLowering.h:4753
CallLoweringInfo & setZExtResult(bool Value=true)
Definition TargetLowering.h:4896
CallLoweringInfo & setIsPatchPoint(bool Value=true)
Definition TargetLowering.h:4901
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
Definition TargetLowering.h:4787
unsigned NumFixedArgs
Definition TargetLowering.h:4764
SDValue Chain
Definition TargetLowering.h:4741
bool RetSExt
Definition TargetLowering.h:4746
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, Type *OrigResultType, SDValue Target, ArgListTy &&ArgsList)
Definition TargetLowering.h:4804
CallLoweringInfo & setTailCall(bool Value=true)
Definition TargetLowering.h:4876
bool NoMerge
Definition TargetLowering.h:4755
CallLoweringInfo & setIsPreallocated(bool Value=true)
Definition TargetLowering.h:4906
CallLoweringInfo & setSExtResult(bool Value=true)
Definition TargetLowering.h:4891
CallLoweringInfo & setNoReturn(bool Value=true)
Definition TargetLowering.h:4866
ArgListTy & getArgs()
Definition TargetLowering.h:4936
CallLoweringInfo & setConvergenceControlToken(SDValue Token)
Definition TargetLowering.h:4926
bool IsReturnValueUsed
Definition TargetLowering.h:4751
const CallBase * CB
Definition TargetLowering.h:4770
SmallVector< ISD::OutputArg, 32 > Outs
Definition TargetLowering.h:4771
SmallVector< SDValue, 32 > OutVals
Definition TargetLowering.h:4772
Type * RetTy
Same as OrigRetTy, or partially legalized for soft float libcalls.
Definition TargetLowering.h:4745
bool IsConvergent
Definition TargetLowering.h:4752
CallingConv::ID CallConv
Definition TargetLowering.h:4765
SelectionDAG & DAG
Definition TargetLowering.h:4768
CallLoweringInfo & setChain(SDValue InChain)
Definition TargetLowering.h:4792
CallLoweringInfo & setPtrAuth(PtrAuthInfo Value)
Definition TargetLowering.h:4911
CallLoweringInfo(SelectionDAG &DAG)
Definition TargetLowering.h:4781
GlobalValue * DeactivationSymbol
Definition TargetLowering.h:4777
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})
Definition TargetLowering.h:4819
bool DoesNotReturn
Definition TargetLowering.h:4750
Definition TargetLowering.h:4444
void * DC
Definition TargetLowering.h:4445
bool isBeforeLegalizeOps() const
Definition TargetLowering.h:4456
bool isAfterLegalizeDAG() const
Definition TargetLowering.h:4457
CombineLevel getDAGCombineLevel()
Definition TargetLowering.h:4458
CombineLevel Level
Definition TargetLowering.h:4446
bool isCalledByLegalizer() const
Definition TargetLowering.h:4459
bool CalledByLegalizer
Definition TargetLowering.h:4447
bool isBeforeLegalize() const
Definition TargetLowering.h:4455
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
Definition TargetLowering.h:4452
SelectionDAG & DAG
Definition TargetLowering.h:4450
This structure is used to pass arguments to makeLibCall function.
Definition TargetLowering.h:4942
MakeLibCallOptions & setIsPostTypeLegalization(bool Value=true)
Definition TargetLowering.h:4974
MakeLibCallOptions & setDiscardResult(bool Value=true)
Definition TargetLowering.h:4969
bool IsSigned
Definition TargetLowering.h:4949
ArrayRef< EVT > OpsVTBeforeSoften
Definition TargetLowering.h:4945
bool IsPostTypeLegalization
Definition TargetLowering.h:4952
MakeLibCallOptions & setTypeListBeforeSoften(ArrayRef< EVT > OpsVT, EVT RetVT)
Definition TargetLowering.h:4979
ArrayRef< Type * > OpsTypeOverrides
Definition TargetLowering.h:4947
MakeLibCallOptions & setIsSigned(bool Value=true)
Definition TargetLowering.h:4959
bool IsReturnValueUsed
Definition TargetLowering.h:4951
bool DoesNotReturn
Definition TargetLowering.h:4950
bool IsSoften
Definition TargetLowering.h:4953
EVT RetVTBeforeSoften
Definition TargetLowering.h:4946
MakeLibCallOptions & setNoReturn(bool Value=true)
Definition TargetLowering.h:4964
MakeLibCallOptions & setOpsTypeOverrides(ArrayRef< Type * > OpsTypes)
Override the argument type for an operand.
Definition TargetLowering.h:4988
MakeLibCallOptions()
Definition TargetLowering.h:4955
This structure contains the information necessary for lowering pointer-authenticating indirect calls.
Definition TargetLowering.h:4731
uint64_t Key
Definition TargetLowering.h:4732
SDValue Discriminator
Definition TargetLowering.h:4733
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
Definition TargetLowering.h:4150
SelectionDAG & DAG
Definition TargetLowering.h:4151
bool CombineTo(SDValue O, SDValue N)
Definition TargetLowering.h:4164
bool LegalTypes() const
Definition TargetLowering.h:4161
SDValue New
Definition TargetLowering.h:4155
bool LegalOps
Definition TargetLowering.h:4153
bool LegalOperations() const
Definition TargetLowering.h:4162
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
Definition TargetLowering.h:4157
bool LegalTys
Definition TargetLowering.h:4152
SDValue Old
Definition TargetLowering.h:4154