LLVM: include/llvm/CodeGen/TargetLowering.h Source File (original) (raw)
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22#ifndef LLVM_CODEGEN_TARGETLOWERING_H
23#define LLVM_CODEGEN_TARGETLOWERING_H
24
54#include
55#include
56#include
57#include
58#include
59#include
60#include
61#include
62#include
63
64namespace llvm {
65
66class AssumptionCache;
67class CCState;
68class CCValAssign;
72class FastISel;
73class FunctionLoweringInfo;
74class GlobalValue;
75class Loop;
76class GISelKnownBits;
77class IntrinsicInst;
78class IRBuilderBase;
79struct KnownBits;
80class LLVMContext;
81class MachineBasicBlock;
82class MachineFunction;
83class MachineInstr;
84class MachineJumpTableInfo;
85class MachineLoop;
86class MachineRegisterInfo;
87class MCContext;
88class MCExpr;
90class ProfileSummaryInfo;
91class TargetLibraryInfo;
92class TargetMachine;
93class TargetRegisterClass;
94class TargetRegisterInfo;
95class TargetTransformInfo;
97
98namespace Sched {
99
111
112}
113
114
116private:
117
119 bool DstAlignCanChange;
120
121 Align DstAlign;
122
123 bool AllowOverlap;
124
125 bool IsMemset;
126 bool ZeroMemset;
127
128 bool MemcpyStrSrc;
129
130 Align SrcAlign;
131
132public:
134 Align SrcAlign, bool IsVolatile,
135 bool MemcpyStrSrc = false) {
137 Op.Size = Size;
138 Op.DstAlignCanChange = DstAlignCanChange;
139 Op.DstAlign = DstAlign;
140 Op.AllowOverlap = !IsVolatile;
141 Op.IsMemset = false;
142 Op.ZeroMemset = false;
143 Op.MemcpyStrSrc = MemcpyStrSrc;
144 Op.SrcAlign = SrcAlign;
145 return Op;
146 }
147
149 bool IsZeroMemset, bool IsVolatile) {
151 Op.Size = Size;
152 Op.DstAlignCanChange = DstAlignCanChange;
153 Op.DstAlign = DstAlign;
154 Op.AllowOverlap = !IsVolatile;
155 Op.IsMemset = true;
156 Op.ZeroMemset = IsZeroMemset;
157 Op.MemcpyStrSrc = false;
158 return Op;
159 }
160
163 assert(!DstAlignCanChange);
164 return DstAlign;
165 }
168 bool isMemset() const { return IsMemset; }
169 bool isMemcpy() const { return !IsMemset; }
171 return isMemcpy() && !DstAlignCanChange;
172 }
176 return MemcpyStrSrc;
177 }
180 return SrcAlign;
181 }
184 }
187 }
190 }
191};
192
193
194
196public:
197
198
204 Custom
206
207
208
221
222
223
224
225
226
227 };
228
229
230
232
233
239
240
244
245 VectorMaskSelect
246
248
249
250
251
252
254 None,
255 CastToInteger,
256
257 LLSC,
258
259 LLOnly,
260
261 CmpXChg,
262 MaskedIntrinsic,
263 BitTestIntrinsic,
264
265 CmpArithIntrinsic,
266
267 Expand,
268
269
270
272 };
273
274
276 Always,
277 OnlyLegalOrCustom,
278
279 };
280
281
283 Cheaper = 0,
284 Neutral = 1,
285 Expensive = 2
286 };
287
288
289
295 };
296
298 public:
319
326
328 };
330
333
337
340
343
345 }
347 }
348
353
354
357 }
358
359protected:
360
362
363public:
365
367
368
369
370
373 }
374
375
376
377
380 }
381
382
383
386 }
387
388
389
392 }
393
394
395
398 }
399
400
401
402
404
405
406
407
408
410
411
412
415 return ShiftValueTy;
416 }
417
418
419
420
423 }
424
425
426
427
428
430
431
432
433
436 }
437
438
439
443 }
444
453
455 return true;
456 }
457
458
459
460 virtual bool
462 return true;
463 }
464
465
466
468 return true;
469 }
470
472 bool IsScalable) const {
473 return true;
474 }
475
476
477
479
480
481
483 bool ZeroIsPoison,
485
486
487
488
490 return true;
491 }
492
493
494
496 return true;
497 }
498
499
500
501
502
504 return true;
505 }
506
507
509 return HasMultipleConditionRegisters;
510 }
511
512
514
515
518
521
524
526 }
527
528
529
530
531
533
534
535
536
537
539
540
541
542
543
544
545
546
547
548
549 virtual bool
551 unsigned DefinedValues) const {
552 return DefinedValues < 3;
553 }
554
555
556
557
558
560
561
563 return true;
564 }
565
566
568
569 return false;
570 }
571
572
578
579
580
581
582
584
585
586
587
588
590
591
592
593
594
596
597
598
599
600
602
603
605
606
607
609 return BypassSlowDivWidths;
610 }
611
612
614
615
616
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
642 };
643
644
645
646
647
650 const Value *) const {
651
652 return {-1, -1, -1};
653 }
654
655
656
659 }
660
662 return false;
663 }
664
665
666
667
668
669
670
674
675
676
680
682 }
683
684
685
686
688 unsigned NumElem,
689 unsigned AddrSpace) const {
690 return IsZero;
691 }
692
693
694
695
697 return true;
698 }
699
700
703 return true;
704 }
705
706
708 return false;
709 }
710
711
713 return false;
714 }
715
716
718 return false;
719 }
720
721
724 }
725
726
727
729 return 1;
730 }
731
732
733
735
736
737
739
740
741
743 return false;
744 }
745
746
747
748
749
750
751
752
753
754
755
757 return false;
758 }
759
760
761 virtual bool
764 return true;
765 }
766
767
768
769
770
771
773 return false;
774 }
775
776
777
778
779
783 }
784
785
786
787
788
789
790
791
792
793
794
795
796
798 return false;
799 }
800
801
802
803
805
806
808 }
809
810
811
812
813
815
816
817
818
819
820
822
823 return false;
824 }
825
826
827
828
829
832 return true;
833 }
834
835
836
837
838
839
840
841
843 unsigned KeptBits) const {
844
845 return false;
846 }
847
848
849
850
851
852
853
854
857 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
860
861
862
863
864
865 if (OldShiftOpcode == ISD::SHL && CC->isOne())
866 return false;
867
868
869 if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
870 return true;
871 }
872
873
874
875
876
877 return !XC;
878 }
879
880
881
882
883
884
885
886
887
888
889
890
891
894
896 }
897
898
899
900
901
902
903
904
905
906
907
908
910 EVT VT, unsigned ShiftOpc, bool MayTransformRotate,
911 const APInt &ShiftOrRotateAmt,
912 const std::optional &AndMask) const {
913 return ShiftOpc;
914 }
915
916
917
918
919
920
922
923 return true;
924 }
925
926
927
929 return true;
930 }
931
932
934
935
936
937
938
940 return true;
941 }
942
943
944
945
947
948
949
950
952 unsigned &Cost) const {
953 return false;
954 }
955
956
957
958
959
961 Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const {
962 return false;
963 }
964
965
966
968 return false;
969 }
970
971
972
973
975
976
977
978
980
981
983 EVT VT) const;
984
985
986
987
988 virtual
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1005 if (isVec)
1006 return BooleanVectorContents;
1007 return isFloat ? BooleanFloatContents : BooleanContents;
1008 }
1009
1012 }
1013
1014
1015
1016
1017
1018
1020 EVT ValVT) const {
1022 EVT BoolVT =
1025 return DAG.getNode(ExtendCode, dl, BoolVT, Bool);
1026 }
1027
1028
1030 return SchedPreferenceInfo;
1031 }
1032
1033
1034
1035
1038 }
1039
1040
1041
1043 (void)isDivergent;
1045 assert(RC && "This value type is not natively supported!");
1046 return RC;
1047 }
1048
1049
1050
1051
1053 const Value *) const {
1054 return false;
1055 }
1056
1057
1058
1059
1060
1061
1062
1063
1066 return RC;
1067 }
1068
1069
1070
1072 return RepRegClassCostForVT[VT.SimpleTy];
1073 }
1074
1075
1076
1081 };
1084 unsigned ExpansionFactor) const {
1085 if (ExpansionFactor == 1)
1088 }
1089
1090
1091
1092
1097 }
1098
1100
1101
1103
1104 public:
1106 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
1108 }
1109
1111 return ValueTypeActions[VT.SimpleTy];
1112 }
1113
1115 ValueTypeActions[VT.SimpleTy] = Action;
1116 }
1117 };
1118
1120 return ValueTypeActions;
1121 }
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1138
1139
1140
1141
1142
1145 }
1148 }
1149
1150
1151
1152
1153
1154
1155
1158 }
1159
1160
1161
1162
1163
1166 while (true) {
1169 return VT;
1172 break;
1173 default:
1174 llvm_unreachable("Type is not legal nor is it to be expanded!");
1175 }
1176 }
1177 }
1178
1179
1180
1181
1182
1183
1184
1185
1186
1188 EVT &IntermediateVT,
1189 unsigned &NumIntermediates,
1190 MVT &RegisterVT) const;
1191
1192
1193
1194
1197 unsigned &NumIntermediates, MVT &RegisterVT) const {
1199 RegisterVT);
1200 }
1201
1205
1206
1208
1209
1210
1212
1215
1217
1220 };
1221
1222
1223
1224
1225
1228 unsigned ) const {
1229 return false;
1230 }
1231
1232
1233
1234
1236 bool ForCodeSize = false) const {
1237 return false;
1238 }
1239
1240
1241
1242
1243
1245 return true;
1246 }
1247
1248
1249
1250
1251
1253
1254
1255
1256
1258 EVT ) const {
1259 return false;
1260 }
1261
1262
1265 }
1266
1267
1268
1269
1271
1272
1273 if (Op >= std::size(OpActions[0]))
1278 }
1279
1280
1281
1282
1284 unsigned Scale) const {
1285 return false;
1286 }
1287
1288
1289
1290
1291
1293 unsigned Scale) const {
1295 if (Action != Legal)
1296 return Action;
1297
1298
1299
1300 bool Supported;
1301 switch (Op) {
1302 default:
1313 break;
1314 }
1315
1316 return Supported ? Action : Expand;
1317 }
1318
1319
1320
1322 unsigned EqOpc;
1323 switch (Op) {
1325#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1326 case ISD::STRICT_##DAGN: EqOpc = ISD::DAGN; break;
1327#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1328 case ISD::STRICT_##DAGN: EqOpc = ISD::SETCC; break;
1329#include "llvm/IR/ConstrainedOps.def"
1330 }
1331
1333 }
1334
1335
1336
1337
1338
1340 bool LegalOnly = false) const {
1341 if (LegalOnly)
1343
1344 return (VT == MVT::Other || isTypeLegal(VT)) &&
1347 }
1348
1349
1350
1351
1352
1354 bool LegalOnly = false) const {
1355 if (LegalOnly)
1357
1358 return (VT == MVT::Other || isTypeLegal(VT)) &&
1361 }
1362
1363
1364
1365
1366
1368 bool LegalOnly = false) const {
1369 if (LegalOnly)
1371
1372 return (VT == MVT::Other || isTypeLegal(VT)) &&
1376 }
1377
1378
1379
1382 }
1383
1384
1387 return false;
1388
1391 }
1392
1393
1396
1397 uint64_t BW = DL.getIndexSizeInBits(0u);
1399 return Range <= BW;
1400 }
1401
1402
1403
1407
1408
1410 EVT ConditionVT) const;
1411
1412
1413
1414
1415
1416
1420
1421
1422
1423
1424
1425
1426
1428 return false;
1429
1430
1431
1432
1433
1434
1435 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1436 (NumDests == 3 && NumCmps >= 6);
1437 }
1438
1439
1440
1441
1444 }
1445
1446
1448 return (VT == MVT::Other || isTypeLegal(VT)) &&
1450 }
1451
1452
1453
1454
1456 EVT MemVT) const {
1462 unsigned Shift = 4 * ExtType;
1463 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1464 }
1465
1466
1469 }
1470
1471
1472
1476 }
1477
1478
1480 EVT MemVT) const {
1486 unsigned Shift = 4 * ExtType;
1488 (LegalizeAction)((AtomicLoadExtActions[ValI][MemI] >> Shift) & 0xf);
1490 "Unsupported atomic load extension action.");
1491 return Action;
1492 }
1493
1494
1495
1498 }
1499
1500
1501
1502
1508 "Table isn't big enough!");
1509 return TruncStoreActions[ValI][MemI];
1510 }
1511
1512
1513
1516 }
1517
1518
1519
1524 }
1525
1527 bool LegalOnly) const {
1528 if (LegalOnly)
1530
1532 }
1533
1534
1535
1536
1538 return getIndexedModeAction(IdxMode, VT, IMAB_Load);
1539 }
1540
1541
1546 }
1547
1548
1549
1550
1552 return getIndexedModeAction(IdxMode, VT, IMAB_Store);
1553 }
1554
1555
1560 }
1561
1562
1563
1564
1566 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad);
1567 }
1568
1569
1574 }
1575
1576
1577
1578
1580 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedStore);
1581 }
1582
1583
1588 }
1589
1590
1591
1593
1594
1595
1597 return false;
1598 }
1599
1600
1601
1602
1605
1606
1607 if (Scale != ElemSize && Scale != 1)
1608 return false;
1609 return true;
1610 }
1611
1612
1613
1614
1617 assert((unsigned)CC < std::size(CondCodeActions) &&
1618 ((unsigned)VT.SimpleTy >> 3) < std::size(CondCodeActions[0]) &&
1619 "Table isn't big enough!");
1620
1624 assert(Action != Promote && "Can't promote condition code!");
1625 return Action;
1626 }
1627
1628
1629
1632 }
1633
1634
1635
1639 }
1640
1641
1642
1645 "This operation isn't promoted!");
1646
1647
1648 std::map<std::pair<unsigned, MVT::SimpleValueType>,
1650 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1651 if (PTTI != PromoteToType.end()) return PTTI->second;
1652
1654 "Cannot autopromote this type, add it with AddPromotedToType.");
1655
1657 MVT NVT = VT;
1658 do {
1662 "Didn't find type to promote to!");
1665 return NVT;
1666 }
1667
1669 bool AllowUnknown = false) const {
1671 }
1672
1673
1674
1675
1676
1678 bool AllowUnknown = false) const {
1679
1680 if (auto *PTy = dyn_cast(Ty))
1682
1683 if (auto *VTy = dyn_cast(Ty)) {
1684 Type *EltTy = VTy->getElementType();
1685
1686 if (auto *PTy = dyn_cast(EltTy)) {
1689 }
1691 VTy->getElementCount());
1692 }
1693
1695 }
1696
1698 bool AllowUnknown = false) const {
1699
1700 if (auto *PTy = dyn_cast(Ty))
1702
1703 if (auto *VTy = dyn_cast(Ty)) {
1704 Type *EltTy = VTy->getElementType();
1705 if (auto *PTy = dyn_cast(EltTy)) {
1708 }
1710 VTy->getElementCount());
1711 }
1712
1714 }
1715
1716
1717
1719 bool AllowUnknown = false) const {
1721 }
1722
1723
1724
1726
1727
1729 assert((unsigned)VT.SimpleTy < std::size(RegisterTypeForVT));
1730 return RegisterTypeForVT[VT.SimpleTy];
1731 }
1732
1733
1738 EVT VT1;
1739 MVT RegisterVT;
1740 unsigned NumIntermediates;
1742 NumIntermediates, RegisterVT);
1743 return RegisterVT;
1744 }
1747 }
1749 }
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762 virtual unsigned
1764 std::optional RegisterVT = std::nullopt) const {
1767 std::size(NumRegistersForVT));
1769 }
1771 EVT VT1;
1772 MVT VT2;
1773 unsigned NumIntermediates;
1775 }
1779 return (BitWidth + RegWidth - 1) / RegWidth;
1780 }
1782 }
1783
1784
1785
1786
1790 }
1791
1792
1793
1794
1797 EVT VT) const {
1799 }
1800
1801
1802
1805 return DL.getABITypeAlign(ArgTy);
1806 }
1807
1808
1809
1810
1812
1813
1814
1816 EVT NewVT) const {
1817
1818
1819 if (NewVT.isVector() && !Load->hasOneUse())
1820 return false;
1821
1822 return true;
1823 }
1824
1825
1826
1828
1829
1830
1831
1834 }
1835
1836
1837
1838
1840 return DL.isBigEndian() || VT == MVT::ppcf128;
1841 }
1842
1843
1844
1846 assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
1847 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1848 }
1849
1852 }
1853
1854
1857 }
1858
1859
1860
1861
1862
1863
1864
1867 }
1868
1869
1870
1871
1872
1873
1874
1877 }
1878
1879
1880
1881
1882
1883
1886 }
1887
1888
1889
1890
1891
1892
1893
1896 }
1897
1898
1899
1900
1901
1902
1903
1906 }
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1919 EVT, unsigned AddrSpace = 0, Align Alignment = Align(1),
1921 unsigned * = nullptr) const {
1922 return false;
1923 }
1924
1925
1927 LLT, unsigned AddrSpace = 0, Align Alignment = Align(1),
1929 unsigned * = nullptr) const {
1930 return false;
1931 }
1932
1933
1934
1935
1936
1939 unsigned AddrSpace = 0, Align Alignment = Align(1),
1941 unsigned *Fast = nullptr) const;
1942
1943
1944
1945
1946
1950 unsigned *Fast = nullptr) const;
1951
1952
1953
1954
1955
1956 virtual bool
1958 unsigned AddrSpace = 0, Align Alignment = Align(1),
1960 unsigned *Fast = nullptr) const;
1961
1962
1963
1964
1965
1968 unsigned *Fast = nullptr) const;
1969
1970
1973 unsigned *Fast = nullptr) const;
1974
1975
1976
1977
1978
1979 virtual EVT
1981 const AttributeList & ) const {
1982 return MVT::Other;
1983 }
1984
1985
1986 virtual LLT
1988 const AttributeList & ) const {
1989 return LLT();
1990 }
1991
1992
1993
1994
1995
1996
1997
1998
2000
2001
2003
2004
2006
2007
2008
2010
2012
2013
2014
2016 return StackPointerRegisterToSaveRestore;
2017 }
2018
2019
2020
2024 }
2025
2026
2027
2031 }
2032
2034 report_fatal_error("Funclet EH is not implemented for this target");
2035 }
2036
2037
2039 return MinStackArgumentAlignment;
2040 }
2041
2042
2044
2045
2047
2048
2050
2051
2052
2053 virtual unsigned
2055
2056
2057
2059
2060
2061
2062
2063
2065
2066
2067
2069
2070
2071
2072
2074
2075
2076
2077
2078
2080
2081
2082
2083
2084
2086
2087protected:
2089 bool UseTLS) const;
2090
2091public:
2092
2094
2095
2096
2098
2100
2102 return "";
2103 }
2104
2105
2106
2107
2108 virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const;
2109
2110
2111
2112
2113
2115 Align & ) const {
2116 return false;
2117 }
2118
2119
2120
2121
2122
2123
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2137 return MaxAtomicSizeInBitsSupported;
2138 }
2139
2140
2141
2143 return MaxDivRemBitWidthSupported;
2144 }
2145
2146
2147
2149 return MaxLargeFPConvertBitWidthSupported;
2150 }
2151
2152
2153
2154
2155
2156
2157
2158
2160
2161
2163
2164
2165
2166
2168 return false;
2169 }
2170
2171
2172
2173 virtual bool
2175 return false;
2176 }
2177
2178
2179
2180
2181
2184 llvm_unreachable("Load linked unimplemented on this target");
2185 }
2186
2187
2188
2191 llvm_unreachable("Store conditional unimplemented on this target");
2192 }
2193
2194
2195
2196
2197
2203 llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
2204 }
2205
2206
2207
2208
2211 "Generic atomicrmw expansion unimplemented on this target");
2212 }
2213
2214
2216 llvm_unreachable("Generic cmpxchg expansion unimplemented on this target");
2217 }
2218
2219
2220
2221
2224 "Bit test atomicrmw expansion unimplemented on this target");
2225 }
2226
2227
2228
2229
2232 "Compare arith atomicrmw expansion unimplemented on this target");
2233 }
2234
2235
2236
2237
2238
2242 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
2243 }
2244
2245
2246
2247
2248
2253 }
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2279
2283
2284
2285
2286
2287
2288
2289
2290
2292
2293
2295 return IsSigned;
2296 }
2297
2298
2300 return true;
2301 }
2302
2303
2304
2307 }
2308
2309
2310
2315 }
2316
2317
2318
2319
2322 }
2323
2324
2325
2326
2328 if (SI->getValueOperand()->getType()->isFloatingPointTy())
2331 }
2332
2333
2334
2338 }
2339
2340
2341
2345 }
2346
2347
2348
2355
2357 }
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2372 return nullptr;
2373 }
2374
2375
2376
2379 }
2380
2381
2382
2383
2384
2385
2386
2387
2388
2391 }
2392
2393
2394
2395
2396
2397
2398
2399
2401 EVT VT) const {
2402
2403
2405 return false;
2406
2407
2411 }
2412
2414
2415
2416
2417
2419 return false;
2420 }
2421
2422
2423
2424
2425
2426
2429 return false;
2430 }
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2442 SDValue ConstNode) const {
2443 return true;
2444 }
2445
2446
2447
2448
2449
2450
2452 bool IsSigned) const {
2453 return false;
2454 }
2455
2456
2457
2458
2459
2460
2466 }
2467
2468
2469
2470
2471
2472protected:
2473
2474
2476 BooleanContents = Ty;
2477 BooleanFloatContents = Ty;
2478 }
2479
2480
2481
2483 BooleanContents = IntTy;
2484 BooleanFloatContents = FloatTy;
2485 }
2486
2487
2488
2490 BooleanVectorContents = Ty;
2491 }
2492
2493
2495 SchedPreferenceInfo = Pref;
2496 }
2497
2498
2500
2501
2502
2504
2505
2506
2508 StackPointerRegisterToSaveRestore = R;
2509 }
2510
2511
2512
2513
2514
2515
2517 HasMultipleConditionRegisters = hasManyRegs;
2518 }
2519
2520
2521
2522
2523
2525 HasExtractBitsInsn = hasExtractInsn;
2526 }
2527
2528
2529
2530
2532
2533
2534 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
2535 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
2536 }
2537
2538
2539
2540
2542 assert((unsigned)VT.SimpleTy < std::size(RegClassForVT));
2543 RegClassForVT[VT.SimpleTy] = RC;
2544 }
2545
2546
2547
2548 virtual std::pair<const TargetRegisterClass *, uint8_t>
2550
2551
2552
2554
2555
2556
2557
2559 assert(Op < std::size(OpActions[0]) && "Table isn't big enough!");
2561 }
2564 for (auto Op : Ops)
2566 }
2569 for (auto VT : VTs)
2571 }
2572
2573
2574
2578 MemVT.isValid() && "Table isn't big enough!");
2579 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2580 unsigned Shift = 4 * ExtType;
2583 }
2586 for (auto ExtType : ExtTypes)
2588 }
2591 for (auto MemVT : MemVTs)
2593 }
2594
2595
2596
2600 MemVT.isValid() && "Table isn't big enough!");
2601 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2602 unsigned Shift = 4 * ExtType;
2606 ((uint16_t)Action << Shift);
2607 }
2610 for (auto ExtType : ExtTypes)
2612 }
2615 for (auto MemVT : MemVTs)
2617 }
2618
2619
2620
2624 }
2625
2626
2627
2628
2629
2630
2633 for (auto IdxMode : IdxModes)
2634 setIndexedModeAction(IdxMode, VT, IMAB_Load, Action);
2635 }
2636
2639 for (auto VT : VTs)
2641 }
2642
2643
2644
2645
2646
2647
2650 for (auto IdxMode : IdxModes)
2651 setIndexedModeAction(IdxMode, VT, IMAB_Store, Action);
2652 }
2653
2656 for (auto VT : VTs)
2658 }
2659
2660
2661
2662
2663
2664
2667 setIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad, Action);
2668 }
2669
2670
2671
2672
2673
2674
2677 setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action);
2678 }
2679
2680
2681
2684 for (auto CC : CCs) {
2685 assert(VT.isValid() && (unsigned)CC < std::size(CondCodeActions) &&
2686 "Table isn't big enough!");
2687 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2688
2689
2690
2694 }
2695 }
2698 for (auto VT : VTs)
2700 }
2701
2702
2703
2704
2705
2707 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2708 }
2709
2710
2711
2715 }
2717 MVT DestVT) {
2718 for (auto Op : Ops) {
2721 }
2722 }
2723
2724
2725
2726
2728 for (auto NT : NTs) {
2729 assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
2730 TargetDAGCombineArray[NT >> 3] |= 1 << (NT & 7);
2731 }
2732 }
2733
2734
2736 MinFunctionAlignment = Alignment;
2737 }
2738
2739
2740
2742 PrefFunctionAlignment = Alignment;
2743 }
2744
2745
2746
2747
2750 MaxBytesForAlignment = MaxBytes;
2751 }
2752
2753
2755 MinStackArgumentAlignment = Alignment;
2756 }
2757
2758
2759
2760
2761
2763 MaxAtomicSizeInBitsSupported = SizeInBits;
2764 }
2765
2766
2767
2769 MaxDivRemBitWidthSupported = SizeInBits;
2770 }
2771
2772
2773
2775 MaxLargeFPConvertBitWidthSupported = SizeInBits;
2776 }
2777
2778
2780 MinCmpXchgSizeInBits = SizeInBits;
2781 }
2782
2783
2785 SupportsUnalignedAtomics = UnalignedSupported;
2786 }
2787
2788public:
2789
2790
2791
2792
2793
2794
2795
2796
2797
2800 Type *& ) const {
2801 return false;
2802 }
2803
2804
2805
2806
2807
2808
2809
2810
2811
2819 };
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2832 Type *Ty, unsigned AddrSpace,
2834
2835
2836
2838 return false;
2839 }
2840
2841
2843 int64_t MaxOffset) const {
2844 return 0;
2845 }
2846
2847
2848
2849
2851 return true;
2852 }
2853
2854
2855
2856
2858 return true;
2859 }
2860
2861
2862
2863
2864
2866
2867
2868
2870
2871
2872 return Value == 0;
2873 }
2874
2875
2876
2877
2878
2879
2881 return nullptr;
2882 }
2883
2884
2885
2886
2888 return (From->isIntegerTy() || From->isFloatingPointTy()) &&
2890 }
2891
2892
2894
2895 switch (Opcode) {
2931 return true;
2932 default: return false;
2933 }
2934 }
2935
2936
2937 virtual bool isBinOp(unsigned Opcode) const {
2938
2940 return true;
2941
2942 switch (Opcode) {
2958 return true;
2959 default:
2960 return false;
2961 }
2962 }
2963
2964
2965
2966
2967
2969 return false;
2970 }
2971
2972
2973
2974
2975
2976
2978 return false;
2979 }
2980
2985 }
2986
2987
2989
2991 }
2992
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3005 switch (I->getOpcode()) {
3006 case Instruction::FPExt:
3009 return true;
3010 break;
3011 case Instruction::ZExt:
3012 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
3013 return true;
3014 break;
3015 case Instruction::SExt:
3016 break;
3017 default:
3019 }
3021 }
3022
3023
3024
3025
3026
3027
3028
3033
3034
3035
3038 return false;
3039
3040
3041 unsigned LType;
3042 if (isa(Ext))
3044 else {
3045 assert(isa(Ext) && "Unexpected ext type!");
3047 }
3048
3050 }
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3063 return false;
3064 }
3065
3070 }
3071
3072
3073
3074
3077 }
3078
3079
3080
3082 return false;
3083 }
3084
3085
3086
3088
3089
3090
3091 virtual bool
3094 return false;
3095 }
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3119 Align & ) const {
3120 return false;
3121 }
3122
3123
3125
3126
3127
3129
3130
3131
3132
3133
3134
3135
3136
3140 unsigned Factor) const {
3141 return false;
3142 }
3143
3144
3145
3146
3147
3148
3149
3151 unsigned Factor) const {
3152 return false;
3153 }
3154
3155
3156
3157
3158
3159
3160
3161
3162
3166 return false;
3167 }
3168
3169
3170
3171
3172
3173
3174
3175
3176
3180 return false;
3181 }
3182
3183
3184
3185
3188 "invalid fpext types");
3189 return false;
3190 }
3191
3192
3193
3194
3196 LLT DestTy, LLT SrcTy) const {
3197 return false;
3198 }
3199
3200
3201
3202
3204 EVT DestVT, EVT SrcVT) const {
3206 "invalid fpext types");
3208 }
3209
3210
3211
3213
3214
3215
3218 return false;
3219 }
3220
3221
3222
3225 return false;
3226 }
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3240 EVT) const {
3241 return false;
3242 }
3243
3244
3245
3246
3247
3248
3249
3250
3251
3253 LLT) const {
3254 return false;
3255 }
3256
3257
3259 return false;
3260 }
3261
3262
3263
3264
3265
3267 assert((MI.getOpcode() == TargetOpcode::G_FADD ||
3268 MI.getOpcode() == TargetOpcode::G_FSUB ||
3269 MI.getOpcode() == TargetOpcode::G_FMUL) &&
3270 "unexpected node in FMAD forming combine");
3272 case 16:
3274 case 32:
3276 case 64:
3278 default:
3279 break;
3280 }
3281
3282 return false;
3283 }
3284
3285
3286
3287
3291 "unexpected node in FMAD forming combine");
3293 }
3294
3295
3296
3299 return false;
3300 }
3301
3302
3303
3304
3306 return false;
3307 }
3308
3309
3310
3311
3313 EVT VT) const {
3314 return false;
3315 }
3316
3317
3318
3319
3320
3321
3323 Type *Ty) const {
3324 return false;
3325 }
3326
3327
3328
3329
3330
3332 unsigned Index) const {
3333 return false;
3334 }
3335
3336
3337
3339 return false;
3340 }
3341
3342
3343
3344
3345
3347 return false;
3348 }
3349
3350
3351
3352
3353
3355 bool MathUsed) const {
3356
3357
3359 return false;
3360
3361
3362
3363
3364
3365
3367 return false;
3369 }
3370
3371
3372
3374 return false;
3375 }
3376
3377
3378
3379
3381
3382
3383
3385 return false;
3386 }
3387
3388
3389
3391 const APInt &AndMask) const {
3392 unsigned ShCt = AndMask.getBitWidth() - 1;
3394 }
3395
3396
3397
3399
3400
3401
3404 }
3405
3406
3407
3409
3410
3412
3413
3414
3417 return false;
3418 }
3419
3420
3421
3422
3427 return nullptr;
3428 }
3429
3430
3433 }
3434
3437 }
3438
3439
3442 }
3443
3444
3445
3446
3448 CmpLibcallCCs[Call] = CC;
3449 }
3450
3451
3452
3453
3454
3456 return CmpLibcallCCs[Call];
3457 }
3458
3459
3460
3463 }
3464
3465
3468 }
3469
3470
3471
3472
3473
3475
3476
3477
3478
3479
3481
3482
3483private:
3485
3486
3487
3488
3489
3490
3491 bool HasMultipleConditionRegisters;
3492
3493
3494
3495
3496
3497 bool HasExtractBitsInsn;
3498
3499
3500
3501
3502
3503 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
3504
3505
3506
3507
3508 bool JumpIsExpensive;
3509
3510
3511
3513
3514
3515
3517
3518
3519
3521
3522
3523
3525
3526
3527 Align MinStackArgumentAlignment;
3528
3529
3530
3531 Align MinFunctionAlignment;
3532
3533
3534
3535 Align PrefFunctionAlignment;
3536
3537
3538 Align PrefLoopAlignment;
3539
3540 unsigned MaxBytesForAlignment;
3541
3542
3543
3544 unsigned MaxAtomicSizeInBitsSupported;
3545
3546
3547
3548 unsigned MaxDivRemBitWidthSupported;
3549
3550
3551
3552 unsigned MaxLargeFPConvertBitWidthSupported;
3553
3554
3555
3556 unsigned MinCmpXchgSizeInBits;
3557
3558
3559 bool SupportsUnalignedAtomics;
3560
3561
3562
3563 Register StackPointerRegisterToSaveRestore;
3564
3565
3566
3570
3571
3572
3573
3574
3575
3576
3578
3579
3580
3581
3583
3584
3585
3586
3587
3588
3590
3591
3592
3593
3594
3595
3597
3598
3599
3600
3601
3603
3604
3605
3607
3608
3609
3611
3612
3613
3614
3615
3616
3617
3619
3620
3621
3622
3623
3624
3625
3627
3628 ValueTypeActionImpl ValueTypeActions;
3629
3630private:
3631
3632
3633
3634 unsigned char
3636
3637
3638
3639
3640
3641
3642
3644 PromoteToType;
3645
3646
3647 RTLIB::RuntimeLibcallsInfo Libcalls;
3648
3649
3650
3651 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
3652
3653
3654
3655 enum IndexedModeActionsBits {
3656 IMAB_Store = 0,
3657 IMAB_Load = 4,
3658 IMAB_MaskedStore = 8,
3659 IMAB_MaskedLoad = 12
3660 };
3661
3662 void setIndexedModeAction(unsigned IdxMode, MVT VT, unsigned Shift,
3665 (unsigned)Action < 0xf && "Table isn't big enough!");
3666 unsigned Ty = (unsigned)VT.SimpleTy;
3667 IndexedModeActions[Ty][IdxMode] &= ~(0xf << Shift);
3668 IndexedModeActions[Ty][IdxMode] |= ((uint16_t)Action) << Shift;
3669 }
3670
3671 LegalizeAction getIndexedModeAction(unsigned IdxMode, MVT VT,
3672 unsigned Shift) const {
3674 "Table isn't big enough!");
3675 unsigned Ty = (unsigned)VT.SimpleTy;
3676 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] >> Shift) & 0xf);
3677 }
3678
3679protected:
3680
3681
3682
3684
3685
3686
3687
3688
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3702
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3717
3719
3720
3721
3722
3723
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3738
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3752
3754
3755
3756
3758
3759
3761
3762
3763
3766
3767
3768
3771
3773};
3774
3775
3776
3777
3778
3779
3781public:
3784
3787
3789
3791
3795 return false;
3796 }
3797
3798
3799
3800
3801
3802
3803
3807 }
3808
3809
3810
3811
3812
3813
3814
3817 return MRI.hasOneNonDBGUse(N0);
3818 }
3819
3821 return false;
3822 }
3823
3824
3825
3826
3831 return false;
3832 }
3833
3834
3835
3836
3842 return false;
3843 }
3844
3845
3846
3847
3850 return false;
3851 }
3852
3853
3854
3856
3859 }
3860
3861 virtual const MCExpr *
3865 llvm_unreachable("Need to implement this hook if target has custom JTIs");
3866 }
3867
3868
3871
3872
3873
3874 virtual const MCExpr *
3876 unsigned JTI, MCContext &Ctx) const;
3877
3878
3879
3881
3882
3883
3884
3885
3886
3887
3888
3889 virtual bool
3891 unsigned OpNo) const {
3892 return false;
3893 }
3894
3897
3901 const SDValue OldRHS) const;
3902
3907 bool IsSignaling = false) const;
3908
3914 }
3915
3921 }
3922
3923
3924
3927 MakeLibCallOptions CallOptions,
3928 const SDLoc &dl,
3930
3931
3932
3933
3935 const uint32_t *CallerPreservedMask,
3938
3939
3940
3941
3942
3943
3944
3945
3952
3954 bool LT, bool LO) :
3956
3959
3961 Old = O;
3963 return true;
3964 }
3965 };
3966
3967
3968
3969
3970
3971
3972 virtual bool
3974 const MemOp &Op, unsigned DstAS, unsigned SrcAS,
3976
3977
3978
3979
3980
3982 const APInt &DemandedElts,
3983 TargetLoweringOpt &TLO) const;
3984
3985
3987 TargetLoweringOpt &TLO) const;
3988
3989
3990
3991
3994 const APInt &DemandedElts,
3996 return false;
3997 }
3998
3999
4000
4001
4002
4005 TargetLoweringOpt &TLO) const;
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4022 TargetLoweringOpt &TLO, unsigned Depth = 0,
4023 bool AssumeSingleUse = false) const;
4024
4025
4026
4028 KnownBits &Known, TargetLoweringOpt &TLO,
4029 unsigned Depth = 0,
4030 bool AssumeSingleUse = false) const;
4031
4032
4033
4035 DAGCombinerInfo &DCI) const;
4036
4037
4038
4040 const APInt &DemandedElts,
4041 DAGCombinerInfo &DCI) const;
4042
4043
4044
4045
4047 const APInt &DemandedElts,
4049 unsigned Depth = 0) const;
4050
4051
4052
4055 unsigned Depth = 0) const;
4056
4057
4058
4060 const APInt &DemandedElts,
4062 unsigned Depth = 0) const;
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4079 APInt &KnownUndef, APInt &KnownZero,
4080 TargetLoweringOpt &TLO, unsigned Depth = 0,
4081 bool AssumeSingleUse = false) const;
4082
4083
4084
4086 DAGCombinerInfo &DCI) const;
4087
4088
4089
4090 virtual bool
4093 return true;
4094 }
4095
4096
4097
4098
4099
4102 const APInt &DemandedElts,
4104 unsigned Depth = 0) const;
4105
4106
4107
4108
4109
4112 const APInt &DemandedElts,
4114 unsigned Depth = 0) const;
4115
4116
4117
4118
4119
4123 unsigned Depth = 0) const;
4124
4125
4126
4127
4131
4132
4133
4134
4135
4137 const APInt &DemandedElts,
4139 unsigned Depth = 0) const;
4140
4141
4142
4143
4144
4147 const APInt &DemandedElts,
4149 unsigned Depth = 0) const;
4150
4151
4152
4153
4154
4155
4158 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
4159
4160
4161
4162
4163
4164
4167 const APInt &DemandedElts,
4169 TargetLoweringOpt &TLO,
4170 unsigned Depth = 0) const;
4171
4172
4173
4174
4178
4179
4180
4181
4185
4186
4187
4188
4189 virtual bool
4192 bool ConsiderFlags, unsigned Depth) const;
4193
4194
4195
4196
4197
4201
4202
4203
4205
4206
4207
4208
4211 bool SNaN = false,
4212 unsigned Depth = 0) const;
4213
4214
4215
4217 APInt &UndefElts,
4219 unsigned Depth = 0) const;
4220
4221
4222
4226 }
4227
4232
4233 public:
4235
4238
4244
4249
4251
4253 };
4254
4255
4256
4258
4259
4260
4262
4263
4265
4266
4267
4269 bool foldBooleans, DAGCombinerInfo &DCI,
4270 const SDLoc &dl) const;
4271
4272
4274
4275
4276
4277 virtual bool
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4294
4295
4296
4297
4298
4299
4300
4301
4302
4305 SDValue ShiftLHS = N->getOperand(0);
4307 return false;
4310 return false;
4311 return true;
4312 }
4313
4314
4315
4316
4317
4318
4319
4320
4321
4323 bool IsAfterLegal) const {
4324 return true;
4325 }
4326
4327
4328
4330 return true;
4331 }
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4352 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const {
4354 }
4355
4356
4357
4358
4359
4361 return true;
4362 }
4363
4364
4365
4366
4367
4369
4371 }
4372
4373
4374
4375
4377 EVT ) const {
4378 return false;
4379 }
4380
4381
4382
4383
4385 return false;
4386 }
4387
4388
4389
4391 return false;
4392 }
4393
4394
4395
4397 return false;
4398 }
4399
4400
4402
4403
4405
4406
4407
4408
4411 }
4412
4413
4414
4415
4416
4421 }
4422
4423
4424
4425
4427 bool LegalOps, bool OptForSize,
4429 unsigned Depth = 0) const;
4430
4434 unsigned Depth = 0) const {
4438 if (!Neg)
4440
4442 return Neg;
4443
4444
4448 }
4449
4450
4451
4453 bool LegalOps, bool OptForSize,
4454 unsigned Depth = 0) const {
4457 }
4458
4459
4460
4462 bool OptForSize, unsigned Depth = 0) const {
4465 }
4466
4467
4468
4469
4470
4471
4472
4473
4476 unsigned NumParts, MVT PartVT, std::optionalCallingConv::ID CC) const {
4477 return false;
4478 }
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4493 unsigned &PhysReg, int &Cost) const {
4494 return false;
4495 }
4496
4497
4500 const SDValue *Parts, unsigned NumParts,
4502 std::optionalCallingConv::ID CC) const {
4504 }
4505
4506
4507
4508
4509
4515 }
4516
4517
4518
4519
4523 };
4524
4525
4526
4527
4528
4542
4543
4544
4546
4547
4549
4563
4565
4571
4573 DL = dl;
4574 return *this;
4575 }
4576
4578 Chain = InChain;
4579 return *this;
4580 }
4581
4582
4585 RetTy = ResultType;
4589 Args = std::move(ArgsList);
4590
4593 return *this;
4594 }
4595
4599 RetTy = ResultType;
4600 IsInReg = ResultAttrs.hasAttribute(Attribute::InReg);
4601 RetSExt = ResultAttrs.hasAttribute(Attribute::SExt);
4602 RetZExt = ResultAttrs.hasAttribute(Attribute::ZExt);
4603 NoMerge = ResultAttrs.hasAttribute(Attribute::NoMerge);
4604
4608 Args = std::move(ArgsList);
4609 return *this;
4610 }
4611
4615 RetTy = ResultType;
4616
4617 IsInReg = Call.hasRetAttr(Attribute::InReg);
4619 Call.doesNotReturn() ||
4620 (!isa(Call) && isa(Call.getNextNode()));
4623 RetSExt = Call.hasRetAttr(Attribute::SExt);
4624 RetZExt = Call.hasRetAttr(Attribute::ZExt);
4625 NoMerge = Call.hasFnAttr(Attribute::NoMerge);
4626
4628
4629 CallConv = Call.getCallingConv();
4631 Args = std::move(ArgsList);
4632
4633 CB = &Call;
4634
4635 return *this;
4636 }
4637
4640 return *this;
4641 }
4642
4645 return *this;
4646 }
4647
4650 return *this;
4651 }
4652
4655 return *this;
4656 }
4657
4660 return *this;
4661 }
4662
4665 return *this;
4666 }
4667
4670 return *this;
4671 }
4672
4675 return *this;
4676 }
4677
4680 return *this;
4681 }
4682
4685 return *this;
4686 }
4687
4690 return *this;
4691 }
4692
4695 return *this;
4696 }
4697
4700 return *this;
4701 }
4702
4705 return *this;
4706 }
4707
4709 return Args;
4710 }
4711 };
4712
4713
4715
4716
4724
4728
4731 return *this;
4732 }
4733
4736 return *this;
4737 }
4738
4741 return *this;
4742 }
4743
4746 return *this;
4747 }
4748
4750 bool Value = true) {
4754 return *this;
4755 }
4756 };
4757
4758
4759
4760
4761
4762 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
4763
4764
4765
4766
4767
4768
4773 }
4774
4775
4777
4778
4779
4780
4785 {
4786
4787 return true;
4788 }
4789
4790
4791
4792
4794 bool ,
4797 const SDLoc & ,
4800 }
4801
4802
4803
4804
4805
4806
4808 return false;
4809 }
4810
4811
4812
4813
4815 return false;
4816 }
4817
4818
4819
4820
4823 report_fatal_error("Named registers not implemented for this target");
4824 }
4825
4826
4827
4828
4829
4830
4831
4835 return VT.bitsLT(MinVT) ? MinVT : VT;
4836 }
4837
4838
4839
4840
4841 virtual bool
4843 bool isVarArg,
4845 return false;
4846 }
4847
4848
4849
4850
4851
4852 virtual bool
4854 return DL.isLittleEndian();
4855 }
4856
4857
4858
4860 return nullptr;
4861 }
4862
4863
4864
4867 }
4868
4869
4870
4871
4872
4873
4874
4875
4878 return Chain;
4879 }
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4897
4898
4899
4900
4901
4902
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4917 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
4918 }
4919
4920
4922
4923
4924
4927 return nullptr;
4928 }
4929
4932
4933#ifndef NDEBUG
4934
4936#endif
4937
4938
4939
4940
4941
4942
4943
4944
4945
4947 return false;
4948 }
4949
4957 C_Unknown
4959
4961
4967
4968
4975
4976
4978
4979
4980
4982
4983
4984
4986
4987
4988
4989
4991
4992
4994
4995
4998
4999
5000
5002
5003
5004
5006 };
5007
5009
5010
5011
5012
5013
5016 const CallBase &Call) const;
5017
5018
5019
5022
5023
5024
5027
5028
5029
5030
5031
5035
5036
5038
5039 using ConstraintPair = std::pair<StringRef, TargetLowering::ConstraintType>;
5041
5042
5043
5044
5045
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057 virtual std::pair<unsigned, const TargetRegisterClass *>
5060
5063 if (ConstraintCode == "m")
5065 if (ConstraintCode == "o")
5067 if (ConstraintCode == "X")
5069 if (ConstraintCode == "p")
5072 }
5073
5074
5075
5076
5078
5079
5080
5082 std::vector &Ops,
5084
5085
5088 const AsmOperandInfo &OpInfo,
5090
5091
5092
5096
5097
5098
5099
5100
5102 bool IsAfterLegalTypes,
5105 bool IsAfterLegalTypes,
5107
5111
5112
5113
5114
5115
5119
5120
5121
5122
5123
5127
5128
5129
5130
5131
5133 return 0;
5134 }
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5155 int Enabled, int &RefinementSteps,
5156 bool &UseOneConstNR, bool Reciprocal) const {
5158 }
5159
5160
5161
5162
5163
5164
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5178 int Enabled, int &RefinementSteps) const {
5180 }
5181
5182
5183
5184
5185
5188
5189
5190
5194 }
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5249
5250
5251
5252
5254
5255
5256
5257
5258
5259
5261
5262
5263
5264
5265
5268
5269
5270
5271
5272
5274
5275
5276
5277
5278
5279
5282
5283
5284
5285
5286
5287
5290
5291
5293
5294
5296
5297
5299
5300
5301
5302
5304
5305
5306
5307
5308
5309
5312
5313
5314
5315
5317
5318
5319
5320
5321
5322
5323
5327
5328
5329
5330
5331
5333
5334
5335
5337
5338
5339
5340
5341
5343
5344
5345
5346
5348
5349
5350
5351
5353 SDValue Op, unsigned NumBitsPerElt) const;
5354
5355
5356
5357
5358
5360
5361
5362
5363
5365
5366
5367
5368
5370
5371
5372
5373
5375
5376
5377
5378
5379
5380
5381
5383 bool IsNegative = false) const;
5384
5385
5386
5387
5389
5390
5391
5392
5394
5395
5396
5397
5398
5400
5401
5402
5403
5405
5406
5407
5408
5409
5411
5412
5413
5414
5416
5417
5418
5419
5422
5423
5424
5425
5427
5428
5429
5432
5433
5434
5436
5437
5438
5439
5440
5441
5442
5443
5446 bool IsCompressedMemory) const;
5447
5448
5449
5450
5451
5454
5455
5456
5457
5458
5459
5462
5463
5464
5466
5467
5468
5470
5471
5472
5474
5475
5476
5478
5479
5480
5482
5483
5484
5485
5486
5490
5491
5492
5495
5496
5497
5500
5501
5502
5505
5506
5507
5508
5509
5510
5511
5512
5517
5518
5519
5523
5524
5525
5527
5528
5530
5531
5532
5534
5535
5536
5538
5539
5540
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5567 SDValue EVL, bool &NeedInvert, const SDLoc &dl,
5568 SDValue &Chain, bool IsSignaling = false) const;
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5584
5585
5586
5587
5588
5591
5592
5593
5595
5599 }
5600
5601
5604
5605
5606
5610
5611
5612
5613
5614
5616
5617
5619 return true;
5620 }
5621
5622
5623
5625
5626private:
5628 const SDLoc &DL, DAGCombinerInfo &DCI) const;
5630 const SDLoc &DL, DAGCombinerInfo &DCI) const;
5631
5632 SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
5634 DAGCombinerInfo &DCI,
5636
5637
5638 SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
5640 DAGCombinerInfo &DCI, const SDLoc &DL) const;
5641
5644 DAGCombinerInfo &DCI, const SDLoc &DL,
5649
5652 DAGCombinerInfo &DCI, const SDLoc &DL,
5657};
5658
5659
5660
5661
5663 SmallVectorImplISD::OutputArg &Outs,
5664 const TargetLowering &TLI, const DataLayout &DL);
5665
5666}
5667
5668#endif
unsigned const MachineRegisterInfo * MRI
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
Atomic ordering constants.
This file contains the simple types necessary to represent the attributes associated with functions a...
block Block Frequency Analysis
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static cl::opt< unsigned > CostThreshold("dfa-cost-threshold", cl::desc("Maximum cost accepted for the transformation"), cl::Hidden, cl::init(50))
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
Implement a low-level type suitable for MachineInstr level instruction selection.
Machine Check Debug Module
unsigned const TargetRegisterInfo * TRI
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Class for arbitrary precision integers.
unsigned getBitWidth() const
Return the number of bits in the APInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
an instruction that atomically reads a memory location, combines it with another value,...
bool isFloatingPointOperation() const
BinOp getOperation() const
bool getValueAsBool() const
Return the attribute's value as a boolean.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
CCState - This class holds information needed while lowering arguments and return values.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
This class represents a range of values.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
constexpr bool isScalar() const
Exactly one element.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Class to represent function types.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Common base class shared among various IRBuilders.
A wrapper class for inspecting calls to intrinsic functions.
constexpr unsigned getScalarSizeInBits() const
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
Represents a single loop in the control flow graph.
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
@ INVALID_SIMPLE_VALUE_TYPE
uint64_t getScalarSizeInBits() const
bool isInteger() const
Return true if this is an integer or a vector integer type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
ElementCount getVectorElementCount() const
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
Representation of each machine instruction.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is an abstract virtual class for memory operations.
A Module instance is used to store all the information related to an LLVM module.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool hasOneUse() const
Return true if there is exactly one use of this node.
bool use_empty() const
Return true if there are no uses of this node.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
const TargetLowering & getTargetLoweringInfo() const
const DataLayout & getDataLayout() const
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
MachineFunction & getMachineFunction() const
LLVMContext * getContext() const
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setAttributes(const CallBase *Call, unsigned ArgIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes.
LegalizeTypeAction getTypeAction(MVT VT) const
void setTypeAction(MVT VT, LegalizeTypeAction Action)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parame...
virtual Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool isOperationExpand(unsigned Op, EVT VT) const
Return true if the specified operation is illegal on this target or unlikely to be made legal with cu...
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
EVT getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
virtual bool enableAggressiveFMAFusion(LLT Ty) const
Return true if target always benefits from combining into FMA for a given value type.
virtual void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const
Perform a bit test atomicrmw using a target-specific intrinsic.
void setOperationAction(ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action)
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *) const
Allows target to decide about the register class of the specific value that is live outside the defin...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const
Returns the size of the platform's va_list object.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const
virtual bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
void setMaxDivRemBitWidthSupported(unsigned SizeInBits)
Set the size in bits of the maximum div/rem the backend supports.
virtual bool hasAndNot(SDValue X) const
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
void initActions()
Initialize all of the actions to default values.
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
virtual bool isShuffleMaskLegal(ArrayRef< int >, EVT) const
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always benefits from combining into FMA for a given value type.
virtual bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const
Does this target support complex deinterleaving with the given operation and type.
virtual bool shouldRemoveRedundantExtend(SDValue Op) const
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...
bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
SDValue promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool, EVT ValVT) const
Promote the given target boolean to a target boolean of the given type.
virtual bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const
Returns true if be combined with to form an ISD::FMAD.
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
LegalizeAction getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
virtual bool canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOnly) const
virtual bool isSelectSupported(SelectSupportKind) const
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual bool isEqualityCmpFoldedWithSignedCmp() const
Return true if instruction generated for equality comparison is folded with instruction generated for...
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
void setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
virtual Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const
Create the IR node for the given complex deinterleaving operation.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
virtual MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
bool isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const
Return true if Load and Ext can form an ExtLoad.
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
LegalizeTypeAction getTypeAction(MVT VT) const
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
virtual bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
virtual bool allowsMisalignedMemoryAccesses(LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
LLT handling variant.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
virtual bool isSafeMemOpType(MVT) const
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
virtual void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const
Perform a cmpxchg expansion using a target-specific method.
virtual CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) const
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.
virtual bool isCtpopFast(EVT VT) const
Return true if ctpop instruction is fast.
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
bool isPaddedAtMostSignificantBitsWhenStored(EVT VT) const
Indicates if any padding is guaranteed to go at the most significant bits when storing the type to me...
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
@ TypeScalarizeScalableVector
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
unsigned getMinCmpXchgSizeInBits() const
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(....
virtual bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const
Return true if an fpext operation input to an Opcode operation is free (for instance,...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
virtual bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI, SmallVectorImpl< Instruction * > &DeadInsts) const
Lower an interleave intrinsic to a target specific store intrinsic.
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
void setMaxBytesForAlignment(unsigned MaxBytes)
bool isOperationLegalOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal using promotion.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool hasBitTest(SDValue X, SDValue Y) const
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual bool needsFixedCatchObjects() const
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
void setMaxLargeFPConvertBitWidthSupported(unsigned SizeInBits)
Set the size in bits of the maximum fp convert the backend supports.
virtual EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &) const
Returns the target specific optimal type for load and store operations as a result of memset,...
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
virtual bool isCheapToSpeculateCttz(Type *Ty) const
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool useFPRegsForHalfType() const
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
void setPrefLoopAlignment(Align Alignment)
Set the target's preferred loop alignment.
virtual bool softPromoteHalfType() const
virtual bool areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const
Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
virtual bool isFPImmLegal(const APFloat &, EVT, bool ForCodeSize=false) const
Returns true if the target can instruction select the specified FP immediate natively.
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
virtual bool optimizeFMulOrFDivAsShiftAddBitcast(SDNode *N, SDValue FPConst, SDValue IntPow2) const
unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const
Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...
SelectSupportKind
Enum that describes what type of support for selects the target has.
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
virtual bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
virtual bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance,...
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Let target indicate that an extending atomic load of the specified type is legal.
virtual bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const
Returns true if the index type for a masked gather/scatter requires extending.
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X,...
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
virtual StringRef getStackProbeSymbolName(const MachineFunction &MF) const
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales.
virtual bool preferScalarizeSplat(SDNode *N) const
virtual bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl< Instruction * > &DeadInsts) const
Lower a deinterleave intrinsic to a target specific load intrinsic.
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
bool isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
virtual bool shouldExpandCmpUsingSelects(EVT VT) const
Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean ...
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
virtual LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &) const
LLT returning variant.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
virtual void emitExpandAtomicRMW(AtomicRMWInst *AI) const
Perform a atomicrmw expansion using a target-specific way.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
virtual bool hasStackProbeSymbol(const MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
Returns the type for the shift amount of a shift opcode.
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
virtual Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const
Certain targets have context sensitive alignment requirements, where one type has the alignment requi...
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
virtual bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
virtual bool shouldExtendTypeInLibCall(EVT Type) const
Returns true if arguments should be extended in lib calls.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const
Return true if it is profitable to fold a pair of shifts into a mask.
virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
bool isStrictFPEnabled() const
Return true if the target support strict float operation.
virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const
Return true if creating a shift of the type by the given amount is not profitable.
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
virtual bool shouldFoldSelectWithSingleBitTest(EVT VT, const APInt &AndMask) const
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
virtual bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const
Return true if pulling a binary operation into a select with an identity constant is profitable.
virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal for a comparison of the specified types on this ...
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
LegalizeAction getAtomicLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Same as getLoadExtAction, but for atomic loads.
bool EnableExtLdPromotion
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
MVT getProgramPointerTy(const DataLayout &DL) const
Return the type for code pointers, which is determined by the program address space specified through...
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)
virtual bool isJumpTableRelative() const
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
virtual bool preferIncOfAddToSubOfNot(EVT VT) const
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
unsigned getMaxDivRemBitWidthSupported() const
Returns the size in bits of the maximum div/rem the backend supports.
virtual bool isLegalAddImmediate(int64_t) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
virtual bool shouldKeepZExtForFP16Conv() const
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...
virtual AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *RMWI) const
Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
virtual bool shouldConsiderGEPOffsetSplit() const
const ValueTypeActionImpl & getValueTypeActions() const
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
virtual bool isTruncateFree(SDValue Val, EVT VT2) const
Return true if truncating the specific node Val to type VT2 is free.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Return true if it is profitable to reduce a load to a smaller type.
virtual bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const
Return true if the @llvm.experimental.vector.match intrinsic should be expanded for vector type ‘VT’ ...
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const
Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a cust...
virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <>...
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
virtual ~TargetLoweringBase()=default
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name)
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
virtual bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
virtual ISD::NodeType getExtendForAtomicCmpSwapArg() const
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
BooleanContent
Enum that describes how the target represents true/false values.
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
virtual bool shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) const
virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const
Return true if integer divide is usually cheaper than a sequence of several shifts,...
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the 'representative' register class for the specified value type.
virtual bool isZExtFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
bool isPredictableSelectExpensive() const
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right...
virtual bool mergeStoresAfterLegalization(EVT MemVT) const
Allow store merging for the specified type after legalization in addition to before legalization.
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual bool isProfitableToHoist(Instruction *I) const
unsigned getGatherAllAliasesMaxDepth() const
virtual LegalizeAction getCustomOperationAction(SDNode &Op) const
How to legalize this custom operation?
virtual bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *) const
IR version.
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
virtual bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the 'representative' register class for the specified value type.
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
virtual bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const
Return true if it's profitable to narrow operations of type SrcVT to DestVT.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
TargetLoweringBase(const TargetLoweringBase &)=delete
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
bool isAtomicLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified atomic load with extension is legal on this target.
virtual bool isBinOp(unsigned Opcode) const
Return true if the node is a math/logic binary operator.
virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const
Returns if it's reasonable to merge stores to MemVT size.
LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
virtual bool preferABDSToABSWithNSW(EVT VT) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
virtual bool getAddrModeArguments(const IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal on this target.
virtual bool hasInlineStackProbe(const MachineFunction &MF) const
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool shouldExpandPartialReductionIntrinsic(const IntrinsicInst *I) const
Return true if the @llvm.experimental.vector.partial.reduce.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
void setOperationPromotedToType(ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT)
unsigned getMaxLargeFPConvertBitWidthSupported() const
Returns the size in bits of the maximum larget fp convert the backend supports.
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, LLT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
virtual bool isCheapToSpeculateCtlz(Type *Ty) const
Return true if it is cheap to speculate a call to intrinsic ctlz.
virtual bool shouldExpandCttzElements(EVT VT) const
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
virtual bool signExtendConstant(const ConstantInt *C) const
Return true if this constant should be sign extended when promoting to a larger type.
virtual bool isTruncateFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const
AndOrSETCCFoldKind
Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ....
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
virtual bool shouldScalarizeBinop(SDValue VecOp) const
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
Align getPrefFunctionAlignment() const
Return the preferred function alignment.
Align getMinFunctionAlignment() const
Return the minimum function alignment.
virtual AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
virtual bool useSoftFloat() const
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x,...
BooleanContent getBooleanContents(EVT Type) const
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
virtual int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const
Return the prefered common base offset.
virtual bool isVectorClearMaskLegal(ArrayRef< int >, EVT) const
Similar to isShuffleMaskLegal.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool hasTargetDAGCombine(ISD::NodeType NT) const
If true, the target has custom DAG combine transformations that it can perform for the specified node...
virtual bool fallBackToDAGISel(const Instruction &Inst) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...
virtual bool shouldSplatInsEltVarIndex(EVT) const
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
LegalizeAction getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
NegatibleCost
Enum that specifies when a float negation is beneficial.
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation has solution on this target.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that's to be used to test the result of the comparison libcall against zero.
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
virtual unsigned preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const
virtual void emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const
Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.
virtual bool shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
virtual bool isFMADLegal(const MachineInstr &MI, LLT Ty) const
Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action)
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
virtual bool isLegalAddScalableImmediate(int64_t) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
std::vector< ArgListEntry > ArgListTy
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
virtual bool shouldAlignPointerArgs(CallInst *, unsigned &, Align &) const
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)
virtual bool isVScaleKnownToBeAPowerOfTwo() const
Return true only if vscale must be a power of two.
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
virtual MachineMemOperand::Flags getTargetMMOFlags(const MemSDNode &Node) const
This callback is used to inspect load/store SDNode.
virtual Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
void setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
virtual bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual LLVM_READONLY LLT getPreferredShiftAmountTy(LLT ShiftValueTy) const
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
bool isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) const
Return true if it is beneficial to expand an @llvm.powi.
virtual EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)
virtual AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal or custom for a comparison of the specified type...
virtual bool isComplexDeinterleavingSupported() const
Does this target support complex deinterleaving.
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual bool addressingModeSupportsTLS(const GlobalValue &) const
Returns true if the targets addressing mode can target thread local storage (TLS).
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
virtual bool shouldConvertPhiType(Type *From, Type *To) const
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
virtual bool isFAbsFree(EVT VT) const
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
virtual bool preferZeroCompareBranch() const
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
virtual bool generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
virtual bool hasPairedLoad(EVT, Align &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual bool convertSelectOfConstantsToMath(EVT VT) const
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
virtual bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
virtual MVT getVPExplicitVectorLengthTy() const
Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB,...
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
TargetLoweringBase & operator=(const TargetLoweringBase &)=delete
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
static ISD::NodeType getExtendForContent(BooleanContent Content)
virtual bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool supportKCFIBundles() const
Return true if the target supports kcfi operand bundles.
SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT.
SDValue buildSDIVPow2WithCMov(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const
Build sdiv by power-of-2 with conditional move instructions Ref: "Hacker's Delight" by Henry Warren 1...
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
Examine constraint type and operand type and determine a weight value.
SDValue expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const
Expand VP_CTLZ/VP_CTLZ_ZERO_UNDEF nodes.
bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::[US]MULO.
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
virtual bool isDesirableToCommuteWithShift(const MachineInstr &MI, bool IsAfterLegal) const
GlobalISel - return true if it is profitable to move this shift by a constant amount through its oper...
virtual bool supportPtrAuthBundles() const
Return true if the target supports ptrauth operand bundles.
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Vector Op.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const
Determine which of the bits of FrameIndex FIOp are known to be 0.
virtual SDValue visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
This is the helper function to return the newly negated expression if the cost is not expensive.
SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const
virtual unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
virtual bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
SDValue expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const
Expand VP_BSWAP nodes.
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) const
Soften the operands of a comparison.
SDValue getCheaperOrNeutralNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) const
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
SDValue expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const
Expand a VECREDUCE_SEQ_* into an explicit ordered calculation.
virtual Register getRegisterByName(const char *RegName, LLT Ty, const MachineFunction &MF) const
Return the register ID of the name passed in.
SDValue expandCTLZ(SDNode *N, SelectionDAG &DAG) const
Expand CTLZ/CTLZ_ZERO_UNDEF nodes.
SDValue expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const
Expand BITREVERSE nodes.
SDValue expandCTTZ(SDNode *N, SelectionDAG &DAG) const
Expand CTTZ/CTTZ_ZERO_UNDEF nodes.
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expansion.
SDValue expandABD(SDNode *N, SelectionDAG &DAG) const
Expand ABDS/ABDU nodes.
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const
virtual Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const
Determine the known alignment for the pointer value R.
std::vector< AsmOperandInfo > AsmOperandInfoVector
SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::[US]SHLSAT.
SDValue expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const
Expand check for floating point class.
virtual bool isTargetCanonicalConstantNode(SDValue Op) const
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
SDValue expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const
Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.
SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
This is the helper function to return the newly negated expression only when the cost is cheaper.
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.
SDValue SimplifyMultipleUseDemandedVectorElts(SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const
Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all bits from only some vector eleme...
virtual void verifyTargetSDNode(const SDNode *N) const
Check the given SDNode. Aborts if it is invalid.
virtual bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue unwrapAddress(SDValue N) const
void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::S(ADD|SUB)O.
SDValue expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const
Expand VP_BITREVERSE nodes.
SDValue expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative=false) const
Expand ABS nodes.
SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const
Expand a VECREDUCE_* into an explicit calculation.
bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const
Check to see if the specified operand of the specified instruction is a constant integer.
virtual bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const
Target-specific splitting of values into parts that fit a register storing a legal type.
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node.
SDValue expandVPCTTZElements(SDNode *N, SelectionDAG &DAG) const
Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_UNDEF nodes.
SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const
Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will ...
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const
Expand float to UINT conversion.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
virtual bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
virtual SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const
Target-specific combining of register parts into its original value.
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const
Insert explicit copies in entry and exit blocks.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
bool expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) const
Expand an SREM or UREM using SDIV/UDIV or SDIVREM/UDIVREM, if legal.
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.
SDValue expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *N, SelectionDAG &DAG) const
Expand fminimumnum/fmaximumnum into multiple comparison with selects.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDValue expandVectorSplice(SDNode *Node, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::VECTOR_SPLICE.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
SDValue expandCTPOP(SDNode *N, SelectionDAG &DAG) const
Expand CTPOP nodes.
SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const
Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will ...
SDValue expandVectorNaryOpBySplitting(SDNode *Node, SelectionDAG &DAG) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
SDValue expandBSWAP(SDNode *N, SelectionDAG &DAG) const
Expand BSWAP nodes.
TargetLowering & operator=(const TargetLowering &)=delete
SDValue expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const
Expand fminimum/fmaximum into multiple comparison with selects.
SDValue CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned NumBitsPerElt) const
Expand CTTZ via Table Lookup.
virtual bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
If SNaN is false,.
bool expandDIVREMByConstant(SDNode *N, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue()) const
Attempt to expand an n-bit div/rem/divrem by constant using a n/2-bit urem by constant and other arit...
virtual bool isDesirableToPullExtFromShl(const MachineInstr &MI) const
GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x),...
SDValue getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) const
Get a pointer to a sub-vector of type SubVecVT at index Idx located in memory for a vector of type Ve...
virtual void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool isPositionIndependent() const
std::pair< StringRef, TargetLowering::ConstraintType > ConstraintPair
virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) const
Returns true if the specified base+offset is a legal indexed addressing mode for this target.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, const DenormalMode &Mode) const
Return a target-dependent comparison result if the input operand is suitable for use with a square ro...
ConstraintGroup getConstraintPreferences(AsmOperandInfo &OpInfo) const
Given an OpInfo with list of constraints codes as strings, return a sorted Vector of pairs of constra...
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const
Expand float(f32) to SINT(i64) conversion.
virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const
SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) const
Tries to build a legal vector shuffle using the provided parameters or equivalent variations.
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
Return a reciprocal estimate value for the input operand.
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
std::pair< SDValue, SDValue > scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Turn load of vector type into a load of the individual elements.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Op.
void forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, EVT WideVT, const SDValue LL, const SDValue LH, const SDValue RL, const SDValue RH, SDValue &Lo, SDValue &Hi) const
forceExpandWideMUL - Unconditionally expand a MUL into either a libcall or brute force via a wide mul...
virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
virtual bool isDesirableToCommuteXorWithShift(const SDNode *N) const
Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT...
TargetLowering(const TargetLowering &)=delete
virtual bool shouldSimplifyDemandedVectorElts(SDValue Op, const TargetLoweringOpt &TLO) const
Return true if the target supports simplifying demanded vector elements by converting them to undefs.
bool isConstFalseVal(SDValue N) const
Return if the N is a constant or constant vector equal to the false value from getBooleanContents().
SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const
Increments memory address Addr according to the type of the value DataVT that should be stored.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
Check whether a given call node is in tail position within its function.
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
virtual SDValue getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) const
Return a target-dependent result if the input operand is not suitable for use with a square root esti...
SDValue expandRoundInexactToOdd(EVT ResultVT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG) const
Truncate Op to ResultVT.
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const
For most targets, an LLVM type must be broken down into multiple smaller types.
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
Try to simplify a setcc built with the specified operands and cc.
SDValue expandFunnelShift(SDNode *N, SelectionDAG &DAG) const
Expand funnel shift.
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
bool LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) const
Legalize a SETCC or VP_SETCC with given LHS and RHS and condition code CC on the current target.
bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const
Return if N is a True value when extended to VT.
bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &DemandedBits, TargetLoweringOpt &TLO) const
Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isConstTrueVal(SDValue N) const
Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
virtual ArrayRef< MCPhysReg > getRoundingControlRegisters() const
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const
Expand VP_CTPOP nodes.
SDValue expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::[US]DIVFIX[SAT].
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const
Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base a...
virtual bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const
Return true if it is profitable to move this shift by a constant amount through its operand,...
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const
SDValue expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const
Expand VP_CTTZ/VP_CTTZ_ZERO_UNDEF nodes.
virtual SDValue visitMaskedStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
SDValue expandVECTOR_COMPRESS(SDNode *Node, SelectionDAG &DAG) const
Expand a vector VECTOR_COMPRESS into a sequence of extract element, store temporarily,...
virtual const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const
This method returns the constant pool value that will be loaded by LD.
virtual bool useLoadStackGuardNode(const Module &M) const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
SDValue expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) const
Expand round(fp) to fp conversion.
SDValue createSelectForFMINNUM_FMAXNUM(SDNode *Node, SelectionDAG &DAG) const
Try to convert the fminnum/fmaxnum to a compare/select sequence.
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
SDValue expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const
Expand rotations.
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual AndOrSETCCFoldKind isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const
virtual void HandleByVal(CCState *, unsigned &, Align) const
Target-specific cleanup for formal ByVal parameters.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const
Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
virtual bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const
Allows the target to handle physreg-carried dependency in target-specific way.
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::[US]CMP.
virtual bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) const
void expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) const
Expand shift-by-parts.
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
This method will be invoked for all target nodes and for any target-independent nodes that the target...
virtual bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT].
virtual bool isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const
On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use eithe...
SDValue expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::[US][MIN|MAX].
SDValue expandVectorFindLastActive(SDNode *N, SelectionDAG &DAG) const
Expand VECTOR_FIND_LAST_ACTIVE nodes.
virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
virtual MVT getJumpTableRegTy(const DataLayout &DL) const
void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const
Method for building the DAG expansion of ISD::U(ADD|SUB)O.
virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
virtual SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const
Targets may override this function to provide custom SREM lowering for power-of-2 denominators.
bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const
Expand UINT(i64) to double(f64) conversion.
bool expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively,...
SDValue expandAVG(SDNode *N, SelectionDAG &DAG) const
Expand vector/scalar AVGCEILS/AVGCEILU/AVGFLOORS/AVGFLOORU nodes.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &, const Type *RetTy) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
virtual bool isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode, EVT) const
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
bool isPointerTy() const
True if this is an instance of PointerType.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
bool isIntegerTy() const
True if this is an instance of IntegerType.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FADD
Simple binary floating point operators.
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ BRIND
BRIND - Indirect branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ FMINIMUMNUM
FMINIMUMNUM/FMAXIMUMNUM - minimumnum/maximumnum that is same with FMINNUM_IEEE and FMAXNUM_IEEE besid...
@ ABDS
ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...
static const int LAST_LOADEXT_TYPE
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
static const int LAST_INDEXED_MODE
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
This is an optimization pass for GlobalISel generic memory operations.
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
int popcount(T Value) noexcept
Count the number of set bits in a value.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
ComplexDeinterleavingOperation
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
CodeGenOptLevel
Code generation optimization level.
AtomicOrdering
Atomic ordering for LLVM's memory model.
EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx)
ComplexDeinterleavingRotation
DWARFExpression::Operation Op
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
Represent subnormal handling kind for floating point instruction inputs and outputs.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isByteSized() const
Return true if the bit size is a multiple of 8.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool isVector() const
Return true if this is a vector value type.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
bool isInteger() const
Return true if this is an integer or a vector integer type.
ConstraintInfo()=default
Default constructor.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
bool isDstAligned(Align AlignCheck) const
bool allowOverlap() const
bool isFixedDstAlign() const
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
Align getDstAlign() const
bool isMemcpyStrSrc() const
bool isAligned(Align AlignCheck) const
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
bool isSrcAligned(Align AlignCheck) const
bool isMemcpyWithFixedDstAlign() const
bool isZeroMemset() const
Align getSrcAlign() const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
These are IR-level optimization flags that may be propagated to SDNodes.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
std::optional< unsigned > fallbackAddressSpace
MachineMemOperand::Flags flags
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
This contains information for each constraint that we are lowering.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
MVT ConstraintVT
The ValueType for the operand value.
std::string ConstraintCode
This contains the actual string for the code, like "m".
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
unsigned getMatchedOperand() const
If this is an input matching constraint, this method returns the output operand it matches.
bool isMatchingInputConstraint() const
Return true of this is an input operand that is a matching constraint like "4".
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setConvergent(bool Value=true)
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, const CallBase &Call)
CallLoweringInfo & setCFIType(const ConstantInt *Type)
CallLoweringInfo & setInRegister(bool Value=true)
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
SDValue ConvergenceControlToken
SmallVector< ISD::InputArg, 32 > Ins
CallLoweringInfo & setVarArg(bool Value=true)
bool IsPostTypeLegalization
SmallVector< SDValue, 4 > InVals
const ConstantInt * CFIType
std::optional< PtrAuthInfo > PAI
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setZExtResult(bool Value=true)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setIsPreallocated(bool Value=true)
CallLoweringInfo & setSExtResult(bool Value=true)
CallLoweringInfo & setNoReturn(bool Value=true)
CallLoweringInfo & setConvergenceControlToken(SDValue Token)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setPtrAuth(PtrAuthInfo Value)
CallLoweringInfo(SelectionDAG &DAG)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})
bool isBeforeLegalizeOps() const
bool isAfterLegalizeDAG() const
CombineLevel getDAGCombineLevel()
void AddToWorklist(SDNode *N)
bool isCalledByLegalizer() const
bool recursivelyDeleteUnusedNodes(SDNode *N)
bool isBeforeLegalize() const
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO)
This structure is used to pass arguments to makeLibCall function.
MakeLibCallOptions & setIsPostTypeLegalization(bool Value=true)
MakeLibCallOptions & setDiscardResult(bool Value=true)
ArrayRef< EVT > OpsVTBeforeSoften
bool IsPostTypeLegalization
MakeLibCallOptions & setIsSigned(bool Value=true)
MakeLibCallOptions & setTypeListBeforeSoften(ArrayRef< EVT > OpsVT, EVT RetVT, bool Value=true)
MakeLibCallOptions & setNoReturn(bool Value=true)
This structure contains the information necessary for lowering pointer-authenticating indirect calls.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
bool CombineTo(SDValue O, SDValue N)
bool LegalOperations() const
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)