TargetRegisterInfo.cpp Source File (original) (raw)

29#include "llvm/Config/llvm-config.h"

39#include

40#include

42#define DEBUG_TYPE "target-reg-info"

44using namespace llvm;

48 cl::desc("A threshold of live range size which may cause "

49 "high compile time cost in global splitting."),

58 : InfoDesc(ID), SubRegIndexNames(SRINames), SubRegIdxRanges(SubIdxRanges),

59 SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE),

60 CoveringLanes(SRICoveringLanes), RCInfos(RCIs), RCVTLists(RCVTLists),

61 HwMode(Mode) {}

70 if (MI && TII->isTriviallyReMaterializable(*MI) &&

72 return false;

73 return true;

74}

79 RegisterSet.set(SR);

80}

86 for (unsigned Reg : RegisterSet.set_bits()) {

87 if (Checked[Reg])

88 continue;

90 if (!RegisterSet[SR] && $is\_contained$ (Exceptions, Reg)) {

91 dbgs() << "Error: Super register " << printReg(SR, this)

92 << " of reserved register " << printReg(Reg, this)

93 << " is not reserved.\n";

94 return false;

95 }

99 Checked.set(SR);

100 }

101 }

102 return true;

103}

104

105namespace llvm {

106

110 if (!Reg)

111 OS << "$noreg";

114 else if (Reg.isVirtual()) {

115 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";

116 if (Name != "") {

117 OS << '%' << Name;

118 } else {

119 OS << '%' << Register::virtReg2Index(Reg);

120 }

121 } else if ( TRI )

122 OS << '$' << "physreg" << Reg.id();

123 else if (Reg < TRI->getNumRegs()) {

124 OS << '$';

125 printLowerCase(TRI->getName(Reg), OS);

126 } else

128

129 if (SubIdx) {

131 OS << ':' << TRI->getSubRegIndexName(SubIdx);

132 else

133 OS << ":sub(" << SubIdx << ')';

134 }

135 });

136}

137

140

141 if ( TRI ) {

142 OS << "Unit~" << Unit;

143 return;

144 }

145

146

147 if (Unit >= TRI->getNumRegUnits()) {

148 OS << "BadUnit~" << Unit;

149 return;

150 }

151

152

154 assert(Roots.isValid() && "Unit has no roots.");

155 OS << TRI->getName(*Roots);

156 for (++Roots; Roots.isValid(); ++Roots)

157 OS << '~' << TRI->getName(*Roots);

158 });

159}

160

165 } else {

167 }

168 });

169}

170

178 else {

179 OS << "_";

180 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&

181 "Generic registers must have a valid type");

182 }

183 });

184}

185

186}

187

188

189

193 return RC;

194

196 ++It) {

199 return SubRC;

200 }

201 return nullptr;

202}

203

204template

207 TypeT Ty) {

208 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);

209 assert(Reg.isPhysical() && "reg must be a physical register");

210

211 bool IsDefault = [&]() {

212 if constexpr (std::is_same_v<TypeT, MVT>)

213 return Ty == MVT::Other;

214 else

215 return !Ty.isValid();

216 }();

217

218

219

222 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(Reg) &&

224 BestRC = RC;

225 }

226

227 if constexpr (std::is_same_v<TypeT, MVT>)

228 assert(BestRC && "Couldn't find the register class");

229 return BestRC;

230}

231

232template

236 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);

238 "Reg1/Reg2 must be a physical register");

239

240 bool IsDefault = [&]() {

241 if constexpr (std::is_same_v<TypeT, MVT>)

242 return Ty == MVT::Other;

243 else

244 return !Ty.isValid();

245 }();

246

247

248

251 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) &&

252 RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))

253 BestRC = RC;

254 }

255

256 if constexpr (std::is_same_v<TypeT, MVT>)

257 assert(BestRC && "Couldn't find the register class");

258 return BestRC;

259}

260

263 return ::getMinimalPhysRegClass(this, Reg, VT);

264}

265

268 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, VT);

269}

270

273 return ::getMinimalPhysRegClass(this, Reg, Ty);

274}

275

278 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, Ty);

279}

280

281

282

288 R.set(PR);

289}

290

294 if (RC) {

295

297 if (SubClass)

299 } else {

301 if (C->isAllocatable())

303 }

304

305

309

310 return Allocatable;

311}

312

313static inline

317 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)

318 if (unsigned Common = *A++ & *B++)

320 return nullptr;

321}

322

326

327 if (A == B)

328 return A;

329 if ( || )

330 return nullptr;

331

332

333

334 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);

335}

336

340 unsigned Idx) const {

341 assert(A && B && "Missing register class");

342 assert(Idx && "Bad sub-register index");

343

344

346 if (RCI.getSubReg() == Idx)

347

348

349 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);

350 return nullptr;

351}

352

356 unsigned &PreA, unsigned &PreB) const {

357 assert(RCA && SubA && RCB && SubB && "Invalid arguments");

358

359

360

361

362

363

364

365

366

367

368

369

370

372 unsigned *BestPreA = &PreA;

373 unsigned *BestPreB = &PreB;

378 }

379

380

381

383

387

391 continue;

392

393

395 if (FinalA != FinalB)

396 continue;

397

398

400 continue;

401

402

403 BestRC = RC;

404 *BestPreA = IA.getSubReg();

405 *BestPreB = IB.getSubReg();

406

407

409 return BestRC;

410 }

411 }

412 return BestRC;

413}

414

415

416

419 unsigned DefSubReg,

421 unsigned SrcSubReg) {

422

423 if (DefRC == SrcRC)

424 return true;

425

426

427 unsigned SrcIdx, DefIdx;

428 if (SrcSubReg && DefSubReg) {

429 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,

430 SrcIdx, DefIdx) != nullptr;

431 }

432

433

434

435 if (!SrcSubReg) {

438 }

439

440

441 if (SrcSubReg)

442 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;

443

444

445 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;

446}

447

449 unsigned DefSubReg,

451 unsigned SrcSubReg) const {

452

454}

455

456

462 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =

463 MRI.getRegAllocationHints(VirtReg);

464

465 if (!Hints_MRI)

466 return false;

467

469

470 bool Skip = (Hints_MRI->first != 0);

471 for (auto Reg : Hints_MRI->second) {

472 if (Skip) {

473 Skip = false;

474 continue;

475 }

476

477

480 Phys = VRM->getPhys(Phys);

481

482

483

484 if (!HintedRegs.insert(Phys).second)

485 continue;

486

488 continue;

489 if (MRI.isReserved(Phys))

490 continue;

491

492

493

495 continue;

496

497

499 }

500 return false;

501}

502

505 if (!PhysReg)

506 return false;

507 const uint32_t *callerPreservedRegs =

509 if (callerPreservedRegs) {

510 assert(PhysReg.isPhysical() && "Expected physical register");

511 return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;

512 }

513 return false;

514}

515

518}

519

522}

523

525 const uint32_t *mask1) const {

527 for (unsigned I = 0; I < N; ++I)

528 if ((mask0[I] & mask1[I]) != mask0[I])

529 return false;

530 return true;

531}

532

537 if (Reg.isPhysical()) {

538

539

540

542 assert(RC && "Unable to deduce the register class");

544 }

545 LLT Ty = MRI.getType(Reg);

548

549

550 RC = MRI.getRegClass(Reg);

551 assert(RC && "Unable to deduce the register class");

553}

554

559 unsigned BestIdx = 0;

560 unsigned BestCover = 0;

561

563

565 continue;

567

568 if (SubRegMask == LaneMask) {

569 BestIdx = Idx;

570 break;

571 }

572

573

574 if ((SubRegMask & ~LaneMask).any())

575 continue;

576

577 unsigned PopCount = SubRegMask.getNumLanes();

579 if (PopCount > BestCover) {

580 BestCover = PopCount;

581 BestIdx = Idx;

582 }

583 }

584

585

586 if (BestIdx == 0)

587 return false;

588

589 NeededIndexes.push_back(BestIdx);

590

591

592

593 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);

594 while (LanesLeft.any()) {

595 unsigned BestIdx = 0;

596 int BestCover = std::numeric_limits::min();

597 for (unsigned Idx : PossibleIndexes) {

599

600 if (SubRegMask == LanesLeft) {

601 BestIdx = Idx;

602 break;

603 }

604

605

606

607

608 if ((SubRegMask & ~LanesLeft).any())

609 continue;

610

611

612 const int Cover = (SubRegMask & LanesLeft).getNumLanes();

613 if (Cover > BestCover) {

614 BestCover = Cover;

615 BestIdx = Idx;

616 }

617 }

618

619 if (BestIdx == 0)

620 return false;

621

622 NeededIndexes.push_back(BestIdx);

623

624 LanesLeft &= ~getSubRegIndexLaneMask(BestIdx);

625 }

626

627 return BestIdx;

628}

629

632 "This is not a subregister index");

634}

635

638 "This is not a subregister index");

640}

641

645 while (true) {

647 if (->isCopyLike())

648 return SrcReg;

649

651 if (MI->isCopy())

652 CopySrcReg = MI->getOperand(1).getReg();

653 else {

654 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");

655 CopySrcReg = MI->getOperand(2).getReg();

656 }

657

659 return CopySrcReg;

660

661 SrcReg = CopySrcReg;

662 }

663}

664

667 while (true) {

669

670 if (->isCopyLike())

671 return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();

672

674 if (MI->isCopy())

675 CopySrcReg = MI->getOperand(1).getReg();

676 else {

677 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");

678 CopySrcReg = MI->getOperand(2).getReg();

679 }

680

681

682

683 if (!CopySrcReg.isVirtual() || MRI ->hasOneNonDBGUse(CopySrcReg))

685

686 SrcReg = CopySrcReg;

687 }

688}

689

692 assert( Offset .getScalable() && "Scalable offsets are not handled");

694}

695

698 unsigned PrependFlags,

700 assert((PrependFlags &

703 "Unsupported prepend flag");

706 OffsetExpr.push_back(dwarf::DW_OP_deref);

709 OffsetExpr.push_back(dwarf::DW_OP_deref);

713}

714

715#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

720}

721#endif

unsigned const MachineRegisterInfo * MRI

This file contains the simple types necessary to represent the attributes associated with functions a...

This file implements the BitVector class.

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

This file contains constants used for implementing Dwarf debug support.

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallSet class.

static const TargetRegisterClass * getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg, TypeT Ty)

static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)

getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...

static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)

static const TargetRegisterClass * getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1, MCRegister Reg2, TypeT Ty)

static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))

static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)

Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)

Append Ops with operations to apply the Offset.

static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)

Prepend DIExpr with the given opcodes and optionally turn it into a stack value.

CallingConv::ID getCallingConv() const

getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...

constexpr bool isValid() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

LiveInterval - This class represents the liveness of a register, or stack slot.

MCRegUnitRootIterator enumerates the root registers of a register unit.

unsigned getNumSubRegIndices() const

Return the number of sub-register indices understood by the target.

iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, excluding Reg.

iterator_range< MCSuperRegIterator > superregs_inclusive(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, including Reg.

unsigned getNumRegs() const

Return the number of registers this target has (useful for sizing arrays holding per register informa...

Wrapper class representing physical registers. Should be passed by value.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

constexpr unsigned id() const

bool shouldRealignStack() const

Return true if stack realignment is forced by function attributes or if the stack alignment.

bool isStackRealignable() const

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

const RegisterBank * getRegBankOrNull(Register Reg) const

Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...

const TargetRegisterClass * getRegClassOrNull(Register Reg) const

Return the register class of Reg, or null if Reg has not been assigned a register class yet.

Simple wrapper around std::function<void(raw_ostream&)>.

const char * getName() const

Get a user friendly name of this register bank.

Wrapper class representing virtual and physical registers.

static constexpr bool isStackSlot(unsigned Reg)

isStackSlot - Sometimes it is useful to be able to store a non-negative frame index in a variable tha...

static int stackSlot2Index(Register Reg)

Compute the frame index from a register value representing a stack slot.

static unsigned virtReg2Index(Register Reg)

Convert a virtual register number to a 0-based index.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

static constexpr bool isVirtualRegister(unsigned Reg)

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StackOffset holds a fixed and a scalable offset in bytes.

StringRef - Represent a constant reference to a string, i.e.

std::string lower() const

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

TargetInstrInfo - Interface to description of machine instruction set.

bool isAllocatable() const

Return true if this register class may be used to create virtual registers.

bool hasSubClass(const TargetRegisterClass *RC) const

Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

const uint32_t * getSubClassMask() const

Returns a bit vector of subclasses, including this one.

ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const

Returns the preferred order for allocating registers from this register class in MF.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

const TargetRegisterClass *const * regclass_iterator

const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const

Returns the Register Class of a physical register of the given type, picking the most sub register cl...

iterator_range< regclass_iterator > regclasses() const

virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const

Region split has a high compile time cost especially for large live range.

virtual bool canRealignStack(const MachineFunction &MF) const

True if the stack can be realigned for the target.

virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const

Returns the largest legal sub-class of RC that supports the sub-register index Idx.

bool getCoveringSubRegIndexes(const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const

Try to find one or more subregister indexes to cover LaneMask.

const TargetRegisterClass * getRegClass(unsigned i) const

Returns the register class associated with the enumeration value.

unsigned composeSubRegIndices(unsigned a, unsigned b) const

Return the subregister index you get from composing two subregister indices.

const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const

Find the largest common subclass of A and B.

const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const

Returns the Register Class of a physical register of the given type, picking the most sub register cl...

void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const

Mark a register and all its aliases as reserved in the given set.

bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const

Return true if all bits that are set in mask mask0 are also set in mask1.

TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const

Return the size in bits of a register from class RC.

virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const

Return a mask of call-preserved registers for the given calling convention on the current function.

virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const

Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...

virtual ~TargetRegisterInfo()

virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const

LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const

Return a bitmask representing the parts of a register that are covered by SubIdx.

bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const

Returns true if for every register in the set all super registers are part of the set as well.

const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const

Return the maximal subclass of the given register class that is allocatable or NULL.

virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const

Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...

const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const

Find a common super-register class if it exists.

unsigned getSubRegIdxSize(unsigned Idx) const

Get the size of the bit range covered by a sub-register index.

static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)

Debugging helper: dump register in human readable form to dbgs() stream.

virtual bool shouldRealignStack(const MachineFunction &MF) const

True if storage within the function requires the stack pointer to be aligned more than the normal cal...

TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0)

DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const

Prepends a DWARF expression for Offset to DIExpression Expr.

const TargetRegisterClass * getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2, MVT VT=MVT::Other) const

Returns the common Register Class of two physical registers of the given type, picking the most sub r...

virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const

This is a wrapper around getCallPreservedMask().

unsigned getSubRegIdxOffset(unsigned Idx) const

Get the offset of the bit range covered by a sub-register index.

virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const

Return a subclass of the specified register class A so that each register in it has a sub-register of...

virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const

Gets the DWARF expression opcodes for Offset.

BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const

Returns a bitset indexed by register number indicating if a register is allocatable or not.

virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const

Get a list of 'hint' registers that the register allocator should try first when allocating a physica...

const TargetRegisterClass * getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2, LLT Ty=LLT()) const

Returns the common Register Class of two physical registers of the given type, picking the most sub r...

virtual const TargetInstrInfo * getInstrInfo() const

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)

Create Printable object to print virtual registers and physical registers on a raw_ostream.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)

Create Printable object to print register classes or register banks on a raw_ostream.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

constexpr bool any() const

unsigned getNumLanes() const

Extra information, not in MCRegisterDesc, about registers.

SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...