TargetRegisterInfo.cpp Source File (original) (raw)

29#include "llvm/Config/llvm-config.h"

39#include

40#include

42#define DEBUG_TYPE "target-reg-info"

44using namespace llvm;

48 cl::desc("A threshold of live range size which may cause "

49 "high compile time cost in global splitting."),

58 : InfoDesc(ID), SubRegIndexNames(SRINames), SubRegIdxRanges(SubIdxRanges),

59 SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE),

60 CoveringLanes(SRICoveringLanes), RCInfos(RCIs), RCVTLists(RCVTLists),

61 HwMode(Mode) {}

70 if (MI && TII->isTriviallyReMaterializable(*MI) &&

72 return false;

73 return true;

74}

79 RegisterSet.set(SR);

80}

86 for (unsigned Reg : RegisterSet.set_bits()) {

87 if (Checked[Reg])

88 continue;

90 if (!RegisterSet[SR] && $is\_contained$ (Exceptions, Reg)) {

91 dbgs() << "Error: Super register " << printReg(SR, this)

92 << " of reserved register " << printReg(Reg, this)

93 << " is not reserved.\n";

94 return false;

95 }

99 Checked.set(SR);

100 }

101 }

102 return true;

103}

104

108 if (!Reg)

109 OS << "$noreg";

110 else if (Reg.isStack())

111 OS << "SS#" << Reg.stackSlotIndex();

112 else if (Reg.isVirtual()) {

114 if (Name != "") {

115 OS << '%' << Name;

116 } else {

117 OS << '%' << Reg.virtRegIndex();

118 }

119 } else if ( TRI )

120 OS << '$' << "physreg" << Reg.id();

122 OS << '$';

124 } else

126

127 if (SubIdx) {

129 OS << ':' << TRI->getSubRegIndexName(SubIdx);

130 else

131 OS << ":sub(" << SubIdx << ')';

132 }

133 });

134}

135

138

139 if ( TRI ) {

140 OS << "Unit~" << static_cast<unsigned>(Unit);

141 return;

142 }

143

144

145 if (static_cast<unsigned>(Unit) >= TRI->getNumRegUnits()) {

146 OS << "BadUnit~" << static_cast<unsigned>(Unit);

147 return;

148 }

149

150

153 OS << TRI->getName(*Roots);

154 for (++Roots; Roots.isValid(); ++Roots)

155 OS << '~' << TRI->getName(*Roots);

156 });

157}

158

164 } else {

166 }

167 });

168}

169

174 if (RegInfo.getRegClassOrNull(Reg))

175 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();

176 else if (RegInfo.getRegBankOrNull(Reg))

177 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();

178 else {

179 OS << "_";

180 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&

181 "Generic registers must have a valid type");

182 }

183 });

184}

185

186

187

191 return RC;

192

194 ++It) {

197 return SubRC;

198 }

199 return nullptr;

200}

201

202template

205 TypeT Ty) {

206 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);

207 assert(Reg.isPhysical() && "reg must be a physical register");

208

209 bool IsDefault = [&]() {

210 if constexpr (std::is_same_v<TypeT, MVT>)

211 return Ty == MVT::Other;

212 else

213 return !Ty.isValid();

214 }();

215

216

217

220 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(Reg) &&

222 BestRC = RC;

223 }

224

225 if constexpr (std::is_same_v<TypeT, MVT>)

226 assert(BestRC && "Couldn't find the register class");

227 return BestRC;

228}

229

230template

234 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);

236 "Reg1/Reg2 must be a physical register");

237

238 bool IsDefault = [&]() {

239 if constexpr (std::is_same_v<TypeT, MVT>)

240 return Ty == MVT::Other;

241 else

242 return !Ty.isValid();

243 }();

244

245

246

249 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) &&

250 RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))

251 BestRC = RC;

252 }

253

254 if constexpr (std::is_same_v<TypeT, MVT>)

255 assert(BestRC && "Couldn't find the register class");

256 return BestRC;

257}

258

261 return ::getMinimalPhysRegClass(this, Reg, VT);

262}

263

266 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, VT);

267}

268

271 return ::getMinimalPhysRegClass(this, Reg, Ty);

272}

273

276 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, Ty);

277}

278

279

280

288

292 if (RC) {

293

295 if (SubClass)

297 } else {

299 if (C->isAllocatable())

301 }

302

303

307

308 return Allocatable;

309}

310

311static inline

315 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)

316 if (unsigned Common = *A++ & *B++)

318 return nullptr;

319}

320

324

325 if (A == B)

326 return A;

327 if ( || )

328 return nullptr;

329

330

331

332 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);

333}

334

338 unsigned Idx) const {

339 assert(A && B && "Missing register class");

340 assert(Idx && "Bad sub-register index");

341

342

344 if (RCI.getSubReg() == Idx)

345

346

347 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);

348 return nullptr;

349}

350

354 unsigned &PreA, unsigned &PreB) const {

355 assert(RCA && SubA && RCB && SubB && "Invalid arguments");

356

357

358

359

360

361

362

363

364

365

366

367

368

370 unsigned *BestPreA = &PreA;

371 unsigned *BestPreB = &PreB;

376 }

377

378

379

381

385

389 continue;

390

391

393 if (FinalA != FinalB)

394 continue;

395

396

398 continue;

399

400

401 BestRC = RC;

402 *BestPreA = IA.getSubReg();

403 *BestPreB = IB.getSubReg();

404

405

407 return BestRC;

408 }

409 }

410 return BestRC;

411}

412

416

417

418

419

420 if (DefRC == SrcRC && DefSubReg == SrcSubReg)

421 return DefRC;

422

423

424 unsigned SrcIdx, DefIdx;

425 if (SrcSubReg && DefSubReg) {

427 DefIdx);

428 }

429

430

431

432 if (!SrcSubReg) {

435 }

436

437

438 if (SrcSubReg)

440

441

443}

444

449

450

456 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =

457 MRI.getRegAllocationHints(VirtReg);

458

459 if (!Hints_MRI)

460 return false;

461

463

464 bool Skip = (Hints_MRI->first != 0);

465 for (auto Reg : Hints_MRI->second) {

466 if (Skip) {

467 Skip = false;

468 continue;

469 }

470

471

474 Phys = VRM->getPhys(Phys);

475

476

477

478 if (!HintedRegs.insert(Phys).second)

479 continue;

480

482 continue;

483 if (MRI.isReserved(Phys))

484 continue;

485

486

487

489 continue;

490

491

493 }

494 return false;

495}

496

499 if (!PhysReg)

500 return false;

501 const uint32_t *callerPreservedRegs =

503 if (callerPreservedRegs) {

504 assert(PhysReg.isPhysical() && "Expected physical register");

505 return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;

506 }

507 return false;

508}

509

513

517

519 const uint32_t *mask1) const {

521 for (unsigned I = 0; I < N; ++I)

522 if ((mask0[I] & mask1[I]) != mask0[I])

523 return false;

524 return true;

525}

526

531 if (Reg.isPhysical()) {

532

533

534

536 assert(RC && "Unable to deduce the register class");

538 }

539 LLT Ty = MRI.getType(Reg);

540 if (Ty.isValid())

541 return Ty.getSizeInBits();

542

543

544 RC = MRI.getRegClass(Reg);

545 assert(RC && "Unable to deduce the register class");

547}

548

553 unsigned BestIdx = 0;

554 unsigned BestCover = 0;

555

557

559 continue;

561

562 if (SubRegMask == LaneMask) {

563 BestIdx = Idx;

564 break;

565 }

566

567

568 if ((SubRegMask & ~LaneMask).any())

569 continue;

570

571 unsigned PopCount = SubRegMask.getNumLanes();

573 if (PopCount > BestCover) {

574 BestCover = PopCount;

575 BestIdx = Idx;

576 }

577 }

578

579

580 if (BestIdx == 0)

581 return false;

582

583 NeededIndexes.push_back(BestIdx);

584

585

586

588 while (LanesLeft.any()) {

589 unsigned BestIdx = 0;

590 int BestCover = std::numeric_limits::min();

591 for (unsigned Idx : PossibleIndexes) {

593

594 if (SubRegMask == LanesLeft) {

595 BestIdx = Idx;

596 break;

597 }

598

599

600

601

602 if ((SubRegMask & ~LanesLeft).any())

603 continue;

604

605

606 const int Cover = (SubRegMask & LanesLeft).getNumLanes();

607 if (Cover > BestCover) {

608 BestCover = Cover;

609 BestIdx = Idx;

610 }

611 }

612

613 if (BestIdx == 0)

614 return false;

615

616 NeededIndexes.push_back(BestIdx);

617

619 }

620

621 return BestIdx;

622}

623

626 "This is not a subregister index");

628}

629

632 "This is not a subregister index");

634}

635

639 while (true) {

641 if (->isCopyLike())

642 return SrcReg;

643

645 if (MI->isCopy())

646 CopySrcReg = MI->getOperand(1).getReg();

647 else {

648 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");

649 CopySrcReg = MI->getOperand(2).getReg();

650 }

651

653 return CopySrcReg;

654

655 SrcReg = CopySrcReg;

656 }

657}

658

661 while (true) {

663

664 if (->isCopyLike())

665 return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();

666

668 if (MI->isCopy())

669 CopySrcReg = MI->getOperand(1).getReg();

670 else {

671 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");

672 CopySrcReg = MI->getOperand(2).getReg();

673 }

674

675

676

677 if (!CopySrcReg.isVirtual() || MRI ->hasOneNonDBGUse(CopySrcReg))

679

680 SrcReg = CopySrcReg;

681 }

682}

683

686 assert( Offset .getScalable() && "Scalable offsets are not handled");

688}

689

692 unsigned PrependFlags,

694 assert((PrependFlags &

697 "Unsupported prepend flag");

700 OffsetExpr.push_back(dwarf::DW_OP_deref);

703 OffsetExpr.push_back(dwarf::DW_OP_deref);

707}

708

709#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

715#endif

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file contains the simple types necessary to represent the attributes associated with functions a...

This file implements the BitVector class.

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

This file contains constants used for implementing Dwarf debug support.

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Promote Memory to Register

This file defines the SmallSet class.

static const TargetRegisterClass * getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg, TypeT Ty)

Definition TargetRegisterInfo.cpp:204

static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)

getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...

Definition TargetRegisterInfo.cpp:281

static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)

Definition TargetRegisterInfo.cpp:312

static const TargetRegisterClass * getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1, MCRegister Reg2, TypeT Ty)

Definition TargetRegisterInfo.cpp:232

static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

static LLVM_ABI void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)

Append Ops with operations to apply the Offset.

static LLVM_ABI DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)

Prepend DIExpr with the given opcodes and optionally turn it into a stack value.

CallingConv::ID getCallingConv() const

getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...

LiveInterval - This class represents the liveness of a register, or stack slot.

MCRegUnitRootIterator enumerates the root registers of a register unit.

bool isValid() const

Check if the iterator is at the end of the list.

unsigned getNumSubRegIndices() const

Return the number of sub-register indices understood by the target.

iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, excluding Reg.

iterator_range< MCSuperRegIterator > superregs_inclusive(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, including Reg.

unsigned getNumRegs() const

Return the number of registers this target has (useful for sizing arrays holding per register informa...

Wrapper class representing physical registers. Should be passed by value.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

constexpr unsigned id() const

bool shouldRealignStack() const

Return true if stack realignment is forced by function attributes or if the stack alignment.

bool isStackRealignable() const

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Simple wrapper around std::function<void(raw_ostream&)>.

Wrapper class representing virtual and physical registers.

unsigned virtRegIndex() const

Convert a virtual register number to a 0-based index.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr unsigned id() const

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StackOffset holds a fixed and a scalable offset in bytes.

StringRef - Represent a constant reference to a string, i.e.

LLVM_ABI std::string lower() const

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

TargetInstrInfo - Interface to description of machine instruction set.

ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF, bool Rev=false) const

Returns the preferred order for allocating registers from this register class in MF.

bool isAllocatable() const

Return true if this register class may be used to create virtual registers.

bool hasSubClass(const TargetRegisterClass *RC) const

Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

const uint32_t * getSubClassMask() const

Returns a bit vector of subclasses, including this one.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

const TargetRegisterClass *const * regclass_iterator

~TargetRegisterInfo() override

const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const

Returns the Register Class of a physical register of the given type, picking the most sub register cl...

Definition TargetRegisterInfo.cpp:260

iterator_range< regclass_iterator > regclasses() const

virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const

Region split has a high compile time cost especially for large live range.

Definition TargetRegisterInfo.cpp:65

virtual bool canRealignStack(const MachineFunction &MF) const

True if the stack can be realigned for the target.

Definition TargetRegisterInfo.cpp:510

virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const

Returns the largest legal sub-class of RC that supports the sub-register index Idx.

bool getCoveringSubRegIndexes(const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const

Try to find one or more subregister indexes to cover LaneMask.

Definition TargetRegisterInfo.cpp:549

const TargetRegisterClass * getRegClass(unsigned i) const

Returns the register class associated with the enumeration value.

unsigned composeSubRegIndices(unsigned a, unsigned b) const

Return the subregister index you get from composing two subregister indices.

const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const

Find the largest common subclass of A and B.

Definition TargetRegisterInfo.cpp:322

const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const

Returns the Register Class of a physical register of the given type, picking the most sub register cl...

Definition TargetRegisterInfo.cpp:270

void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const

Mark a register and all its aliases as reserved in the given set.

Definition TargetRegisterInfo.cpp:76

virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const

Get the scale factor of spill weight for this register class.

Definition TargetRegisterInfo.cpp:445

bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const

Return true if all bits that are set in mask mask0 are also set in mask1.

Definition TargetRegisterInfo.cpp:518

TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const

Return the size in bits of a register from class RC.

virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const

Return a mask of call-preserved registers for the given calling convention on the current function.

virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const

Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...

Definition TargetRegisterInfo.cpp:659

LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const

Return a bitmask representing the parts of a register that are covered by SubIdx.

bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const

Returns true if for every register in the set all super registers are part of the set as well.

Definition TargetRegisterInfo.cpp:82

const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const

Return the maximal subclass of the given register class that is allocatable or NULL.

Definition TargetRegisterInfo.cpp:189

virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const

Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...

Definition TargetRegisterInfo.cpp:637

const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const

Find a common super-register class if it exists.

Definition TargetRegisterInfo.cpp:352

unsigned getSubRegIdxSize(unsigned Idx) const

Get the size of the bit range covered by a sub-register index.

Definition TargetRegisterInfo.cpp:624

static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)

Debugging helper: dump register in human readable form to dbgs() stream.

Definition TargetRegisterInfo.cpp:711

virtual bool shouldRealignStack(const MachineFunction &MF) const

True if storage within the function requires the stack pointer to be aligned more than the normal cal...

Definition TargetRegisterInfo.cpp:514

TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0)

Definition TargetRegisterInfo.cpp:52

DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const

Prepends a DWARF expression for Offset to DIExpression Expr.

Definition TargetRegisterInfo.cpp:691

const TargetRegisterClass * findCommonRegClass(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const

Find a common register class that can accomodate both the source and destination operands of a copy-l...

Definition TargetRegisterInfo.cpp:413

const TargetRegisterClass * getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2, MVT VT=MVT::Other) const

Returns the common Register Class of two physical registers of the given type, picking the most sub r...

Definition TargetRegisterInfo.cpp:264

virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const

This is a wrapper around getCallPreservedMask().

Definition TargetRegisterInfo.cpp:497

unsigned getSubRegIdxOffset(unsigned Idx) const

Get the offset of the bit range covered by a sub-register index.

Definition TargetRegisterInfo.cpp:630

virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const

Return a subclass of the specified register class A so that each register in it has a sub-register of...

Definition TargetRegisterInfo.cpp:336

virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const

Gets the DWARF expression opcodes for Offset.

Definition TargetRegisterInfo.cpp:684

BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const

Returns a bitset indexed by register number indicating if a register is allocatable or not.

Definition TargetRegisterInfo.cpp:289

virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const

Get a list of 'hint' registers that the register allocator should try first when allocating a physica...

Definition TargetRegisterInfo.cpp:451

const TargetRegisterClass * getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2, LLT Ty=LLT()) const

Returns the common Register Class of two physical registers of the given type, picking the most sub r...

Definition TargetRegisterInfo.cpp:274

virtual const TargetInstrInfo * getInstrInfo() const

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

Wrapper class representing a virtual register or register unit.

constexpr bool isVirtualReg() const

constexpr MCRegUnit asMCRegUnit() const

constexpr Register asVirtualReg() const

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI void printLowerCase(StringRef String, raw_ostream &Out)

printLowerCase - Print each character as lowercase if it is uppercase.

LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

Definition TargetRegisterInfo.cpp:136

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)

Create Printable object to print register classes or register banks on a raw_ostream.

Definition TargetRegisterInfo.cpp:170

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

Definition TargetRegisterInfo.cpp:105

LLVM_ABI Printable printVRegOrUnit(VirtRegOrUnit VRegOrUnit, const TargetRegisterInfo *TRI)

Create Printable object to print virtual registers and physical registers on a raw_ostream.

Definition TargetRegisterInfo.cpp:159

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

constexpr bool any() const

unsigned getNumLanes() const

Extra information, not in MCRegisterDesc, about registers.

SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...