TargetSchedule.h Source File (original) (raw)

15#ifndef LLVM_CODEGEN_TARGETSCHEDULE_H

16#define LLVM_CODEGEN_TARGETSCHEDULE_H

20#include "llvm/Config/llvm-config.h"

25namespace llvm {

42 unsigned MicroOpFactor = 0;

45 unsigned ResourceLCM = 0;

47 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;

56 bool EnableSchedModel = true;

57 bool EnableSchedItins = true;

59public:

68 bool EnableSModel = true, bool EnableSItins = true);

97 return &InstrItins;

98 return nullptr;

99 }

100

101

102

107

108 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }

109

110

111 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }

112

113

116

119

120

123

124

126 return SchedModel.getNumProcResourceKinds();

127 }

128

129

131 return SchedModel.getProcResource(PIdx);

132 }

133

134#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

136 if (!PIdx)

137 return "MOps";

138 return SchedModel.getProcResource(PIdx)->Name;

139 }

140#endif

141

143

144

145

147

148 return STI->getWriteProcResBegin(SC);

149 }

151 return STI->getWriteProcResEnd(SC);

152 }

153

154

155

157 return ResourceFactors[ResIdx];

158 }

159

160

161

163 return MicroOpFactor;

164 }

165

166

167

169 return ResourceLCM;

170 }

171

172

174

175

176

178 return SchedModel.getProcResource(PIdx)->BufferSize;

179 }

180

181

182

183

184

185

187 unsigned DefOperIdx,

189 unsigned UseOperIdx) const;

190

191

192

193

194

195

196

197

198

199

200

201

203 bool UseDefaultDefLatency = true) const;

204 LLVM_ABI unsigned computeInstrLatency(const MCInst &Inst) const;

205 LLVM_ABI unsigned computeInstrLatency(unsigned Opcode) const;

206

207

208

209

211 unsigned DefOperIdx,

213

214

218};

219

220}

221

222#endif

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

This file defines the SmallVector class.

Itinerary data supplied by a subtarget to be used by a target.

Instances of this class represent a single low-level machine instruction.

Representation of each machine instruction.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

const char * getResourceName(unsigned PIdx) const

Definition TargetSchedule.h:135

const MCSchedModel * getMCSchedModel() const

Definition TargetSchedule.h:87

const TargetInstrInfo * getInstrInfo() const

TargetInstrInfo getter.

Definition TargetSchedule.h:78

LLVM_ABI bool mustEndGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const

Return true if current group must end.

unsigned getIssueWidth() const

Maximum number of micro-ops that may be scheduled per cycle.

Definition TargetSchedule.h:111

unsigned getMicroOpFactor() const

Multiply number of micro-ops by this factor to normalize it relative to other resources.

Definition TargetSchedule.h:162

ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const

Definition TargetSchedule.h:150

int getResourceBufferSize(unsigned PIdx) const

Number of resource units that may be buffered for OOO execution.

Definition TargetSchedule.h:177

LLVM_ABI bool hasInstrSchedModel() const

Return true if this machine model includes an instruction-level scheduling model.

LLVM_ABI unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const

Output dependency latency of a pair of defs of the same register.

LLVM_ABI bool mustBeginGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const

Return true if new group must begin.

const MCWriteProcResEntry * ProcResIter

Definition TargetSchedule.h:142

unsigned getLatencyFactor() const

Multiply cycle count by this factor to normalize it relative to other resources.

Definition TargetSchedule.h:168

TargetSchedModel()

Definition TargetSchedule.h:60

unsigned getResourceFactor(unsigned ResIdx) const

Multiply the number of units consumed for a resource by this factor to normalize it relative to other...

Definition TargetSchedule.h:156

LLVM_ABI void init(const TargetSubtargetInfo *TSInfo, bool EnableSModel=true, bool EnableSItins=true)

Initialize the machine model for instruction scheduling.

LLVM_ABI const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const

Return the MCSchedClassDesc for this instruction.

LLVM_ABI unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const

Compute operand latency based on the available machine model.

bool hasInstrSchedModelOrItineraries() const

Return true if this machine model includes an instruction-level scheduling model or cycle-to-cycle it...

Definition TargetSchedule.h:103

unsigned getMicroOpBufferSize() const

Number of micro-ops that may be buffered for OOO execution.

Definition TargetSchedule.h:173

LLVM_ABI double computeReciprocalThroughput(const MachineInstr *MI) const

Compute the reciprocal throughput of the given instruction.

LLVM_ABI unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const

Return the number of issue slots required for this MI.

const MCProcResourceDesc * getProcResource(unsigned PIdx) const

Get a processor resource by ID for convenience.

Definition TargetSchedule.h:130

unsigned getNumProcResourceKinds() const

Get the number of kinds of resources for this target.

Definition TargetSchedule.h:125

unsigned getProcessorID() const

Identify the processor corresponding to the current subtarget.

Definition TargetSchedule.h:108

const InstrItineraryData * getInstrItineraries() const

Definition TargetSchedule.h:95

const TargetSubtargetInfo * getSubtargetInfo() const

TargetSubtargetInfo getter.

Definition TargetSchedule.h:75

LLVM_ABI bool enableIntervals() const

ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const

Definition TargetSchedule.h:146

LLVM_ABI bool hasInstrItineraries() const

Return true if this machine model includes cycle-to-cycle itinerary data.

TargetSubtargetInfo - Generic base class for all target subtargets.

This is an optimization pass for GlobalISel generic memory operations.

@ Default

The result values are uniform if and only if all operands are uniform.

Define a kind of processor resource that will be modeled by the scheduler.

Summarize the scheduling resources required for an instruction of a particular scheduling class.

Machine model for scheduling, bundling, and heuristics.

Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...