LLVM: lib/Target/VE/AsmParser/VEAsmParser.cpp Source File (original) (raw)
1
2
3
4
5
6
7
8
12#include "VE.h"
30#include
31
32using namespace llvm;
33
34#define DEBUG_TYPE "ve-asmparser"
35
36namespace {
37
38class VEOperand;
39
42
43
44
45
46#define GET_ASSEMBLER_HEADER
47#include "VEGenAsmMatcher.inc"
48
49
50
51
52 bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
55 bool MatchingInlineAsm) override;
59 SMLoc &EndLoc) override;
63
65 unsigned Kind) override;
66
67
74 ParseStatus parseVEAsmOperand(std::unique_ptr &Operand);
75
76
78 bool parseExpression(const MCExpr *&EVal);
79
80
83
84 bool parseLiteralValues(unsigned Size, SMLoc L);
85
86public:
90
91 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
92 }
93};
94
95}
96
98 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
99 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
100 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
101 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
102 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
103 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
104 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
105 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
106 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
107 VE::SW63};
108
110 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
111 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
112 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
113 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
114 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
115 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
116 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
117 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
118 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
119 VE::SF63};
120
122 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
123 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
124 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
125 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
126
128 VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7};
129
131 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
132 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
133 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
134 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
135 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
136 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
137 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
138 VE::PMC12, VE::PMC13, VE::PMC14};
139
140namespace {
141
142
143
145private:
146 enum KindTy {
147 k_Token,
148 k_Register,
149 k_Immediate,
150
151 k_MemoryRegRegImm,
152 k_MemoryRegImmImm,
153 k_MemoryZeroRegImm,
154 k_MemoryZeroImmImm,
155
156 k_MemoryRegImm,
157 k_MemoryZeroImm,
158
159 k_CCOp,
160 k_RDOp,
161 k_MImmOp,
162 } Kind;
163
164 SMLoc StartLoc, EndLoc;
165
166 struct Token {
167 const char *Data;
168 unsigned Length;
169 };
170
171 struct RegOp {
172 MCRegister Reg;
173 };
174
175 struct ImmOp {
176 const MCExpr *Val;
177 };
178
179 struct MemOp {
180 MCRegister Base;
181 MCRegister IndexReg;
182 const MCExpr *Index;
183 const MCExpr *Offset;
184 };
185
186 struct CCOp {
187 unsigned CCVal;
188 };
189
190 struct RDOp {
191 unsigned RDVal;
192 };
193
194 struct MImmOp {
195 const MCExpr *Val;
196 bool M0Flag;
197 };
198
199 union {
200 struct Token Tok;
201 struct RegOp Reg;
202 struct ImmOp Imm;
203 struct MemOp Mem;
204 struct CCOp CC;
205 struct RDOp RD;
206 struct MImmOp MImm;
207 };
208
209public:
210 VEOperand(KindTy K) : Kind(K) {}
211
212 bool isToken() const override { return Kind == k_Token; }
213 bool isReg() const override { return Kind == k_Register; }
214 bool isImm() const override { return Kind == k_Immediate; }
215 bool isMem() const override {
216 return isMEMrri() || isMEMrii() || isMEMzri() || isMEMzii() || isMEMri() ||
217 isMEMzi();
218 }
219 bool isMEMrri() const { return Kind == k_MemoryRegRegImm; }
220 bool isMEMrii() const { return Kind == k_MemoryRegImmImm; }
221 bool isMEMzri() const { return Kind == k_MemoryZeroRegImm; }
222 bool isMEMzii() const { return Kind == k_MemoryZeroImmImm; }
223 bool isMEMri() const { return Kind == k_MemoryRegImm; }
224 bool isMEMzi() const { return Kind == k_MemoryZeroImm; }
225 bool isCCOp() const { return Kind == k_CCOp; }
226 bool isRDOp() const { return Kind == k_RDOp; }
228 if (!isImm())
229 return false;
230
231
233 int64_t Value = ConstExpr->getValue();
234 return Value == 0;
235 }
236 return false;
237 }
238 bool isUImm0to2() {
239 if (!isImm())
240 return false;
241
242
244 int64_t Value = ConstExpr->getValue();
246 }
247 return false;
248 }
249 bool isUImm1() {
250 if (!isImm())
251 return false;
252
253
255 int64_t Value = ConstExpr->getValue();
257 }
258 return false;
259 }
260 bool isUImm2() {
261 if (!isImm())
262 return false;
263
264
266 int64_t Value = ConstExpr->getValue();
268 }
269 return false;
270 }
271 bool isUImm3() {
272 if (!isImm())
273 return false;
274
275
277 int64_t Value = ConstExpr->getValue();
279 }
280 return false;
281 }
282 bool isUImm4() {
283 if (!isImm())
284 return false;
285
286
288 int64_t Value = ConstExpr->getValue();
290 }
291 return false;
292 }
293 bool isUImm6() {
294 if (!isImm())
295 return false;
296
297
299 int64_t Value = ConstExpr->getValue();
301 }
302 return false;
303 }
304 bool isUImm7() {
305 if (!isImm())
306 return false;
307
308
310 int64_t Value = ConstExpr->getValue();
312 }
313 return false;
314 }
315 bool isSImm7() {
316 if (!isImm())
317 return false;
318
319
321 int64_t Value = ConstExpr->getValue();
323 }
324 return false;
325 }
326 bool isMImm() const {
327 if (Kind != k_MImmOp)
328 return false;
329
330
332 int64_t Value = ConstExpr->getValue();
334 }
335 return false;
336 }
337
339 assert(Kind == k_Token && "Invalid access!");
340 return StringRef(Tok.Data, Tok.Length);
341 }
342
343 MCRegister getReg() const override {
344 assert((Kind == k_Register) && "Invalid access!");
345 return Reg.Reg;
346 }
347
348 const MCExpr *getImm() const {
349 assert((Kind == k_Immediate) && "Invalid access!");
350 return Imm.Val;
351 }
352
353 MCRegister getMemBase() const {
354 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
355 Kind == k_MemoryRegImm) &&
356 "Invalid access!");
357 return Mem.Base;
358 }
359
360 MCRegister getMemIndexReg() const {
361 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryZeroRegImm) &&
362 "Invalid access!");
363 return Mem.IndexReg;
364 }
365
366 const MCExpr *getMemIndex() const {
367 assert((Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm) &&
368 "Invalid access!");
369 return Mem.Index;
370 }
371
372 const MCExpr *getMemOffset() const {
373 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
374 Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ||
375 Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm) &&
376 "Invalid access!");
377 return Mem.Offset;
378 }
379
380 void setMemOffset(const MCExpr *off) {
381 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
382 Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ||
383 Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm) &&
384 "Invalid access!");
385 Mem.Offset = off;
386 }
387
388 unsigned getCCVal() const {
389 assert((Kind == k_CCOp) && "Invalid access!");
390 return CC.CCVal;
391 }
392
393 unsigned getRDVal() const {
394 assert((Kind == k_RDOp) && "Invalid access!");
395 return RD.RDVal;
396 }
397
398 const MCExpr *getMImmVal() const {
399 assert((Kind == k_MImmOp) && "Invalid access!");
400 return MImm.Val;
401 }
402 bool getM0Flag() const {
403 assert((Kind == k_MImmOp) && "Invalid access!");
404 return MImm.M0Flag;
405 }
406
407
408 SMLoc getStartLoc() const override { return StartLoc; }
409
410 SMLoc getEndLoc() const override { return EndLoc; }
411
412 void print(raw_ostream &OS, const MCAsmInfo &MAI) const override {
413 switch (Kind) {
414 case k_Token:
415 OS << "Token: " << getToken() << "\n";
416 break;
417 case k_Register:
418 OS << "Reg: #" << getReg().id() << "\n";
419 break;
420 case k_Immediate:
421 OS << "Imm: " << getImm() << "\n";
422 break;
423 case k_MemoryRegRegImm:
424 assert(getMemOffset() != nullptr);
425 OS << "Mem: #" << getMemBase().id() << "+#" << getMemIndexReg().id()
426 << "+";
427 MAI.printExpr(OS, *getMemOffset());
428 OS << "\n";
429 break;
430 case k_MemoryRegImmImm:
431 assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
432 OS << "Mem: #" << getMemBase().id() << "+";
433 MAI.printExpr(OS, *getMemIndex());
434 OS << "+";
435 MAI.printExpr(OS, *getMemOffset());
436 OS << "\n";
437 break;
438 case k_MemoryZeroRegImm:
439 assert(getMemOffset() != nullptr);
440 OS << "Mem: 0+#" << getMemIndexReg().id() << "+";
441 MAI.printExpr(OS, *getMemOffset());
442 OS << "\n";
443 break;
444 case k_MemoryZeroImmImm:
445 assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
446 OS << "Mem: 0+";
447 MAI.printExpr(OS, *getMemIndex());
448 OS << "+";
449 MAI.printExpr(OS, *getMemOffset());
450 OS << "\n";
451 break;
452 case k_MemoryRegImm:
453 assert(getMemOffset() != nullptr);
454 OS << "Mem: #" << getMemBase().id() << "+";
455 MAI.printExpr(OS, *getMemOffset());
456 OS << "\n";
457 break;
458 case k_MemoryZeroImm:
459 assert(getMemOffset() != nullptr);
460 OS << "Mem: 0+";
461 MAI.printExpr(OS, *getMemOffset());
462 OS << "\n";
463 break;
464 case k_CCOp:
465 OS << "CCOp: " << getCCVal() << "\n";
466 break;
467 case k_RDOp:
468 OS << "RDOp: " << getRDVal() << "\n";
469 break;
470 case k_MImmOp:
471 OS << "MImm: (" << getMImmVal() << (getM0Flag() ? ")0" : ")1") << "\n";
472 break;
473 }
474 }
475
476 void addRegOperands(MCInst &Inst, unsigned N) const {
477 assert(N == 1 && "Invalid number of operands!");
479 }
480
481 void addImmOperands(MCInst &Inst, unsigned N) const {
482 assert(N == 1 && "Invalid number of operands!");
483 const MCExpr *Expr = getImm();
484 addExpr(Inst, Expr);
485 }
486
487 void addZeroOperands(MCInst &Inst, unsigned N) const {
488 addImmOperands(Inst, N);
489 }
490
491 void addUImm0to2Operands(MCInst &Inst, unsigned N) const {
492 addImmOperands(Inst, N);
493 }
494
495 void addUImm1Operands(MCInst &Inst, unsigned N) const {
496 addImmOperands(Inst, N);
497 }
498
499 void addUImm2Operands(MCInst &Inst, unsigned N) const {
500 addImmOperands(Inst, N);
501 }
502
503 void addUImm3Operands(MCInst &Inst, unsigned N) const {
504 addImmOperands(Inst, N);
505 }
506
507 void addUImm4Operands(MCInst &Inst, unsigned N) const {
508 addImmOperands(Inst, N);
509 }
510
511 void addUImm6Operands(MCInst &Inst, unsigned N) const {
512 addImmOperands(Inst, N);
513 }
514
515 void addUImm7Operands(MCInst &Inst, unsigned N) const {
516 addImmOperands(Inst, N);
517 }
518
519 void addSImm7Operands(MCInst &Inst, unsigned N) const {
520 addImmOperands(Inst, N);
521 }
522
523 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
524
525 if (!Expr)
529 else
531 }
532
533 void addMEMrriOperands(MCInst &Inst, unsigned N) const {
534 assert(N == 3 && "Invalid number of operands!");
535
538 addExpr(Inst, getMemOffset());
539 }
540
541 void addMEMriiOperands(MCInst &Inst, unsigned N) const {
542 assert(N == 3 && "Invalid number of operands!");
543
545 addExpr(Inst, getMemIndex());
546 addExpr(Inst, getMemOffset());
547 }
548
549 void addMEMzriOperands(MCInst &Inst, unsigned N) const {
550 assert(N == 3 && "Invalid number of operands!");
551
554 addExpr(Inst, getMemOffset());
555 }
556
557 void addMEMziiOperands(MCInst &Inst, unsigned N) const {
558 assert(N == 3 && "Invalid number of operands!");
559
561 addExpr(Inst, getMemIndex());
562 addExpr(Inst, getMemOffset());
563 }
564
565 void addMEMriOperands(MCInst &Inst, unsigned N) const {
566 assert(N == 2 && "Invalid number of operands!");
567
569 addExpr(Inst, getMemOffset());
570 }
571
572 void addMEMziOperands(MCInst &Inst, unsigned N) const {
573 assert(N == 2 && "Invalid number of operands!");
574
576 addExpr(Inst, getMemOffset());
577 }
578
579 void addCCOpOperands(MCInst &Inst, unsigned N) const {
580 assert(N == 1 && "Invalid number of operands!");
581
583 }
584
585 void addRDOpOperands(MCInst &Inst, unsigned N) const {
586 assert(N == 1 && "Invalid number of operands!");
587
589 }
590
591 void addMImmOperands(MCInst &Inst, unsigned N) const {
592 assert(N == 1 && "Invalid number of operands!");
594 assert(ConstExpr && "Null operands!");
595 int64_t Value = ConstExpr->getValue();
596 if (getM0Flag())
599 }
600
601 static std::unique_ptr CreateToken(StringRef Str, SMLoc S) {
602 auto Op = std::make_unique(k_Token);
603 Op->Tok.Data = Str.data();
604 Op->Tok.Length = Str.size();
605 Op->StartLoc = S;
606 Op->EndLoc = S;
607 return Op;
608 }
609
610 static std::unique_ptr CreateReg(MCRegister Reg, SMLoc S,
611 SMLoc E) {
612 auto Op = std::make_unique(k_Register);
614 Op->StartLoc = S;
616 return Op;
617 }
618
619 static std::unique_ptr CreateImm(const MCExpr *Val, SMLoc S,
620 SMLoc E) {
621 auto Op = std::make_unique(k_Immediate);
622 Op->Imm.Val = Val;
623 Op->StartLoc = S;
625 return Op;
626 }
627
628 static std::unique_ptr CreateCCOp(unsigned CCVal, SMLoc S,
629 SMLoc E) {
630 auto Op = std::make_unique(k_CCOp);
631 Op->CC.CCVal = CCVal;
632 Op->StartLoc = S;
634 return Op;
635 }
636
637 static std::unique_ptr CreateRDOp(unsigned RDVal, SMLoc S,
638 SMLoc E) {
639 auto Op = std::make_unique(k_RDOp);
640 Op->RD.RDVal = RDVal;
641 Op->StartLoc = S;
643 return Op;
644 }
645
646 static std::unique_ptr CreateMImm(const MCExpr *Val, bool Flag,
647 SMLoc S, SMLoc E) {
648 auto Op = std::make_unique(k_MImmOp);
649 Op->MImm.Val = Val;
651 Op->StartLoc = S;
653 return Op;
654 }
655
656 static bool MorphToI32Reg(VEOperand &Op) {
657 MCRegister Reg = Op.getReg();
658 unsigned regIdx = Reg - VE::SX0;
659 if (regIdx > 63)
660 return false;
662 return true;
663 }
664
665 static bool MorphToF32Reg(VEOperand &Op) {
666 MCRegister Reg = Op.getReg();
667 unsigned regIdx = Reg - VE::SX0;
668 if (regIdx > 63)
669 return false;
671 return true;
672 }
673
674 static bool MorphToF128Reg(VEOperand &Op) {
675 MCRegister Reg = Op.getReg();
676 unsigned regIdx = Reg - VE::SX0;
677 if (regIdx % 2 || regIdx > 63)
678 return false;
680 return true;
681 }
682
683 static bool MorphToVM512Reg(VEOperand &Op) {
684 MCRegister Reg = Op.getReg();
685 unsigned regIdx = Reg - VE::VM0;
686 if (regIdx % 2 || regIdx > 15)
687 return false;
689 return true;
690 }
691
692 static bool MorphToMISCReg(VEOperand &Op) {
694 if (!ConstExpr)
695 return false;
696 unsigned regIdx = ConstExpr->getValue();
697 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
698 return false;
699 Op.Kind = k_Register;
701 return true;
702 }
703
704 static std::unique_ptr
705 MorphToMEMri(MCRegister Base, std::unique_ptr Op) {
706 const MCExpr *Imm = Op->getImm();
707 Op->Kind = k_MemoryRegImm;
709 Op->Mem.IndexReg = MCRegister();
710 Op->Mem.Index = nullptr;
712 return Op;
713 }
714
715 static std::unique_ptr
716 MorphToMEMzi(std::unique_ptr Op) {
717 const MCExpr *Imm = Op->getImm();
718 Op->Kind = k_MemoryZeroImm;
719 Op->Mem.Base = MCRegister();
720 Op->Mem.IndexReg = MCRegister();
721 Op->Mem.Index = nullptr;
723 return Op;
724 }
725
726 static std::unique_ptr
727 MorphToMEMrri(MCRegister Base, MCRegister Index,
728 std::unique_ptr Op) {
729 const MCExpr *Imm = Op->getImm();
730 Op->Kind = k_MemoryRegRegImm;
733 Op->Mem.Index = nullptr;
735 return Op;
736 }
737
738 static std::unique_ptr
739 MorphToMEMrii(MCRegister Base, const MCExpr *Index,
740 std::unique_ptr Op) {
741 const MCExpr *Imm = Op->getImm();
742 Op->Kind = k_MemoryRegImmImm;
744 Op->Mem.IndexReg = MCRegister();
747 return Op;
748 }
749
750 static std::unique_ptr
751 MorphToMEMzri(MCRegister Index, std::unique_ptr Op) {
752 const MCExpr *Imm = Op->getImm();
753 Op->Kind = k_MemoryZeroRegImm;
754 Op->Mem.Base = MCRegister();
756 Op->Mem.Index = nullptr;
758 return Op;
759 }
760
761 static std::unique_ptr
762 MorphToMEMzii(const MCExpr *Index, std::unique_ptr Op) {
763 const MCExpr *Imm = Op->getImm();
764 Op->Kind = k_MemoryZeroImmImm;
765 Op->Mem.Base = MCRegister();
766 Op->Mem.IndexReg = MCRegister();
769 return Op;
770 }
771};
772
773}
774
775bool VEAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
778 bool MatchingInlineAsm) {
779 MCInst Inst;
780 unsigned MatchResult =
781 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
782 switch (MatchResult) {
783 case Match_Success:
786 return false;
787
788 case Match_MissingFeature:
789 return Error(IDLoc,
790 "instruction requires a CPU feature not currently enabled");
791
792 case Match_InvalidOperand: {
793 SMLoc ErrorLoc = IDLoc;
794 if (ErrorInfo != ~0ULL) {
795 if (ErrorInfo >= Operands.size())
796 return Error(IDLoc, "too few operands for instruction");
797
798 ErrorLoc = ((VEOperand &)*Operands[ErrorInfo]).getStartLoc();
799 if (ErrorLoc == SMLoc())
800 ErrorLoc = IDLoc;
801 }
802
803 return Error(ErrorLoc, "invalid operand for instruction");
804 }
805 case Match_MnemonicFail:
806 return Error(IDLoc, "invalid instruction mnemonic");
807 }
809}
810
811bool VEAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
812 SMLoc &EndLoc) {
813 if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
814 return Error(StartLoc, "invalid register name");
815 return false;
816}
817
818
819
820MCRegister VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
822
823 MCRegister RegNum = matchFn(Name);
824
825
826
827 if (!RegNum) {
828 RegNum = matchFn(Name.lower());
829 }
830
831 return RegNum;
832}
833
834
835
837
838
839
841
845 StartLoc = Tok.getLoc();
847 Reg = VE::NoRegister;
850 Parser.Lex();
851
853 if (Reg == VE::NoRegister)
855
856 if (Reg != VE::NoRegister) {
857 Parser.Lex();
859 }
860
861 getLexer().UnLex(Tok);
863}
864
866 bool IntegerCC, bool OmitCC, SMLoc NameLoc,
868
869
873
874
877 StringRef SuffixStr = Name.substr(Suffix);
878
879 Name = Name.slice(0, Prefix);
880 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
881
884 Operands->push_back(VEOperand::CreateCCOp(CondCode, CondLoc, SuffixLoc));
885
886 if (!SuffixStr.empty())
887 Operands->push_back(VEOperand::CreateToken(SuffixStr, SuffixLoc));
888 } else {
889 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
890 }
891 return Name;
892}
893
896
897
898 StringRef RD = Name.substr(Prefix);
900
902 Name = Name.slice(0, Prefix);
903
904 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
905 SMLoc SuffixLoc =
909
912 } else {
913 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
914 }
915 return Name;
916}
917
918
919
920StringRef VEAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,
922
923 StringRef Mnemonic = Name;
924
925 if (Name[0] == 'b') {
926
927 size_t Start = 1;
928 size_t Next = Name.find('.');
929
930 if (Name.size() > 1 && Name[1] == 'r')
932
933 bool ICC = true;
934 if (Next + 1 < Name.size() &&
935 (Name[Next + 1] == 'd' || Name[Next + 1] == 's'))
936 ICC = false;
937 Mnemonic = parseCC(Name, Start, Next, ICC, true, NameLoc, Operands);
938 } else if (Name.starts_with("cmov.l.") || Name.starts_with("cmov.w.") ||
939 Name.starts_with("cmov.d.") || Name.starts_with("cmov.s.")) {
940 bool ICC = Name[5] == 'l' || Name[5] == 'w';
941 Mnemonic = parseCC(Name, 7, Name.size(), ICC, false, NameLoc, Operands);
942 } else if (Name.starts_with("cvt.w.d.sx") || Name.starts_with("cvt.w.d.zx") ||
943 Name.starts_with("cvt.w.s.sx") || Name.starts_with("cvt.w.s.zx")) {
944 Mnemonic = parseRD(Name, 10, NameLoc, Operands);
945 } else if (Name.starts_with("cvt.l.d")) {
946 Mnemonic = parseRD(Name, 7, NameLoc, Operands);
947 } else if (Name.starts_with("vcvt.w.d.sx") ||
948 Name.starts_with("vcvt.w.d.zx") ||
949 Name.starts_with("vcvt.w.s.sx") ||
950 Name.starts_with("vcvt.w.s.zx")) {
951 Mnemonic = parseRD(Name, 11, NameLoc, Operands);
952 } else if (Name.starts_with("vcvt.l.d")) {
953 Mnemonic = parseRD(Name, 8, NameLoc, Operands);
954 } else if (Name.starts_with("pvcvt.w.s.lo") ||
955 Name.starts_with("pvcvt.w.s.up")) {
956 Mnemonic = parseRD(Name, 12, NameLoc, Operands);
957 } else if (Name.starts_with("pvcvt.w.s")) {
958 Mnemonic = parseRD(Name, 9, NameLoc, Operands);
959 } else if (Name.starts_with("vfmk.l.") || Name.starts_with("vfmk.w.") ||
960 Name.starts_with("vfmk.d.") || Name.starts_with("vfmk.s.")) {
961 bool ICC = Name[5] == 'l' || Name[5] == 'w' ? true : false;
962 Mnemonic = parseCC(Name, 7, Name.size(), ICC, true, NameLoc, Operands);
963 } else if (Name.starts_with("pvfmk.w.lo.") ||
964 Name.starts_with("pvfmk.w.up.") ||
965 Name.starts_with("pvfmk.s.lo.") ||
966 Name.starts_with("pvfmk.s.up.")) {
967 bool ICC = Name[6] == 'l' || Name[6] == 'w' ? true : false;
968 Mnemonic = parseCC(Name, 11, Name.size(), ICC, true, NameLoc, Operands);
969 } else {
970 Operands->push_back(VEOperand::CreateToken(Mnemonic, NameLoc));
971 }
972
973 return Mnemonic;
974}
975
978 unsigned VariantID);
979
982
983
985
986
987
988
989 StringRef Mnemonic = splitMnemonic(Name, NameLoc, &Operands);
990
992
993 if (!parseOperand(Operands, Mnemonic).isSuccess()) {
994 SMLoc Loc = getLexer().getLoc();
995 return Error(Loc, "unexpected token");
996 }
997
999 Parser.Lex();
1000
1001 if (!parseOperand(Operands, Mnemonic).isSuccess()) {
1002 SMLoc Loc = getLexer().getLoc();
1003 return Error(Loc, "unexpected token");
1004 }
1005 }
1006 }
1008 SMLoc Loc = getLexer().getLoc();
1009 return Error(Loc, "unexpected token");
1010 }
1011 Parser.Lex();
1012 return false;
1013}
1014
1015ParseStatus VEAsmParser::parseDirective(AsmToken DirectiveID) {
1017
1018
1019
1020
1021
1022
1023 if (IDVal == ".word")
1024 return parseLiteralValues(4, DirectiveID.getLoc());
1025
1026
1027 if (IDVal == ".long")
1028 return parseLiteralValues(8, DirectiveID.getLoc());
1029
1030
1031 if (IDVal == ".llong")
1032 return parseLiteralValues(8, DirectiveID.getLoc());
1033
1034
1036}
1037
1038
1039
1040
1041
1042bool VEAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
1043 auto parseOne = [&]() -> bool {
1044 const MCExpr *Value;
1045 if (getParser().parseExpression(Value))
1046 return true;
1047 getParser().getStreamer().emitValue(Value, Size, L);
1048 return false;
1049 };
1050 return (parseMany(parseOne));
1051}
1052
1053
1054
1055
1056
1057
1058
1059const MCExpr *VEAsmParser::extractSpecifier(const MCExpr *E,
1061 MCContext &Context = getParser().getContext();
1063
1064 switch (E->getKind()) {
1067 return nullptr;
1070
1073
1076
1078 break;
1081 break;
1084 break;
1087 break;
1090 break;
1093 break;
1096 break;
1099 break;
1102 break;
1105 break;
1108 break;
1111 break;
1114 break;
1117 break;
1120 break;
1121 default:
1122 return nullptr;
1123 }
1124
1126 }
1127
1130 const MCExpr *Sub = extractSpecifier(UE->getSubExpr(), Variant);
1131 if ()
1132 return nullptr;
1134 }
1135
1139 const MCExpr *LHS = extractSpecifier(BE->getLHS(), LHSVariant);
1140 const MCExpr *RHS = extractSpecifier(BE->getRHS(), RHSVariant);
1141
1143 return nullptr;
1144
1145 if ()
1147 if ()
1149
1154 else if (LHSVariant == RHSVariant)
1156 else
1157 return nullptr;
1158
1160 }
1161 }
1162
1164}
1165
1166
1167
1168bool VEAsmParser::parseExpression(const MCExpr *&EVal) {
1169
1170 if (getParser().parseExpression(EVal))
1171 return true;
1172
1173
1175 const MCExpr *E = extractSpecifier(EVal, Specifier);
1176 if (E)
1178
1179 return false;
1180}
1181
1182ParseStatus VEAsmParser::parseMEMOperand(OperandVector &Operands) {
1184 const AsmToken &Tok = Parser.getTok();
1185 SMLoc S = Tok.getLoc();
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196 std::unique_ptr Offset;
1197 switch (getLexer().getKind()) {
1198 default:
1200
1205 const MCExpr *EVal;
1206 if (!parseExpression(EVal))
1207 Offset = VEOperand::CreateImm(EVal, S, E);
1208 else
1210 break;
1211 }
1212
1214
1217 break;
1218 }
1219
1220 switch (getLexer().getKind()) {
1221 default:
1223
1225 Operands.push_back(VEOperand::MorphToMEMzii(
1228
1230 Parser.Lex();
1231 break;
1232 }
1233
1234 const MCExpr *IndexValue = nullptr;
1235 MCRegister IndexReg;
1236
1237 switch (getLexer().getKind()) {
1238 default:
1239 if (parseRegister(IndexReg, S, E))
1241 break;
1242
1246 if (getParser().parseExpression(IndexValue, E))
1248 break;
1249
1251
1253 break;
1254 }
1255
1256 switch (getLexer().getKind()) {
1257 default:
1259
1261 Parser.Lex();
1263 IndexValue ? VEOperand::MorphToMEMzii(IndexValue, std::move(Offset))
1264 : VEOperand::MorphToMEMzri(IndexReg, std::move(Offset)));
1266
1268 Parser.Lex();
1269 break;
1270 }
1271
1273 if (parseRegister(BaseReg, S, E))
1275
1278
1279 Parser.Lex();
1281 IndexValue
1282 ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset))
1283 : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset)));
1284
1286}
1287
1288ParseStatus VEAsmParser::parseMEMAsOperand(OperandVector &Operands) {
1290 const AsmToken &Tok = Parser.getTok();
1291 SMLoc S = Tok.getLoc();
1293
1294
1295
1296
1297
1298
1299
1300
1301
1303 std::unique_ptr Offset;
1304 switch (getLexer().getKind()) {
1305 default:
1307
1312 const MCExpr *EVal;
1313 if (!parseExpression(EVal))
1314 Offset = VEOperand::CreateImm(EVal, S, E);
1315 else
1317 break;
1318 }
1319
1321 if (parseRegister(BaseReg, S, E))
1325 break;
1326
1328
1331 break;
1332 }
1333
1334 switch (getLexer().getKind()) {
1335 default:
1337
1340 Operands.push_back(BaseReg != VE::NoRegister
1341 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset))
1342 : VEOperand::MorphToMEMzi(std::move(Offset)));
1344
1346 if (BaseReg != VE::NoRegister)
1348 Parser.Lex();
1349 break;
1350 }
1351
1352 switch (getLexer().getKind()) {
1353 default:
1354 if (parseRegister(BaseReg, S, E))
1356 break;
1357
1359 Parser.Lex();
1360 if (parseRegister(BaseReg, S, E))
1362 break;
1363
1365 break;
1366 }
1367
1370
1371 Parser.Lex();
1372 Operands.push_back(BaseReg != VE::NoRegister
1373 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset))
1374 : VEOperand::MorphToMEMzi(std::move(Offset)));
1375
1377}
1378
1379ParseStatus VEAsmParser::parseMImmOperand(OperandVector &Operands) {
1381
1382
1383 const AsmToken Tok1 = Parser.getTok();
1386
1387 Parser.Lex();
1388
1389 const AsmToken Tok2 = Parser.getTok();
1390 SMLoc E;
1391 const MCExpr *EVal;
1393 getLexer().UnLex(Tok1);
1395 }
1396
1397 const AsmToken Tok3 = Parser.getTok();
1399 getLexer().UnLex(Tok2);
1400 getLexer().UnLex(Tok1);
1402 }
1403 Parser.Lex();
1404
1405 const AsmToken &Tok4 = Parser.getTok();
1406 StringRef Suffix = Tok4.getString();
1407 if (Suffix != "1" && Suffix != "0") {
1408 getLexer().UnLex(Tok3);
1409 getLexer().UnLex(Tok2);
1410 getLexer().UnLex(Tok1);
1412 }
1413 Parser.Lex();
1416 VEOperand::CreateMImm(EVal, Suffix == "0", Tok1.getLoc(), EndLoc));
1418}
1419
1420ParseStatus VEAsmParser::parseOperand(OperandVector &Operands,
1421 StringRef Mnemonic) {
1423 ParseStatus Res = MatchOperandParserImpl(Operands, Mnemonic);
1424
1425
1426
1427
1429 return Res;
1430
1431 switch (getLexer().getKind()) {
1433
1434 const AsmToken Tok1 = Parser.getTok();
1435 Parser.Lex();
1436
1437 MCRegister Reg1;
1438 SMLoc S1, E1;
1439 if (!tryParseRegister(Reg1, S1, E1).isSuccess()) {
1440 getLexer().UnLex(Tok1);
1442 }
1443
1446 Parser.Lex();
1447
1448 MCRegister Reg2;
1449 SMLoc S2, E2;
1450 if (!tryParseRegister(Reg2, S2, E2).isSuccess())
1452
1455
1457 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1));
1458 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2));
1461 Parser.Lex();
1462 break;
1463 }
1464 default: {
1465 std::unique_ptr Op;
1466 Res = parseVEAsmOperand(Op);
1469
1470
1472
1474 break;
1475
1476
1477 std::unique_ptr Op1 = VEOperand::CreateToken(
1479 Parser.Lex();
1480
1481 std::unique_ptr Op2;
1482 Res = parseVEAsmOperand(Op2);
1485
1488
1489 Operands.push_back(std::move(Op1));
1490 Operands.push_back(std::move(Op2));
1493 Parser.Lex();
1494 break;
1495 }
1496 }
1497
1499}
1500
1501ParseStatus VEAsmParser::parseVEAsmOperand(std::unique_ptr &Op) {
1505 const MCExpr *EVal;
1506
1507 Op = nullptr;
1508 switch (getLexer().getKind()) {
1509 default:
1510 break;
1511
1513 MCRegister Reg;
1514 if (tryParseRegister(Reg, S, E).isSuccess())
1515 Op = VEOperand::CreateReg(Reg, S, E);
1516 break;
1517 }
1522 if (!parseExpression(EVal))
1523 Op = VEOperand::CreateImm(EVal, S, E);
1524 break;
1525 }
1527}
1528
1529
1533
1534#define GET_REGISTER_MATCHER
1535#define GET_MATCHER_IMPLEMENTATION
1536#include "VEGenAsmMatcher.inc"
1537
1538unsigned VEAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1539 unsigned Kind) {
1540 VEOperand &Op = (VEOperand &)GOp;
1541
1542
1543
1544
1545 switch (Kind) {
1546 default:
1547 break;
1548 case MCK_F32:
1549 if (Op.isReg() && VEOperand::MorphToF32Reg(Op))
1551 break;
1552 case MCK_I32:
1553 if (Op.isReg() && VEOperand::MorphToI32Reg(Op))
1555 break;
1556 case MCK_F128:
1557 if (Op.isReg() && VEOperand::MorphToF128Reg(Op))
1559 break;
1560 case MCK_VM512:
1561 if (Op.isReg() && VEOperand::MorphToVM512Reg(Op))
1563 break;
1564 case MCK_MISC:
1565 if (Op.isImm() && VEOperand::MorphToMISCReg(Op))
1567 break;
1568 }
1569 return Match_InvalidOperand;
1570}
static MCRegister MatchRegisterName(StringRef Name)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
static MCRegister MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
const SmallVectorImpl< MachineOperand > & Cond
This file defines the SmallVector class.
static const MCPhysReg MISCRegs[31]
Definition VEAsmParser.cpp:130
static const MCPhysReg F128Regs[32]
Definition VEAsmParser.cpp:121
static const MCPhysReg F32Regs[64]
Definition VEAsmParser.cpp:109
static StringRef parseCC(StringRef Name, unsigned Prefix, unsigned Suffix, bool IntegerCC, bool OmitCC, SMLoc NameLoc, OperandVector *Operands)
Definition VEAsmParser.cpp:865
static const MCPhysReg VM512Regs[8]
Definition VEAsmParser.cpp:127
static const MCPhysReg I32Regs[64]
Definition VEAsmParser.cpp:97
static StringRef parseRD(StringRef Name, unsigned Prefix, SMLoc NameLoc, OperandVector *Operands)
Definition VEAsmParser.cpp:894
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmParser()
Definition VEAsmParser.cpp:1530
static bool isMImm(SDValue V)
Target independent representation for an assembler token.
LLVM_ABI SMLoc getLoc() const
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
bool is(TokenKind K) const
LLVM_ABI SMLoc getEndLoc() const
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Base class for user error types.
Container class for subtarget features.
void printExpr(raw_ostream &, const MCExpr &) const
Generic assembler parser interface, for use by target specific assembly parsers.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Opcode getOpcode() const
Get the kind of this binary expression.
static LLVM_ABI const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Base class for the full range of assembler expressions which are needed for parsing.
@ Unary
Unary expressions.
@ Constant
Constant expressions.
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
@ Specifier
Expression with a relocation specifier.
@ Binary
Binary expressions.
void addOperand(const MCOperand Op)
Interface to description of machine instruction set.
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Wrapper class representing physical registers. Should be passed by value.
constexpr unsigned id() const
static const MCSpecifierExpr * create(const MCExpr *Expr, Spec S, MCContext &Ctx, SMLoc Loc=SMLoc())
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
const MCSymbol & getSymbol() const
uint16_t getSpecifier() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Opcode getOpcode() const
Get the kind of this unary expression.
static LLVM_ABI const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
const MCExpr * getSubExpr() const
Get the child of this unary expression.
Ternary parse status returned by various parse* methods.
constexpr bool isFailure() const
static constexpr StatusTy Failure
constexpr bool isSuccess() const
static constexpr StatusTy Success
static constexpr StatusTy NoMatch
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
constexpr const char * getPointer() const
void push_back(const T &Elt)
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
LLVM_ABI std::string lower() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::variant< std::monostate, Loc::Single, Loc::Multi, Loc::MMI, Loc::EntryValue > Variant
Alias for the std::variant specialization base class of DbgVariable.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ CE
Windows NT (Windows on ARM)
Context & getContext() const
BaseReg
Stack frame base register. Bit 0 of FREInfo.Info.
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
static bool isMem(const MachineInstr &MI, unsigned Op)
LLVM_ABI std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
Target & getTheVETarget()
SmallVectorImpl< std::unique_ptr< MCParsedAsmOperand > > OperandVector
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
static VECC::CondCode stringToVEFCondCode(StringRef S)
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
@ Sub
Subtraction of integers.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
FunctionAddr VTableAddr Next
DWARFExpression::Operation Op
RoundingMode
Rounding mode.
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
static VERD::RoundingMode stringToVERD(StringRef S)
static VECC::CondCode stringToVEICondCode(StringRef S)
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...