VEDisassembler.cpp Source File (original) (raw)

15#include "VE.h"

25using namespace llvm;

28#define DEBUG_TYPE "ve-disassembler"

32namespace {

36public:

39 ~VEDisassembler() override = default;

44};

45}

50 return new VEDisassembler(STI, Ctx);

51}

62 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,

63 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,

64 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,

65 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,

66 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,

67 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,

68 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,

69 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,

70 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,

71 VE::SW63};

74 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,

75 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13,

76 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20,

77 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27,

78 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34,

79 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41,

80 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48,

81 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55,

82 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62,

83 VE::SX63};

86 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,

87 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,

88 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,

89 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,

90 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,

91 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,

92 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,

93 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,

94 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,

95 VE::SF63};

98 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,

99 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,

100 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,

101 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};

102

104 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7,

105 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,

106 VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23,

107 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,

108 VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39,

109 VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47,

110 VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55,

111 VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63};

112

114 VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5,

115 VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11,

116 VE::VM12, VE::VM13, VE::VM14, VE::VM15};

117

119 VE::VMP3, VE::VMP4, VE::VMP5,

120 VE::VMP6, VE::VMP7};

121

123 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,

124 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,

125 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,

126 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,

127 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,

128 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,

129 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,

130 VE::PMC12, VE::PMC13, VE::PMC14};

131

132

142

152

162

166 if (RegNo % 2 || RegNo > 63)

171}

172

176 unsigned Reg = VE::NoRegister;

177 if (RegNo == 255)

178 Reg = VE::VIX;

179 else if (RegNo > 63)

181 else

185}

186

196

200 if (RegNo % 2 || RegNo > 15)

205}

206

210 if (RegNo > 30)

213 if (Reg == VE::NoRegister)

217}

218

221

230

231

232 if (cz) {

235 return status;

236 } else {

238 }

239

240

241 if (cy) {

244 return status;

245 } else {

247 }

248

249

251

253}

254

261

262

263 if (cz) {

266 return status;

267 } else {

269 }

270

271

273

275}

276

281

284 status = DecodeSX(MI, sx, Address, Decoder);

286 return status;

287 }

288

289 status = DecodeASX(MI, insn, Address, Decoder);

291 return status;

292

294 status = DecodeSX(MI, sx, Address, Decoder);

296 return status;

297 }

299}

300

305

308 status = DecodeSX(MI, sx, Address, Decoder);

310 return status;

311 }

312

313 status = DecodeAS(MI, insn, Address, Decoder);

315 return status;

316

318 status = DecodeSX(MI, sx, Address, Decoder);

320 return status;

321 }

323}

324

329

335

340

346

351

357

361 return DecodeMemAS(Inst, insn, Address, Decoder, true,

363}

364

368 return DecodeMemAS(Inst, insn, Address, Decoder, false,

370}

371

378

379

381 status = DecodeSX(MI, sx, Address, Decoder);

383 return status;

384

385

386 status = DecodeAS(MI, insn, Address, Decoder);

388 return status;

389

390

391 if (cy && !isImmOnly) {

392 status = DecodeSX(MI, sy, Address, Decoder);

394 return status;

395 } else {

396 if (isUImm)

398 else

400 }

401

402

403 status = DecodeSX(MI, sx, Address, Decoder);

405 return status;

406

408}

409

412 return DecodeCAS(MI, insn, Address, Decoder, false, true,

414}

415

418 return DecodeCAS(MI, insn, Address, Decoder, false, true,

420}

421

424 return DecodeCAS(MI, insn, Address, Decoder, false, false,

426}

427

430 return DecodeCAS(MI, insn, Address, Decoder, false, false,

432}

433

438

445

452

454

455#define BCm_kind(NAME) \

456 case NAME##rri: \

457 case NAME##rzi: \

458 case NAME##iri: \

459 case NAME##izi: \

460 case NAME##rri_nt: \

461 case NAME##rzi_nt: \

462 case NAME##iri_nt: \

463 case NAME##izi_nt: \

464 case NAME##rri_t: \

465 case NAME##rzi_t: \

466 case NAME##iri_t: \

467 case NAME##izi_t:

468

469#define BCRm_kind(NAME) \

470 case NAME##rr: \

471 case NAME##ir: \

472 case NAME##rr_nt: \

473 case NAME##ir_nt: \

474 case NAME##rr_t: \

475 case NAME##ir_t:

476

477 {

479 switch (MI.getOpcode()) {

482 }

483 }

484#undef BCm_kind

485

486 return false;

487}

488

489

495

496

502

503

510

511

513

514

516 if (cy) {

519 return status;

520 } else {

522 }

523

524

525 return DecodeAS(MI, insn, Address, Decoder);

526}

527

531

532 return DecodeAS(MI, insn, Address, Decoder);

533}

534

535#include "VEGenDisassemblerTables.inc"

536

537

540 bool IsLittleEndian) {

541

542 if (Bytes.size() < 8) {

545 }

546

547 Insn = IsLittleEndian

556

558}

559

564 uint64_t Insn;

565 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();

570

571

572

573 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI);

574

578 }

579

581}

MCDisassembler::DecodeStatus DecodeStatus

static bool readInstruction64(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn)

static bool isLoad(int Opcode)

DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)

#define LLVM_EXTERNAL_VISIBILITY

static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:173

static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder, bool isImmOnly, bool isUImm, DecodeFunc DecodeSX)

Definition VEDisassembler.cpp:372

static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:439

static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:163

static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:416

static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:336

static DecodeStatus readInstruction64(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian)

Read four bytes from the ArrayRef and return 32 bit word.

Definition VEDisassembler.cpp:538

static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:347

static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:341

static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:325

static const unsigned I32RegDecoderTable[]

Definition VEDisassembler.cpp:61

static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:528

static const unsigned F128RegDecoderTable[]

Definition VEDisassembler.cpp:97

static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:143

static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:422

static bool isIntegerBCKind(MCInst &MI)

Definition VEDisassembler.cpp:453

static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:358

static const unsigned V64RegDecoderTable[]

Definition VEDisassembler.cpp:103

static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:504

static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:222

static const unsigned I64RegDecoderTable[]

Definition VEDisassembler.cpp:73

static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:410

static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:330

static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:352

static const unsigned F32RegDecoderTable[]

Definition VEDisassembler.cpp:85

static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:255

static const unsigned VM512RegDecoderTable[]

Definition VEDisassembler.cpp:118

static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:197

static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:434

static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:365

static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:133

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEDisassembler()

Definition VEDisassembler.cpp:54

static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:153

static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder, bool isLoad, DecodeFunc DecodeSX)

Definition VEDisassembler.cpp:277

static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:187

static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder, bool isLoad, DecodeFunc DecodeSX)

Definition VEDisassembler.cpp:301

static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:428

static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:490

static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:207

static const unsigned VMRegDecoderTable[]

Definition VEDisassembler.cpp:113

static MCDisassembler * createVEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition VEDisassembler.cpp:47

static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:497

static DecodeStatus DecodeSIMM32(MCInst &MI, uint64_t insn, uint64_t Address, const MCDisassembler *Decoder)

Definition VEDisassembler.cpp:446

static const unsigned MiscRegDecoderTable[]

Definition VEDisassembler.cpp:122

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Generic base class for all target subtargets.

Target - Wrapper for Target specific information.

This class implements an extremely fast bulk output stream that can only output to a stream.

std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)

Context & getContext() const

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheVETarget()

static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger)

static VERD::RoundingMode VEValToRD(unsigned Val)

constexpr int32_t SignExtend32(uint32_t X)

Sign-extend the number in the bottom B bits of X to a 32-bit integer.

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.