VEInstrInfo.cpp Source File (original) (raw)

14#include "VE.h"

27#define DEBUG_TYPE "ve-instr-info"

29using namespace llvm;

31#define GET_INSTRINFO_CTOR_DTOR

32#include "VEGenInstrInfo.inc"

35void VEInstrInfo::anchor() {}

43 switch (CC) {

90 }

92}

99#define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t)

100

101

103 "Branch relative word/double/float always instructions should not be "

104 "used!");

105 return BRKIND(BRCFL);

106#undef BRKIND

107}

108

109

110

113

114#define BRKIND(NAME) \

115 (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \

116 Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t)

118#undef BRKIND

119}

120

121

122

125

126#define BRKIND(NAME) \

127 (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t)

128

129

131 "Branch word/double/float always instructions should not be used!");

133#undef BRKIND

134}

135

143

147 bool AllowModify) const {

149 if (I == MBB.end())

150 return false;

151

152 if (!isUnpredicatedTerminator(*I))

153 return false;

154

155

157 unsigned LastOpc = LastInst->getOpcode();

158

159

160 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {

163 return false;

164 }

166

168 return false;

169 }

170 return true;

171 }

172

173

175 unsigned SecondLastOpc = SecondLastInst->getOpcode();

176

177

178

182 LastInst = SecondLastInst;

184 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {

185

187 return false;

188 }

189 SecondLastInst = &*I;

190 SecondLastOpc = SecondLastInst->getOpcode();

191 }

192 }

193

194

195 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))

196 return true;

197

198

202 return false;

203 }

204

205

206

209 return false;

210 }

211

212

213

215 I = LastInst;

216 if (AllowModify)

217 I->eraseFromParent();

218 return true;

219 }

220

221

222 return true;

223}

224

229 const DebugLoc &DL, int *BytesAdded) const {

230 assert(TBB && "insertBranch must not be told to insert a fallthrough");

232 "VE branch conditions should have three component!");

233 assert(!BytesAdded && "code size not handled");

234 if (Cond.empty()) {

235

236 assert(!FBB && "Unconditional branch with multiple successors!");

239 return 1;

240 }

241

242

243

245

246 unsigned opc[2];

252 if (TRI->getRegSizeInBits(Reg, MRI) == 32) {

253 opc[0] = VE::BRCFWir;

254 opc[1] = VE::BRCFWrr;

255 } else {

256 opc[0] = VE::BRCFLir;

257 opc[1] = VE::BRCFLrr;

258 }

259 } else {

260 if (TRI->getRegSizeInBits(Reg, MRI) == 32) {

261 opc[0] = VE::BRCFSir;

262 opc[1] = VE::BRCFSrr;

263 } else {

264 opc[0] = VE::BRCFDir;

265 opc[1] = VE::BRCFDrr;

266 }

267 }

268 if (Cond[1].isImm()) {

270 .add(Cond[0])

274 } else {

280 }

281

282 if (!FBB)

283 return 1;

284

287 return 2;

288}

289

291 int *BytesRemoved) const {

292 assert(!BytesRemoved && "code size not handled");

293

295 unsigned Count = 0;

296 while (I != MBB.begin()) {

297 --I;

298

299 if (I->isDebugValue())

300 continue;

301

304 break;

305

306 I->eraseFromParent();

307 I = MBB.end();

309 }

311}

312

319

321 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||

322 VE::F32RegClass.contains(Reg);

323}

324

329 const unsigned *SubRegIdx,

332

333 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) {

334 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]);

335 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]);

336 assert(SubDest && SubSrc && "Bad sub-register");

337

338 if (MCID.getOpcode() == VE::ORri) {

339

343 } else if (MCID.getOpcode() == VE::ANDMmm) {

344

348 } else {

350 }

351 }

352

354 if (KillSrc)

356}

357

361 bool RenamableDest, bool RenamableSrc) const {

362

367 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) {

368

369

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371

372

373

376 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32);

382 .addImm(M1(0))

386 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) {

390 } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) {

391

392 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd};

393 unsigned int NumSubRegs = 2;

396 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) {

397

398 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};

399 unsigned int NumSubRegs = 2;

402 } else {

404 dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI)

405 << " to " << printReg(DestReg, TRI) << "\n";

407 }

408}

409

410

411

412

413

414

416 int &FrameIndex) const {

417 if (MI.getOpcode() == VE::LDrii ||

418 MI.getOpcode() == VE::LDLSXrii ||

419 MI.getOpcode() == VE::LDUrii ||

420 MI.getOpcode() == VE::LDQrii ||

421 MI.getOpcode() == VE::LDVMrii ||

422 MI.getOpcode() == VE::LDVM512rii

423 ) {

424 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&

425 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() &&

426 MI.getOperand(3).getImm() == 0) {

427 FrameIndex = MI.getOperand(1).getIndex();

428 return MI.getOperand(0).getReg();

429 }

430 }

431 return 0;

432}

433

434

435

436

437

438

440 int &FrameIndex) const {

441 if (MI.getOpcode() == VE::STrii ||

442 MI.getOpcode() == VE::STLrii ||

443 MI.getOpcode() == VE::STUrii ||

444 MI.getOpcode() == VE::STQrii ||

445 MI.getOpcode() == VE::STVMrii ||

446 MI.getOpcode() == VE::STVM512rii

447 ) {

448 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&

449 MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() &&

450 MI.getOperand(2).getImm() == 0) {

451 FrameIndex = MI.getOperand(0).getIndex();

452 return MI.getOperand(3).getReg();

453 }

454 }

455 return 0;

456}

457

460 Register SrcReg, bool isKill, int FI,

465 if (I != MBB.end())

466 DL = I->getDebugLoc();

467

473

474

475 if (RC == &VE::I64RegClass) {

482 } else if (RC == &VE::I32RegClass) {

489 } else if (RC == &VE::F32RegClass) {

496 } else if (VE::F128RegClass.hasSubClassEq(RC)) {

503 } else if (RC == &VE::VMRegClass) {

510 } else if (VE::VM512RegClass.hasSubClassEq(RC)) {

517 } else

519}

520

528 if (I != MBB.end())

529 DL = I->getDebugLoc();

530

536

537 if (RC == &VE::I64RegClass) {

543 } else if (RC == &VE::I32RegClass) {

549 } else if (RC == &VE::F32RegClass) {

555 } else if (VE::F128RegClass.hasSubClassEq(RC)) {

561 } else if (RC == &VE::VMRegClass) {

567 } else if (VE::VM512RegClass.hasSubClassEq(RC)) {

573 } else

575}

576

580

582 int64_t ImmVal;

583 switch (DefMI.getOpcode()) {

584 default:

585 return false;

586 case VE::ORim:

587

590

593 ImmVal =

594 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm());

595 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");

596 break;

597 case VE::LEAzii:

598

601

603 if ( DefMI .getOperand(3).isImm())

604

605 return false;

606 ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm();

607 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");

608 break;

609 }

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636

639 unsigned NewUseOpcSImm7;

640 unsigned NewUseOpcMImm;

641 enum InstType {

642 rr2ri_rm,

643 rr2ir_rm,

644 } InstType;

645

647#define INSTRKIND(NAME) \

648 case NAME##rr: \

649 NewUseOpcSImm7 = NAME##ri; \

650 NewUseOpcMImm = NAME##rm; \

651 InstType = rr2ri_rm; \

652 break

653#define NCINSTRKIND(NAME) \

654 case NAME##rr: \

655 NewUseOpcSImm7 = NAME##ir; \

656 NewUseOpcMImm = NAME##rm; \

657 InstType = rr2ir_rm; \

658 break

659

660 switch (UseMI.getOpcode()) {

661 default:

662 return false;

663

696 }

697

698#undef INSTRKIND

699

700 unsigned NewUseOpc;

701 unsigned UseIdx;

702 bool Commute = false;

704 switch (InstType) {

705 case rr2ri_rm:

706 UseIdx = 2;

707 if (UseMI.getOperand(1).getReg() == Reg) {

708 Commute = true;

709 } else {

710 assert(UseMI.getOperand(2).getReg() == Reg);

711 }

713

714

715 NewUseOpc = NewUseOpcSImm7;

717

718 NewUseOpc = NewUseOpcMImm;

720 } else

721 return false;

722 break;

723 case rr2ir_rm:

724 if (UseMI.getOperand(1).getReg() == Reg) {

725

727 return false;

728 NewUseOpc = NewUseOpcSImm7;

729 UseIdx = 1;

730 } else {

731 assert(UseMI.getOperand(2).getReg() == Reg);

732

734 return false;

735 NewUseOpc = NewUseOpcMImm;

737 UseIdx = 2;

738 }

739 break;

740 }

741

743 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);

744 UseMI.setDesc(get(NewUseOpc));

745 if (Commute) {

746 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg());

747 }

748 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);

749 if (DeleteDef)

750 DefMI.eraseFromParent();

751

752 return true;

753}

754

758 if (GlobalBaseReg != 0)

759 return GlobalBaseReg;

760

761

762 GlobalBaseReg = VE::SX15;

763

764

765

769 BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg);

771 return GlobalBaseReg;

772}

773

775 return (reg - VE::VMP0) * 2 + VE::VM0;

776}

777

779

780

784

789

790 switch (MI.getOpcode()) {

791 default: {

796 break;

797 }

798 case VE::NEGMy:

801 break;

802 }

803 MI.eraseFromParent();

804}

805

808

811

812 switch (MI.getNumExplicitOperands()) {

813 default:

815 case 2:

816

817 MIB.addReg(MI.getOperand(1).getReg());

818 break;

819 case 4:

820

821 MIB.addImm(MI.getOperand(1).getImm());

822

823 MIB.addReg(MI.getOperand(2).getReg());

824

825 MIB.addReg(MI.getOperand(3).getReg());

826 break;

827 case 5:

828

829 MIB.addImm(MI.getOperand(1).getImm());

830

831 MIB.addReg(MI.getOperand(2).getReg());

832

835

836 MIB.addReg(MI.getOperand(4).getReg());

837 break;

838 }

839}

840

842

843

844

845 static const std::pair<unsigned, std::pair<unsigned, unsigned>> VFMKMap[] = {

846 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}},

847 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}},

848 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}},

849 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}},

850 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}},

851 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}},

852 };

853

854 unsigned Opcode = MI.getOpcode();

855

856 const auto *Found =

857 llvm::find_if(VFMKMap, [&](auto P) { return P.first == Opcode; });

858 if (Found == std::end(VFMKMap))

860

861 unsigned OpcodeUpper = (*Found).second.first;

862 unsigned OpcodeLower = (*Found).second.second;

863

866

871

872 MI.eraseFromParent();

873}

874

876 switch (MI.getOpcode()) {

877 case VE::EXTEND_STACK: {

879 }

880 case VE::EXTEND_STACK_GUARD: {

881 MI.eraseFromParent();

882 return true;

883 }

884 case VE::GETSTACKTOP: {

886 }

887

888 case VE::ANDMyy:

890 return true;

891 case VE::ORMyy:

893 return true;

894 case VE::XORMyy:

896 return true;

897 case VE::EQVMyy:

899 return true;

900 case VE::NNDMyy:

902 return true;

903 case VE::NEGMy:

905 return true;

906

907 case VE::LVMyir:

908 case VE::LVMyim:

909 case VE::LVMyir_y:

910 case VE::LVMyim_y: {

913 int64_t Imm = MI.getOperand(1).getImm();

914 bool IsSrcReg =

915 MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y;

916 Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister;

917 int64_t MImm = IsSrcReg ? 0 : MI.getOperand(2).getImm();

918 bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false;

920 if (Imm >= 4) {

921 VMX = VMXu;

922 Imm -= 4;

923 }

926 switch (MI.getOpcode()) {

927 case VE::LVMyir:

932 break;

933 case VE::LVMyim:

938 break;

939 case VE::LVMyir_y:

940 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&

941 "LVMyir_y has different register in 3rd operand");

947 break;

948 case VE::LVMyim_y:

949 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&

950 "LVMyim_y has different register in 3rd operand");

956 break;

957 }

958 MI.eraseFromParent();

959 return true;

960 }

961 case VE::SVMyi: {

962 Register Dest = MI.getOperand(0).getReg();

965 bool KillSrc = MI.getOperand(1).isKill();

966 int64_t Imm = MI.getOperand(2).getImm();

968 if (Imm >= 4) {

969 VMZ = VMZu;

970 Imm -= 4;

971 }

977 if (KillSrc) {

980 }

981 MI.eraseFromParent();

982 return true;

983 }

984 case VE::VFMKyal:

985 case VE::VFMKynal:

986 case VE::VFMKWyvl:

987 case VE::VFMKWyvyl:

988 case VE::VFMKSyvl:

989 case VE::VFMKSyvyl:

991 return true;

992 }

993 return false;

994}

995

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1024 MF.insert(It, syscallMBB);

1025 MF.insert(It, sinkMBB);

1026

1027

1030 BB->end());

1032

1033

1036 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t))

1038 .addReg(VE::SX11)

1039 .addReg(VE::SX8)

1041

1042 BB = syscallMBB;

1043

1044

1046

1047 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61)

1051 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62)

1054 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63)

1058 BuildMI(BB, dl, TII.get(VE::SHMLri))

1062 BuildMI(BB, dl, TII.get(VE::SHMLri))

1066 BuildMI(BB, dl, TII.get(VE::SHMLri))

1071

1072 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0)

1075

1076 MI.eraseFromParent();

1077 return true;

1078}

1079

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1101

1103 .addDef(MI.getOperand(0).getReg())

1107

1108 MI.eraseFromParent();

1109 return true;

1110}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

static bool isReg(const MCInst &MI, unsigned OpNo)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file defines the SmallVector class.

static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)

static bool IsIntegerCC(unsigned CC)

Definition VEInstrInfo.cpp:40

static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI)

Definition VEInstrInfo.cpp:841

#define NCINSTRKIND(NAME)

static Register getVM512Lower(Register reg)

Definition VEInstrInfo.cpp:778

static void copyPhysSubRegs(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const MCInstrDesc &MCID, unsigned int NumSubRegs, const unsigned *SubRegIdx, const TargetRegisterInfo *TRI)

Definition VEInstrInfo.cpp:325

static bool IsAliasOfSX(Register Reg)

Definition VEInstrInfo.cpp:320

static Register getVM512Upper(Register reg)

Definition VEInstrInfo.cpp:774

static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID)

Definition VEInstrInfo.cpp:781

static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI, bool Upper)

Definition VEInstrInfo.cpp:806

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

LLVM Basic Block Representation.

Describe properties that are true of each instruction in the target description file.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Wrapper class representing physical registers. Should be passed by value.

LLVM_ABI void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)

Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool adjustsStack() const

Return true if this function adjusts the stack – e.g., when calling another function.

uint64_t getMaxCallFrameSize() const

Return the maximum size of a call frame that must be allocated for an outgoing function call.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

BasicBlockListType::iterator iterator

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineBasicBlock & front() const

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineInstr - Allocate a new MachineInstr.

void insert(iterator MBBI, MachineBasicBlock *MBB)

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register use operand.

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

LLVM_ABI bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI kills a register.

LLVM_ABI void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)

We have determined MI defines a register.

const MachineOperand & getOperand(unsigned i) const

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineBasicBlock * getMBB() const

static MachineOperand CreateImm(int64_t Val)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Target - Wrapper for Target specific information.

bool hasReservedCallFrame(const MachineFunction &MF) const override

hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

} Stack Spill & Reload

Definition VEInstrInfo.cpp:577

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

} Branch Analysis & Modification

Definition VEInstrInfo.cpp:358

bool expandPostRAPseudo(MachineInstr &MI) const override

Definition VEInstrInfo.cpp:875

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition VEInstrInfo.cpp:290

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition VEInstrInfo.cpp:521

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition VEInstrInfo.cpp:458

} Optimization

Definition VEInstrInfo.cpp:755

const VERegisterInfo & getRegisterInfo() const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition VEInstrInfo.cpp:225

Stack Spill & Reload {.

Definition VEInstrInfo.cpp:415

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

Branch Analysis & Modification {.

Definition VEInstrInfo.cpp:144

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...

Definition VEInstrInfo.cpp:439

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Definition VEInstrInfo.cpp:313

VEInstrInfo(const VESubtarget &ST)

Definition VEInstrInfo.cpp:37

bool expandExtendStackPseudo(MachineInstr &MI) const

Definition VEInstrInfo.cpp:996

bool expandGetStackTopPseudo(MachineInstr &MI) const

Definition VEInstrInfo.cpp:1080

void setGlobalBaseReg(Register Reg)

uint64_t getAdjustedFrameSize(uint64_t FrameSize) const

Given a actual stack size as determined by FrameInfo, this function returns adjusted framesize which ...

const VEInstrInfo * getInstrInfo() const override

const VEFrameLowering * getFrameLowering() const override

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

static bool isCondBranchOpcode(int Opc)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

static bool isIndirectBranchOpcode(int Opc)

unsigned M1(unsigned Val)

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

FunctionAddr VTableAddr Count

static uint64_t val2MImm(uint64_t Val)

val2MImm - Convert an integer immediate value to target MImm immediate.

unsigned getKillRegState(bool B)

static uint64_t mimm2Val(uint64_t Val)

mimm2Val - Convert a target MImm immediate to an integer immediate value.

static bool isUncondBranchOpcode(int Opc)

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

static bool isMImmVal(uint64_t Val)

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.