LLVM: lib/Target/VE/VEInstrInfo.cpp File Reference (original) (raw)
Go to the source code of this file.
| Macros | |
|---|---|
| #define | DEBUG_TYPE "ve-instr-info" |
| #define | GET_INSTRINFO_CTOR_DTOR |
| #define | BRKIND(NAME) |
| #define | BRKIND(NAME) |
| #define | BRKIND(NAME) |
| #define | INSTRKIND(NAME) |
| #define | NCINSTRKIND(NAME) |
| Functions | |
|---|---|
| static bool | IsIntegerCC (unsigned CC) |
| static VECC::CondCode | GetOppositeBranchCondition (VECC::CondCode CC) |
| static bool | isUncondBranchOpcode (int Opc) |
| static bool | isCondBranchOpcode (int Opc) |
| static bool | isIndirectBranchOpcode (int Opc) |
| static void | parseCondBranch (MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond) |
| static bool | IsAliasOfSX (Register Reg) |
| static void | copyPhysSubRegs (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const MCInstrDesc &MCID, unsigned int NumSubRegs, const unsigned *SubRegIdx, const TargetRegisterInfo *TRI) |
| static Register | getVM512Upper (Register reg) |
| static Register | getVM512Lower (Register reg) |
| static void | expandPseudoLogM (MachineInstr &MI, const MCInstrDesc &MCID) |
| static void | addOperandsForVFMK (MachineInstrBuilder &MIB, MachineInstr &MI, bool Upper) |
| static void | expandPseudoVFMK (const TargetInstrInfo &TI, MachineInstr &MI) |
◆ BRKIND [1/3]
◆ BRKIND [2/3]
Value:
(Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \
Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t)
◆ BRKIND [3/3]
Value:
(Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t)
◆ DEBUG_TYPE
#define DEBUG_TYPE "ve-instr-info"
◆ GET_INSTRINFO_CTOR_DTOR
#define GET_INSTRINFO_CTOR_DTOR
◆ INSTRKIND
| #define INSTRKIND | ( | NAME | ) |
|---|
◆ NCINSTRKIND
| #define NCINSTRKIND | ( | NAME | ) |
|---|
◆ addOperandsForVFMK()
◆ copyPhysSubRegs()
Definition at line 325 of file VEInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), assert(), llvm::BuildMI(), DL, llvm::MachineInstrBuilder::getInstr(), I, llvm_unreachable, MBB, and TRI.
Referenced by llvm::VEInstrInfo::copyPhysReg().
◆ expandPseudoLogM()
◆ expandPseudoVFMK()
◆ GetOppositeBranchCondition()
Definition at line 42 of file VEInstrInfo.cpp.
References llvm::VECC::CC_AF, llvm::VECC::CC_AT, llvm::VECC::CC_EQ, llvm::VECC::CC_EQNAN, llvm::VECC::CC_G, llvm::VECC::CC_GE, llvm::VECC::CC_GENAN, llvm::VECC::CC_GNAN, llvm::VECC::CC_IEQ, llvm::VECC::CC_IG, llvm::VECC::CC_IGE, llvm::VECC::CC_IL, llvm::VECC::CC_ILE, llvm::VECC::CC_INE, llvm::VECC::CC_L, llvm::VECC::CC_LE, llvm::VECC::CC_LENAN, llvm::VECC::CC_LNAN, llvm::VECC::CC_NAN, llvm::VECC::CC_NE, llvm::VECC::CC_NENAN, llvm::VECC::CC_NUM, llvm_unreachable, and llvm::VECC::UNKNOWN.
◆ getVM512Lower()
◆ getVM512Upper()
◆ IsAliasOfSX()
◆ isCondBranchOpcode()
| bool isCondBranchOpcode ( int Opc) | static |
|---|
◆ isIndirectBranchOpcode()
| bool isIndirectBranchOpcode ( int Opc) | static |
|---|
◆ IsIntegerCC()
◆ isUncondBranchOpcode()
| bool isUncondBranchOpcode ( int Opc) | static |
|---|