VLIWMachineScheduler.h Source File (original) (raw)

11#ifndef LLVM_CODEGEN_VLIWMACHINESCHEDULER_H

12#define LLVM_CODEGEN_VLIWMACHINESCHEDULER_H

18#include

19#include

20#include

22namespace llvm {

32protected:

49public:

55 virtual void reset();

64protected:

66};

71public:

73 std::unique_ptr S)

82};

90protected:

100

102

104 };

105

116

117

118

123

124

125

126

130

134

137

141

142

143 unsigned MinReadyCycle = std::numeric_limits::max();

144

145

147

148

149

153

157

159 DAG = dag;

163

164

165

166

167

168 const auto BBSize = DAG->getBBSize();

170 if (BBSize < 50)

171

172

173

175 else {

176

177

178 unsigned MaxPath = 0;

179 for (auto &SU : DAG->SUnits)

180 MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth());

182 }

183 }

184

188

190

192

194

196

198

200

202

209 };

210

213

214

217

218

220

221public:

222

224

227

229

231

233

235

237

239 return Top.ResourceModel->getTotalPackets() +

240 Bot.ResourceModel->getTotalPackets();

241 }

242

243protected:

247

249

251

254 bool verbose);

255

258 SchedCandidate &Candidate);

259#ifndef NDEBUG

262

264 SchedCandidate &Candidate, ReadyQueue &Q);

265#endif

266};

267

268}

269

270#endif

This file defines the SmallVector class.

VLIWMachineScheduler * DAG

Definition VLIWMachineScheduler.h:211

~ConvergingVLIWScheduler() override=default

void releaseBottomNode(SUnit *SU) override

When all successor dependencies have been resolved, free this node for bottom-up scheduling.

static constexpr unsigned PriorityOne

Definition VLIWMachineScheduler.h:119

SUnit * pickNode(bool &IsTopNode) override

Pick the best node to balance the schedule. Implements MachineSchedStrategy.

virtual VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const

unsigned reportPackets()

Definition VLIWMachineScheduler.h:238

VLIWSchedBoundary Top

Definition VLIWMachineScheduler.h:215

int pressureChange(const SUnit *SU, bool isBotUp)

Check if the instruction changes the register pressure of a register in the high pressure set.

SmallVector< bool > HighPressureSets

List of pressure sets that have a high pressure level in the region.

Definition VLIWMachineScheduler.h:219

@ BotQID

Definition VLIWMachineScheduler.h:223

@ LogMaxQID

Definition VLIWMachineScheduler.h:223

@ TopQID

Definition VLIWMachineScheduler.h:223

static constexpr unsigned ScaleTwo

Definition VLIWMachineScheduler.h:122

VLIWSchedBoundary Bot

Definition VLIWMachineScheduler.h:216

CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)

Pick the best candidate from the top queue.

void schedNode(SUnit *SU, bool IsTopNode) override

Update the scheduler's state after scheduling a node.

void readyQueueVerboseDump(const RegPressureTracker &RPTracker, SchedCandidate &Candidate, ReadyQueue &Q)

void releaseTopNode(SUnit *SU) override

When all predecessor dependencies have been resolved, free this node for top-down scheduling.

SUnit * pickNodeBidrectional(bool &IsTopNode)

Pick the best candidate node from either the top or bottom queue.

static constexpr unsigned PriorityTwo

Definition VLIWMachineScheduler.h:120

ConvergingVLIWScheduler()

Definition VLIWMachineScheduler.h:225

static constexpr unsigned PriorityThree

Definition VLIWMachineScheduler.h:121

const TargetSchedModel * SchedModel

Definition VLIWMachineScheduler.h:212

void initialize(ScheduleDAGMI *dag) override

Initialize the strategy after building the DAG for a new region.

virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)

Single point to compute overall scheduling cost.

void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P=PressureChange())

CandResult

Represent the type of SchedCandidate found within a single queue.

Definition VLIWMachineScheduler.h:106

@ BestCost

Definition VLIWMachineScheduler.h:113

@ NodeOrder

Definition VLIWMachineScheduler.h:108

@ Weak

Definition VLIWMachineScheduler.h:114

@ MultiPressure

Definition VLIWMachineScheduler.h:112

@ SingleCritical

Definition VLIWMachineScheduler.h:110

@ SingleMax

Definition VLIWMachineScheduler.h:111

@ SingleExcess

Definition VLIWMachineScheduler.h:109

@ NoCand

Definition VLIWMachineScheduler.h:107

MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.

Capture a change in pressure for a single pressure set.

Helpers for implementing custom MachineSchedStrategy classes.

Track the current register pressure at some position in the instruction stream, and remember the high...

Scheduling unit. This is a node in the scheduling DAG.

unsigned getHeight() const

Returns the height of this node, which is the length of the maximum path down to any node which has n...

unsigned getDepth() const

Returns the depth of this node, which is the length of the maximum path up to any node which has no p...

MachineBasicBlock * BB

The block in which to insert instructions.

ScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)

RegisterClassInfo * RegClassInfo

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

Provide an instruction scheduling machine model to CodeGen passes.

TargetSubtargetInfo - Generic base class for all target subtargets.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...

Definition VLIWMachineScheduler.h:70

int getBBSize()

Definition VLIWMachineScheduler.h:81

VLIWMachineScheduler(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)

Definition VLIWMachineScheduler.h:72

RegisterClassInfo * getRegClassInfo()

Definition VLIWMachineScheduler.h:80

void schedule() override

Schedule - This is called back from ScheduleDAGInstrs::Run() when it's time to do some work.

unsigned TotalPackets

Total packets created.

Definition VLIWMachineScheduler.h:47

size_t getPacketInstCount() const

Definition VLIWMachineScheduler.h:61

virtual ~VLIWResourceModel()

virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu)

Return true if there is a dependence between SUd and SUu.

virtual DFAPacketizer * createPacketizer(const TargetSubtargetInfo &STI) const

virtual bool reserveResources(SUnit *SU, bool IsTop)

Keep track of available resources.

VLIWResourceModel & operator=(const VLIWResourceModel &other)=delete

bool isInPacket(SUnit *SU) const

Definition VLIWMachineScheduler.h:62

DFAPacketizer * ResourcesModel

ResourcesModel - Represents VLIW state.

Definition VLIWMachineScheduler.h:38

SmallVector< SUnit * > Packet

Local packet/bundle model.

Definition VLIWMachineScheduler.h:44

const TargetSchedModel * SchedModel

Definition VLIWMachineScheduler.h:40

VLIWResourceModel(const VLIWResourceModel &other)=delete

VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)

unsigned getTotalPackets() const

Definition VLIWMachineScheduler.h:60

virtual bool isResourceAvailable(SUnit *SU, bool IsTop)

Check if scheduling of this SU is possible in the current packet.

const TargetInstrInfo * TII

Definition VLIWMachineScheduler.h:33

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

OutputIt move(R &&Range, OutputIt Out)

Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

Implement std::hash so that hash_code can be used in STL containers.

RegPressureDelta RPDelta

Definition VLIWMachineScheduler.h:98

int SCost

Definition VLIWMachineScheduler.h:101

SUnit * SU

Definition VLIWMachineScheduler.h:95

Each Scheduling boundary is associated with ready queues.

Definition VLIWMachineScheduler.h:127

unsigned IssueCount

Definition VLIWMachineScheduler.h:139

const TargetSchedModel * SchedModel

Definition VLIWMachineScheduler.h:129

unsigned CriticalPathLength

Definition VLIWMachineScheduler.h:140

bool isLatencyBound(SUnit *SU)

Definition VLIWMachineScheduler.h:203

VLIWSchedBoundary(unsigned ID, const Twine &Name)

Pending queues extend the ready queues with the same ID and the PendingFlag set.

Definition VLIWMachineScheduler.h:150

void releaseNode(SUnit *SU, unsigned ReadyCycle)

void removeReady(SUnit *SU)

Remove SU from the ready set for this boundary.

bool CheckPending

Definition VLIWMachineScheduler.h:133

VLIWSchedBoundary & operator=(const VLIWSchedBoundary &other)=delete

ReadyQueue Pending

Definition VLIWMachineScheduler.h:132

bool isTop() const

Definition VLIWMachineScheduler.h:185

ScheduleHazardRecognizer * HazardRec

Definition VLIWMachineScheduler.h:135

void bumpNode(SUnit *SU)

Move the boundary of scheduled code by one SUnit.

unsigned MinReadyCycle

MinReadyCycle - Cycle of the soonest available instruction.

Definition VLIWMachineScheduler.h:143

VLIWResourceModel * ResourceModel

Definition VLIWMachineScheduler.h:136

void releasePending()

Release pending ready nodes in to the available queue.

unsigned CurrCycle

Definition VLIWMachineScheduler.h:138

ReadyQueue Available

Definition VLIWMachineScheduler.h:131

VLIWMachineScheduler * DAG

Definition VLIWMachineScheduler.h:128

SUnit * pickOnlyChoice()

If this queue only has one ready candidate, return it.

void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel)

Definition VLIWMachineScheduler.h:158

void bumpCycle()

Move the boundary of scheduled code by one cycle.

bool checkHazard(SUnit *SU)

Does this SU have a hazard within the current instruction group.

VLIWSchedBoundary(const VLIWSchedBoundary &other)=delete

unsigned MaxMinLatency

Definition VLIWMachineScheduler.h:146

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

Store the effects of a change in pressure on things that MI scheduler cares about.