LLVM: llvm::ConvergingVLIWScheduler Class Reference (original) (raw)

#include "[llvm/CodeGen/VLIWMachineScheduler.h](VLIWMachineScheduler%5F8h%5Fsource.html)"

Public Member Functions
ConvergingVLIWScheduler ()
~ConvergingVLIWScheduler () override=default
void initialize (ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
SUnit * pickNode (bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
void schedNode (SUnit *SU, bool IsTopNode) override
Update the scheduler's state after scheduling a node.
void releaseTopNode (SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling.
void releaseBottomNode (SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
unsigned reportPackets ()
Public Member Functions inherited from llvm::MachineSchedStrategy
virtual ~MachineSchedStrategy ()=default
virtual void initPolicy (MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs)
Optionally override the per-region scheduling policy.
virtual MachineSchedPolicy getPolicy () const
virtual void dumpPolicy () const
virtual bool shouldTrackPressure () const
Check if pressure tracking is needed before building the DAG and initializing this strategy.
virtual bool shouldTrackLaneMasks () const
Returns true if lanemasks should be tracked.
virtual bool doMBBSchedRegionsTopDown () const
virtual void enterMBB (MachineBasicBlock *MBB)
Tell the strategy that MBB is about to be processed.
virtual void leaveMBB ()
Tell the strategy that current MBB is done.
virtual void registerRoots ()
Notify this strategy that all roots have been released (including those that depend on EntrySU or ExitSU).
virtual void scheduleTree (unsigned SubtreeID)
Scheduler callback to notify that a new subtree is scheduled.
Protected Member Functions
virtual VLIWResourceModel * createVLIWResourceModel (const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const
SUnit * pickNodeBidrectional (bool &IsTopNode)
Pick the best candidate node from either the top or bottom queue.
int pressureChange (const SUnit *SU, bool isBotUp)
Check if the instruction changes the register pressure of a register in the high pressure set.
virtual int SchedulingCost (ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
Single point to compute overall scheduling cost.
CandResult pickNodeFromQueue (VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
Pick the best candidate from the top queue.
void traceCandidate (const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P=PressureChange())
void readyQueueVerboseDump (const RegPressureTracker &RPTracker, SchedCandidate &Candidate, ReadyQueue &Q)
Protected Attributes
VLIWMachineScheduler * DAG = nullptr
const TargetSchedModel * SchedModel = nullptr
VLIWSchedBoundary Top
VLIWSchedBoundary Bot
SmallVector< bool > HighPressureSets
List of pressure sets that have a high pressure level in the region.

Definition at line 89 of file VLIWMachineScheduler.h.

◆ anonymous enum

◆ CandResult

Represent the type of SchedCandidate found within a single queue.

Enumerator
NoCand
NodeOrder
SingleExcess
SingleCritical
SingleMax
MultiPressure
BestCost
Weak

Definition at line 106 of file VLIWMachineScheduler.h.

llvm::ConvergingVLIWScheduler::ConvergingVLIWScheduler ( ) inline

◆ ~ConvergingVLIWScheduler()

llvm::ConvergingVLIWScheduler::~ConvergingVLIWScheduler ( ) overridedefault

◆ createVLIWResourceModel()

◆ initialize()

void ConvergingVLIWScheduler::initialize ( ScheduleDAGMI * DAG) overridevirtual

◆ pickNode()

SUnit * ConvergingVLIWScheduler::pickNode ( bool & IsTopNode) overridevirtual

Pick the best node to balance the schedule. Implements MachineSchedStrategy.

Implements llvm::MachineSchedStrategy.

Definition at line 946 of file VLIWMachineScheduler.cpp.

References assert(), Bot, llvm::MISched::BottomUp, DAG, llvm::dbgs(), llvm::SUnit::isBottomReady(), llvm::SUnit::isTopReady(), LLVM_DEBUG, NoCand, pickNodeBidrectional(), pickNodeFromQueue(), llvm::PreRADirection, reportPackets(), llvm::ConvergingVLIWScheduler::SchedCandidate::SU, Top, and llvm::MISched::TopDown.

◆ pickNodeBidrectional()

SUnit * ConvergingVLIWScheduler::pickNodeBidrectional ( bool & IsTopNode) protected

Pick the best candidate node from either the top or bottom queue.

Definition at line 880 of file VLIWMachineScheduler.cpp.

References assert(), Bot, DAG, llvm::dbgs(), LLVM_DEBUG, NoCand, pickNodeFromQueue(), llvm::ConvergingVLIWScheduler::SchedCandidate::SCost, SingleCritical, SingleExcess, SingleMax, llvm::ConvergingVLIWScheduler::SchedCandidate::SU, and Top.

Referenced by pickNode().

◆ pickNodeFromQueue()

Pick the best candidate from the top queue.

TODO: getMaxPressureDelta results can be mostly cached for each SUnit during DAG building. To adjust for the current scheduling location we need to maintain the number of vreg uses remaining to be top-scheduled.

Definition at line 765 of file VLIWMachineScheduler.cpp.

References llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::Available, llvm::ReadyQueue::begin(), BestCost, BotQID, DAG, llvm::ReadyQueue::dump(), llvm::ReadyQueue::end(), llvm::ReadyQueue::getID(), llvm::getWeakLeft(), I, llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::isLatencyBound(), LLVM_DEBUG, NoCand, llvm::SUnit::NodeNum, NodeOrder, llvm::SUnit::Preds, readyQueueVerboseDump(), llvm::ConvergingVLIWScheduler::SchedCandidate::RPDelta, SchedDebugVerboseLevel, SchedulingCost(), llvm::ConvergingVLIWScheduler::SchedCandidate::SCost, llvm::ConvergingVLIWScheduler::SchedCandidate::SU, llvm::SUnit::Succs, TopQID, traceCandidate(), UseNewerCandidate, and Weak.

Referenced by pickNode(), and pickNodeBidrectional().

◆ pressureChange()

int ConvergingVLIWScheduler::pressureChange ( const SUnit * SU, bool isBotUp ) protected

Check if the instruction changes the register pressure of a register in the high pressure set.

The function returns a negative value if the pressure decreases and a positive value is the pressure increases. If the instruction doesn't use a high pressure register or doesn't change the register pressure, then return 0.

Definition at line 576 of file VLIWMachineScheduler.cpp.

References DAG, HighPressureSets, and P.

Referenced by SchedulingCost().

◆ readyQueueVerboseDump()

◆ releaseBottomNode()

void ConvergingVLIWScheduler::releaseBottomNode ( SUnit * SU) overridevirtual

◆ releaseTopNode()

void ConvergingVLIWScheduler::releaseTopNode ( SUnit * SU) overridevirtual

◆ reportPackets()

unsigned llvm::ConvergingVLIWScheduler::reportPackets ( ) inline

◆ schedNode()

void ConvergingVLIWScheduler::schedNode ( SUnit * SU, bool IsTopNode ) overridevirtual

◆ SchedulingCost()

Single point to compute overall scheduling cost.

TODO: More heuristics will be used soon.

Reimplemented in llvm::HexagonConvergingVLIWScheduler.

Definition at line 592 of file VLIWMachineScheduler.cpp.

References Bot, BotQID, CheckEarlyAvail, llvm::RegPressureDelta::CriticalMax, llvm::RegPressureDelta::CurrentMax, llvm::dbgs(), llvm::RegPressureDelta::Excess, llvm::SUnit::getDepth(), llvm::SUnit::getHeight(), llvm::ReadyQueue::getID(), llvm::SUnit::getInstr(), llvm::SDep::getLatency(), llvm::SDep::getSUnit(), llvm::PressureChange::getUnitInc(), llvm::getWeakLeft(), IgnoreBBRegPressure, llvm::SDep::isAssignedRegDep(), llvm::MachineInstr::isPseudo(), llvm::SUnit::isScheduled, llvm::SUnit::isScheduleHigh, isSingleUnscheduledPred(), isSingleUnscheduledSucc(), LLVM_DEBUG, llvm::SUnit::Preds, pressureChange(), PriorityOne, PriorityThree, PriorityTwo, ScaleTwo, llvm::SUnit::Succs, Top, and TopQID.

Referenced by pickNodeFromQueue(), readyQueueVerboseDump(), and llvm::HexagonConvergingVLIWScheduler::SchedulingCost().

◆ traceCandidate()

◆ Bot

◆ DAG

◆ HighPressureSets

◆ PriorityOne

unsigned llvm::ConvergingVLIWScheduler::PriorityOne = 200 staticconstexprprotected

◆ PriorityThree

unsigned llvm::ConvergingVLIWScheduler::PriorityThree = 75 staticconstexprprotected

◆ PriorityTwo

unsigned llvm::ConvergingVLIWScheduler::PriorityTwo = 50 staticconstexprprotected

◆ ScaleTwo

unsigned llvm::ConvergingVLIWScheduler::ScaleTwo = 10 staticconstexprprotected

◆ SchedModel

◆ Top

The documentation for this class was generated from the following files: