LLVM: lib/Target/X86/MCTargetDesc/X86BaseInfo.h Source File (original) (raw)
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16#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18
23
24namespace llvm {
25namespace X86 {
26
27
28enum {
33
35
37};
38
39
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49
50
68
74
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76
104
105
106
115
122
123
124
127 switch (Opcode) {
128 default:
130
131 case X86::TEST16i16:
132 case X86::TEST16mr:
133 case X86::TEST16ri:
134 case X86::TEST16rr:
135 case X86::TEST32i32:
136 case X86::TEST32mr:
137 case X86::TEST32ri:
138 case X86::TEST32rr:
139 case X86::TEST64i32:
140 case X86::TEST64mr:
141 case X86::TEST64ri32:
142 case X86::TEST64rr:
143 case X86::TEST8i8:
144 case X86::TEST8mr:
145 case X86::TEST8ri:
146 case X86::TEST8rr:
148 case X86::AND16i16:
149 case X86::AND16ri:
150 case X86::AND16ri8:
151 case X86::AND16rm:
152 case X86::AND16rr:
153 case X86::AND32i32:
154 case X86::AND32ri:
155 case X86::AND32ri8:
156 case X86::AND32rm:
157 case X86::AND32rr:
158 case X86::AND64i32:
159 case X86::AND64ri32:
160 case X86::AND64ri8:
161 case X86::AND64rm:
162 case X86::AND64rr:
163 case X86::AND8i8:
164 case X86::AND8ri:
165 case X86::AND8ri8:
166 case X86::AND8rm:
167 case X86::AND8rr:
169
170 case X86::CMP16i16:
171 case X86::CMP16mr:
172 case X86::CMP16ri:
173 case X86::CMP16ri8:
174 case X86::CMP16rm:
175 case X86::CMP16rr:
176 case X86::CMP32i32:
177 case X86::CMP32mr:
178 case X86::CMP32ri:
179 case X86::CMP32ri8:
180 case X86::CMP32rm:
181 case X86::CMP32rr:
182 case X86::CMP64i32:
183 case X86::CMP64mr:
184 case X86::CMP64ri32:
185 case X86::CMP64ri8:
186 case X86::CMP64rm:
187 case X86::CMP64rr:
188 case X86::CMP8i8:
189 case X86::CMP8mr:
190 case X86::CMP8ri:
191 case X86::CMP8ri8:
192 case X86::CMP8rm:
193 case X86::CMP8rr:
195
196 case X86::ADD16i16:
197 case X86::ADD16ri:
198 case X86::ADD16ri8:
199 case X86::ADD16rm:
200 case X86::ADD16rr:
201 case X86::ADD32i32:
202 case X86::ADD32ri:
203 case X86::ADD32ri8:
204 case X86::ADD32rm:
205 case X86::ADD32rr:
206 case X86::ADD64i32:
207 case X86::ADD64ri32:
208 case X86::ADD64ri8:
209 case X86::ADD64rm:
210 case X86::ADD64rr:
211 case X86::ADD8i8:
212 case X86::ADD8ri:
213 case X86::ADD8ri8:
214 case X86::ADD8rm:
215 case X86::ADD8rr:
216
217 case X86::SUB16i16:
218 case X86::SUB16ri:
219 case X86::SUB16ri8:
220 case X86::SUB16rm:
221 case X86::SUB16rr:
222 case X86::SUB32i32:
223 case X86::SUB32ri:
224 case X86::SUB32ri8:
225 case X86::SUB32rm:
226 case X86::SUB32rr:
227 case X86::SUB64i32:
228 case X86::SUB64ri32:
229 case X86::SUB64ri8:
230 case X86::SUB64rm:
231 case X86::SUB64rr:
232 case X86::SUB8i8:
233 case X86::SUB8ri:
234 case X86::SUB8ri8:
235 case X86::SUB8rm:
236 case X86::SUB8rr:
238
239 case X86::INC16r:
240 case X86::INC16r_alt:
241 case X86::INC32r:
242 case X86::INC32r_alt:
243 case X86::INC64r:
244 case X86::INC8r:
245
246 case X86::DEC16r:
247 case X86::DEC16r_alt:
248 case X86::DEC32r:
249 case X86::DEC32r_alt:
250 case X86::DEC64r:
251 case X86::DEC8r:
253 }
254}
255
256
261 switch (CC) {
262 default:
283 }
284}
285
286
287
288
289
292 switch (FirstKind) {
295 return true;
303 return false;
304 }
306}
307
308
318
319
328
329
330
333 switch (Reg.id()) {
334 default:
336 case X86::CS:
338 case X86::DS:
340 case X86::ES:
342 case X86::FS:
344 case X86::GS:
346 case X86::SS:
348 }
349}
350
351}
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489};
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903 default:
908 return 1;
911 return 2;
915 return 4;
917 return 8;
918 }
919}
920
921
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925 default:
930 return true;
937 return false;
938 }
939}
940
941
942
945 default:
948 return true;
957 return false;
958 }
959}
960
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969 unsigned NumDefs = Desc.getNumDefs();
970 unsigned NumOps = Desc.getNumOperands();
971 switch (NumDefs) {
972 default:
974 case 0:
975 return 0;
976 case 1:
977
979 return 1;
980
981
983 return 1;
984 return 0;
985 case 2:
986
989 return 2;
990
991
995 return 2;
996 return 0;
997 }
998}
999
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1007
1008
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1016 default:
1017 llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
1029 return -1;
1036
1037
1038 return 1 + HasVEX_4V + HasEVEX_K;
1040
1041 return 1 + HasEVEX_K;
1043
1044 return 3;
1048
1049
1050 return 1;
1068 return -1;
1077 return -1;
1088
1089 return 0 + HasVEX_4V + HasEVEX_K;
1154 return -1;
1155 }
1156}
1157
1158
1160 static_assert(X86::XMM15 - X86::XMM0 == 15,
1161 "XMM0-15 registers are not continuous");
1162 static_assert(X86::XMM31 - X86::XMM16 == 15,
1163 "XMM16-31 registers are not continuous");
1164 return (Reg >= X86::XMM0 && Reg <= X86::XMM15) ||
1165 (Reg >= X86::XMM16 && Reg <= X86::XMM31);
1166}
1167
1168
1170 static_assert(X86::YMM15 - X86::YMM0 == 15,
1171 "YMM0-15 registers are not continuous");
1172 static_assert(X86::YMM31 - X86::YMM16 == 15,
1173 "YMM16-31 registers are not continuous");
1174 return (Reg >= X86::YMM0 && Reg <= X86::YMM15) ||
1175 (Reg >= X86::YMM16 && Reg <= X86::YMM31);
1176}
1177
1178
1180 static_assert(X86::ZMM31 - X86::ZMM0 == 31,
1181 "ZMM registers are not continuous");
1182 return Reg >= X86::ZMM0 && Reg <= X86::ZMM31;
1183}
1184
1185
1187 static_assert(X86::R31WH - X86::R16 == 95, "EGPRs are not continuous");
1188 return Reg >= X86::R16 && Reg <= X86::R31WH;
1189}
1190
1191
1192
1194 if ((Reg >= X86::XMM8 && Reg <= X86::XMM15) ||
1195 (Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1196 (Reg >= X86::YMM8 && Reg <= X86::YMM15) ||
1197 (Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1198 (Reg >= X86::ZMM8 && Reg <= X86::ZMM31))
1199 return true;
1200
1202 return true;
1203
1204 switch (Reg.id()) {
1205 default:
1206 break;
1207 case X86::R8:
1208 case X86::R9:
1209 case X86::R10:
1210 case X86::R11:
1211 case X86::R12:
1212 case X86::R13:
1213 case X86::R14:
1214 case X86::R15:
1215 case X86::R8D:
1216 case X86::R9D:
1217 case X86::R10D:
1218 case X86::R11D:
1219 case X86::R12D:
1220 case X86::R13D:
1221 case X86::R14D:
1222 case X86::R15D:
1223 case X86::R8W:
1224 case X86::R9W:
1225 case X86::R10W:
1226 case X86::R11W:
1227 case X86::R12W:
1228 case X86::R13W:
1229 case X86::R14W:
1230 case X86::R15W:
1231 case X86::R8B:
1232 case X86::R9B:
1233 case X86::R10B:
1234 case X86::R11B:
1235 case X86::R12B:
1236 case X86::R13B:
1237 case X86::R14B:
1238 case X86::R15B:
1239 case X86::CR8:
1240 case X86::CR9:
1241 case X86::CR10:
1242 case X86::CR11:
1243 case X86::CR12:
1244 case X86::CR13:
1245 case X86::CR14:
1246 case X86::CR15:
1247 case X86::DR8:
1248 case X86::DR9:
1249 case X86::DR10:
1250 case X86::DR11:
1251 case X86::DR12:
1252 case X86::DR13:
1253 case X86::DR14:
1254 case X86::DR15:
1255 return true;
1256 }
1257 return false;
1258}
1259
1263
1265 return true;
1266
1267 unsigned Opcode = Desc.Opcode;
1268
1269 if (Opcode == X86::MOV32r0)
1270 return true;
1271
1272
1273
1275 return false;
1276
1277
1278
1279 switch (Opcode) {
1280 default:
1281 break;
1282 case X86::XSAVE:
1283 case X86::XSAVE64:
1284 case X86::XSAVEOPT:
1285 case X86::XSAVEOPT64:
1286 case X86::XSAVEC:
1287 case X86::XSAVEC64:
1288 case X86::XSAVES:
1289 case X86::XSAVES64:
1290 case X86::XRSTOR:
1291 case X86::XRSTOR64:
1292 case X86::XRSTORS:
1293 case X86::XRSTORS64:
1294 return false;
1295 }
1298}
1299
1300
1301
1303 return ((Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1304 (Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1305 (Reg >= X86::ZMM16 && Reg <= X86::ZMM31));
1306}
1307
1309 return (Reg == X86::SPL || Reg == X86::BPL || Reg == X86::SIL ||
1310 Reg == X86::DIL);
1311}
1312
1313
1317
1318
1322
1323
1325
1326 if (IndexReg)
1327 return true;
1328
1329
1330
1331
1332 switch (BaseReg.id()) {
1333 default:
1334
1335
1336 return In64BitMode && !BaseReg;
1337 case X86::ESP:
1338 case X86::RSP:
1339 case X86::R12:
1340 case X86::R12D:
1341 case X86::R20:
1342 case X86::R20D:
1343 case X86::R28:
1344 case X86::R28D:
1345 return true;
1346 }
1347}
1348
1349}
1350}
1351#endif
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
Describe properties that are true of each instruction in the target description file.
Wrapper class representing physical registers. Should be passed by value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
X86II - This namespace holds all of the target specific flags that instruction info tracks.
Definition X86BaseInfo.h:356
bool isKMergeMasked(uint64_t TSFlags)
Definition X86BaseInfo.h:1319
bool isPrefix(uint64_t TSFlags)
Definition X86BaseInfo.h:882
bool isZMMReg(MCRegister Reg)
Definition X86BaseInfo.h:1179
bool hasImm(uint64_t TSFlags)
Definition X86BaseInfo.h:897
bool hasNewDataDest(uint64_t TSFlags)
Definition X86BaseInfo.h:1001
static bool is32ExtendedReg(MCRegister Reg)
Definition X86BaseInfo.h:1302
TOF
Target Operand Flag enum.
Definition X86BaseInfo.h:358
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition X86BaseInfo.h:411
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition X86BaseInfo.h:391
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition X86BaseInfo.h:381
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition X86BaseInfo.h:468
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
Definition X86BaseInfo.h:367
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition X86BaseInfo.h:488
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition X86BaseInfo.h:450
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition X86BaseInfo.h:464
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition X86BaseInfo.h:432
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition X86BaseInfo.h:456
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition X86BaseInfo.h:438
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition X86BaseInfo.h:476
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition X86BaseInfo.h:376
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition X86BaseInfo.h:484
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition X86BaseInfo.h:396
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition X86BaseInfo.h:403
@ MO_NO_FLAG
MO_NO_FLAG - No flag for the operand.
Definition X86BaseInfo.h:363
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition X86BaseInfo.h:472
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition X86BaseInfo.h:460
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition X86BaseInfo.h:425
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition X86BaseInfo.h:480
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition X86BaseInfo.h:444
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition X86BaseInfo.h:371
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition X86BaseInfo.h:419
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition X86BaseInfo.h:387
bool isX86_64NonExtLowByteReg(MCRegister Reg)
Definition X86BaseInfo.h:1308
@ ExplicitOpPrefixShift
Force REX2/VEX/EVEX encoding.
Definition X86BaseInfo.h:861
@ MRM_E7
Definition X86BaseInfo.h:666
@ MRM0X
MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but ignore r/m.
Definition X86BaseInfo.h:618
@ MRM_C9
Definition X86BaseInfo.h:636
@ EVEX_ZShift
EVEX_Z - Set if this instruction has EVEX.Z field set.
Definition X86BaseInfo.h:843
@ RawFrm
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
Definition X86BaseInfo.h:502
@ MRM5m
Definition X86BaseInfo.h:581
@ VEX_LShift
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition X86BaseInfo.h:837
@ MRM_D5
Definition X86BaseInfo.h:648
@ VEX_L
Definition X86BaseInfo.h:838
@ MRM_C3
Definition X86BaseInfo.h:630
@ SpecialFP
SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
Definition X86BaseInfo.h:802
@ EVEX_RC
Definition X86BaseInfo.h:856
@ T_MAP7
Definition X86BaseInfo.h:756
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition X86BaseInfo.h:518
@ EVEX_KShift
EVEX_K - Set if this instruction requires masking.
Definition X86BaseInfo.h:840
@ OpSize16
Definition X86BaseInfo.h:701
@ EVEX_Z
Definition X86BaseInfo.h:844
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
Definition X86BaseInfo.h:825
@ REX_W
Definition X86BaseInfo.h:763
@ OpcodeShift
Opcode.
Definition X86BaseInfo.h:827
@ MRM_C6
Definition X86BaseInfo.h:633
@ MRM_DC
Definition X86BaseInfo.h:655
@ ExplicitREX2Prefix
For instructions that require REX2 prefix even if EGPR is not used.
Definition X86BaseInfo.h:863
@ OpMapMask
Definition X86BaseInfo.h:730
@ MRM_C2
Definition X86BaseInfo.h:629
@ MRM_F3
Definition X86BaseInfo.h:678
@ MRM_D2
Definition X86BaseInfo.h:645
@ EVEX_BShift
EVEX_B - Set if this instruction has EVEX.B field set.
Definition X86BaseInfo.h:849
@ EVEX_L2
Definition X86BaseInfo.h:847
@ MRMSrcMemCC
MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition X86BaseInfo.h:566
@ MRM5r
Definition X86BaseInfo.h:613
@ ImmShift
Definition X86BaseInfo.h:767
@ MRM_C7
Definition X86BaseInfo.h:634
@ MRM_DE
Definition X86BaseInfo.h:657
@ MRM_E6
Definition X86BaseInfo.h:665
@ MRM_D6
Definition X86BaseInfo.h:649
@ MRM1m
Definition X86BaseInfo.h:577
@ MRM_E9
Definition X86BaseInfo.h:668
@ NotFP
NotFP - The default, set for instructions that do not use FP registers.
Definition X86BaseInfo.h:784
@ T_MAP5
Definition X86BaseInfo.h:754
@ MRM_C5
Definition X86BaseInfo.h:632
@ MRM_C0
MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
Definition X86BaseInfo.h:627
@ MRM_E5
Definition X86BaseInfo.h:664
@ MRM_FA
Definition X86BaseInfo.h:685
@ MRM_E0
Definition X86BaseInfo.h:659
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition X86BaseInfo.h:514
@ OpPrefixShift
OpPrefix - There are several prefix bytes that are used as opcode extensions.
Definition X86BaseInfo.h:717
@ NOTRACK
Definition X86BaseInfo.h:859
@ Imm32PCRel
Definition X86BaseInfo.h:774
@ ImmMask
Definition X86BaseInfo.h:777
@ MRM_C8
Definition X86BaseInfo.h:635
@ MRM1X
Definition X86BaseInfo.h:619
@ MRM_CB
Definition X86BaseInfo.h:638
@ MRMDestMem4VOp3CC
MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destinat...
Definition X86BaseInfo.h:545
@ MRM_E1
Definition X86BaseInfo.h:660
@ FormMask
Definition X86BaseInfo.h:691
@ MRM4m
Definition X86BaseInfo.h:580
@ MRM_D1
Definition X86BaseInfo.h:644
@ MRM_D7
Definition X86BaseInfo.h:650
@ OB
OB - OneByte - Set if this instruction has a one byte opcode.
Definition X86BaseInfo.h:732
@ AddCCFrm
AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...
Definition X86BaseInfo.h:530
@ T_MAP4
MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
Definition X86BaseInfo.h:753
@ PrefixByte
PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.
Definition X86BaseInfo.h:533
@ MRM_EC
Definition X86BaseInfo.h:671
@ Imm32
Definition X86BaseInfo.h:773
@ MRM_F6
Definition X86BaseInfo.h:681
@ MRM_F9
Definition X86BaseInfo.h:684
@ MRMr0
Instructions operate on a register Reg/Opcode operand not the r/m field.
Definition X86BaseInfo.h:547
@ AdSize64
Definition X86BaseInfo.h:712
@ MRM7r
Definition X86BaseInfo.h:615
@ TwoConditionalOps_Shift
Definition X86BaseInfo.h:874
@ EVEX_B
Definition X86BaseInfo.h:850
@ MRM_CF
Definition X86BaseInfo.h:642
@ MRM2r
Definition X86BaseInfo.h:610
@ AdSizeMask
Definition X86BaseInfo.h:708
@ XD
Definition X86BaseInfo.h:725
@ MRM_D9
Definition X86BaseInfo.h:652
@ MRM_DD
Definition X86BaseInfo.h:656
@ MRMXm
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition X86BaseInfo.h:573
@ OneArgFPRW
OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a result back to ST(0).
Definition X86BaseInfo.h:791
@ MRM0r
MRM0r-MRM7r - Instructions that operate on a register r/m operand and use reg field to hold extended ...
Definition X86BaseInfo.h:608
@ MRM_F7
Definition X86BaseInfo.h:682
@ MRMDestMemFSIB
MRMDestMem - But force to use the SIB field.
Definition X86BaseInfo.h:551
@ MRM_CA
Definition X86BaseInfo.h:637
@ AddRegFrm
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Definition X86BaseInfo.h:505
@ MRM_E8
Definition X86BaseInfo.h:667
@ ExplicitEVEXPrefix
For instructions that are promoted to EVEX space for EGPR.
Definition X86BaseInfo.h:868
@ MRM_EB
Definition X86BaseInfo.h:670
@ VEX
VEX - encoding using 0xC4/0xC5.
Definition X86BaseInfo.h:818
@ RawFrmImm8
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition X86BaseInfo.h:522
@ OpSizeShift
OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
Definition X86BaseInfo.h:698
@ TB
TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...
Definition X86BaseInfo.h:735
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition X86BaseInfo.h:820
@ MRMXr
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition X86BaseInfo.h:605
@ MRM_ED
Definition X86BaseInfo.h:672
@ LOCKShift
Lock prefix.
Definition X86BaseInfo.h:804
@ MRM_FB
Definition X86BaseInfo.h:686
@ CD8_Scale_Mask
Definition X86BaseInfo.h:853
@ OpSize32
Definition X86BaseInfo.h:702
@ MRMSrcMem4VOp3
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition X86BaseInfo.h:560
@ REP
Definition X86BaseInfo.h:808
@ EVEX_L2Shift
EVEX_L2 - Set if this instruction has EVEX.L' field set.
Definition X86BaseInfo.h:846
@ MRM_E2
Definition X86BaseInfo.h:661
@ MRM_CD
Definition X86BaseInfo.h:640
@ MRM7m
Definition X86BaseInfo.h:583
@ XOP8
XOP8 - Prefix to include use of imm byte.
Definition X86BaseInfo.h:740
@ Imm8Reg
Definition X86BaseInfo.h:770
@ MRM_D8
Definition X86BaseInfo.h:651
@ ZeroArgFP
ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0.
Definition X86BaseInfo.h:786
@ MRM_CE
Definition X86BaseInfo.h:641
@ LOCK
Definition X86BaseInfo.h:805
@ REXShift
REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
Definition X86BaseInfo.h:762
@ MRMDestRegCC
MRMDestRegCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition X86BaseInfo.h:537
@ MRM7X
Definition X86BaseInfo.h:625
@ AdSizeShift
AsSize - AdSizeX implies this instruction determines its need of 0x67 prefix from a normal ModRM memo...
Definition X86BaseInfo.h:707
@ MRM_F5
Definition X86BaseInfo.h:680
@ REPShift
REP prefix.
Definition X86BaseInfo.h:807
@ VEX_4V
Definition X86BaseInfo.h:832
@ MRM6X
Definition X86BaseInfo.h:624
@ MRM3X
Definition X86BaseInfo.h:621
@ PD
PD - Prefix code for packed double precision vector floating point operations performed in the SSE re...
Definition X86BaseInfo.h:721
@ MRMDestMem
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition X86BaseInfo.h:554
@ MRM_FD
Definition X86BaseInfo.h:688
@ MRM_CC
Definition X86BaseInfo.h:639
@ MRM2X
Definition X86BaseInfo.h:620
@ EncodingShift
Encoding.
Definition X86BaseInfo.h:813
@ OneArgFP
OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst.
Definition X86BaseInfo.h:788
@ MRMSrcMemFSIB
MRMSrcMem - But force to use the SIB field.
Definition X86BaseInfo.h:549
@ CompareFP
CompareFP - 2 arg FP instructions which implicitly read ST(0) and an explicit argument,...
Definition X86BaseInfo.h:798
@ MRM_F0
Definition X86BaseInfo.h:675
@ NoTrackShift
NOTRACK prefix.
Definition X86BaseInfo.h:858
@ MRM_DB
Definition X86BaseInfo.h:654
@ ExplicitVEXPrefix
For instructions that use VEX encoding only when {vex}, {vex2} or {vex3} is present.
Definition X86BaseInfo.h:866
@ EVEX_RCShift
Explicitly specified rounding control.
Definition X86BaseInfo.h:855
@ Imm8
Definition X86BaseInfo.h:768
@ OpSizeMask
Definition X86BaseInfo.h:699
@ MRMSrcRegOp4
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition X86BaseInfo.h:595
@ MRM4X
Definition X86BaseInfo.h:622
@ OpSizeFixed
Definition X86BaseInfo.h:700
@ MRMXrCC
MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition X86BaseInfo.h:602
@ T8
T8, TA - Prefix after the 0x0F prefix.
Definition X86BaseInfo.h:737
@ MRM_D0
Definition X86BaseInfo.h:643
@ MRMDestMemCC
MRMDestMemCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition X86BaseInfo.h:541
@ XOP9
XOP9 - Prefix to exclude use of imm byte.
Definition X86BaseInfo.h:742
@ MRMXmCC
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition X86BaseInfo.h:570
@ MRM_F8
Definition X86BaseInfo.h:683
@ RawFrmImm16
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition X86BaseInfo.h:527
@ MRM2m
Definition X86BaseInfo.h:578
@ AdSize16
Definition X86BaseInfo.h:710
@ MRM5X
Definition X86BaseInfo.h:623
@ Imm8PCRel
Definition X86BaseInfo.h:769
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition X86BaseInfo.h:589
@ MRM_DA
Definition X86BaseInfo.h:653
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition X86BaseInfo.h:511
@ MRM_F4
Definition X86BaseInfo.h:679
@ MRM_E3
Definition X86BaseInfo.h:662
@ MRMDestReg
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition X86BaseInfo.h:586
@ EVEX_K
Definition X86BaseInfo.h:841
@ MRMSrcMem
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition X86BaseInfo.h:557
@ MRMSrcMemOp4
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition X86BaseInfo.h:563
@ Pseudo
PseudoFrm - This represents an instruction that is a pseudo instruction or one that has not been impl...
Definition X86BaseInfo.h:499
@ Imm16
Definition X86BaseInfo.h:771
@ MRM_FC
Definition X86BaseInfo.h:687
@ VEX_4VShift
VEX_4V - Used to specify an additional AVX/SSE register.
Definition X86BaseInfo.h:831
@ CD8_Scale_Shift
The scaling factor for the AVX512's 8-bit compressed displacement.
Definition X86BaseInfo.h:852
@ Imm64
Definition X86BaseInfo.h:776
@ MRMSrcRegCC
MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition X86BaseInfo.h:598
@ EVEX_NF
Definition X86BaseInfo.h:872
@ SSEDomainShift
Execution domain for SSE instructions.
Definition X86BaseInfo.h:811
@ CondMovFP
CondMovFP - "2 operand" floating point conditional move instructions.
Definition X86BaseInfo.h:800
@ MRM0m
MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use reg field to hold extended op...
Definition X86BaseInfo.h:576
@ MRM_FF
Definition X86BaseInfo.h:690
@ MRM_DF
Definition X86BaseInfo.h:658
@ ThreeDNow
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!
Definition X86BaseInfo.h:751
@ MRM_D3
Definition X86BaseInfo.h:646
@ EVEX_U
Definition X86BaseInfo.h:878
@ TA
Definition X86BaseInfo.h:738
@ MRM_FE
Definition X86BaseInfo.h:689
@ EncodingMask
Definition X86BaseInfo.h:814
@ MRM_F1
Definition X86BaseInfo.h:676
@ XS
XS, XD - These prefix codes are for single and double precision scalar floating point operations perf...
Definition X86BaseInfo.h:724
@ MRM_F2
Definition X86BaseInfo.h:677
@ FPTypeMask
Definition X86BaseInfo.h:782
@ T_MAP6
Definition X86BaseInfo.h:755
@ Imm32S
Definition X86BaseInfo.h:775
@ MRM_C1
Definition X86BaseInfo.h:628
@ ExplicitOpPrefixMask
Definition X86BaseInfo.h:869
@ MRM_EE
Definition X86BaseInfo.h:673
@ FPTypeShift
FP Instruction Classification... Zero is non-fp instruction.
Definition X86BaseInfo.h:781
@ AdSize32
Definition X86BaseInfo.h:711
@ TwoConditionalOps
Definition X86BaseInfo.h:875
@ MRM3r
Definition X86BaseInfo.h:611
@ XOPA
XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
Definition X86BaseInfo.h:744
@ MRM3m
Definition X86BaseInfo.h:579
@ MRM_EF
Definition X86BaseInfo.h:674
@ MRM_D4
Definition X86BaseInfo.h:647
@ MRM_C4
Definition X86BaseInfo.h:631
@ MRMSrcReg4VOp3
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition X86BaseInfo.h:592
@ MRM_E4
Definition X86BaseInfo.h:663
@ OpMapShift
OpMap - This field determines which opcode map this instruction belongs to.
Definition X86BaseInfo.h:729
@ Imm16PCRel
Definition X86BaseInfo.h:772
@ MRM_EA
Definition X86BaseInfo.h:669
@ MRM6m
Definition X86BaseInfo.h:582
@ MRM4r
Definition X86BaseInfo.h:612
@ LEGACY
LEGACY - encoding using REX/REX2 or w/o opcode prefix.
Definition X86BaseInfo.h:816
@ EVEX_UShift
Definition X86BaseInfo.h:877
@ AdSizeX
Definition X86BaseInfo.h:709
@ MRM1r
Definition X86BaseInfo.h:609
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition X86BaseInfo.h:508
@ TwoArgFP
TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an explicit argument,...
Definition X86BaseInfo.h:795
@ EVEX_NFShift
EVEX_NF - Set if this instruction has EVEX.NF field set.
Definition X86BaseInfo.h:871
@ OpPrefixMask
Definition X86BaseInfo.h:718
@ MRM6r
Definition X86BaseInfo.h:614
bool canUseApxExtendedReg(const MCInstrDesc &Desc)
Definition X86BaseInfo.h:1260
bool isPseudo(uint64_t TSFlags)
Definition X86BaseInfo.h:887
bool isImmPCRel(uint64_t TSFlags)
Definition X86BaseInfo.h:923
bool isXMMReg(MCRegister Reg)
Definition X86BaseInfo.h:1159
unsigned getSizeOfImm(uint64_t TSFlags)
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
Definition X86BaseInfo.h:901
bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode)
Definition X86BaseInfo.h:1324
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition X86BaseInfo.h:893
bool isKMasked(uint64_t TSFlags)
Definition X86BaseInfo.h:1314
bool isYMMReg(MCRegister Reg)
Definition X86BaseInfo.h:1169
int getMemoryOperandNo(uint64_t TSFlags)
Definition X86BaseInfo.h:1011
bool isX86_64ExtendedReg(MCRegister Reg)
Definition X86BaseInfo.h:1193
bool isApxExtendedReg(MCRegister Reg)
Definition X86BaseInfo.h:1186
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition X86BaseInfo.h:968
bool isImmSigned(uint64_t TSFlags)
Definition X86BaseInfo.h:943
Define some predicates that are used for node matching.
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
Definition X86BaseInfo.h:126
OperandType
Definition X86BaseInfo.h:69
@ OPERAND_COND_CODE
Definition X86BaseInfo.h:72
@ OPERAND_ROUNDING_CONTROL
Definition X86BaseInfo.h:71
CondCode
Definition X86BaseInfo.h:77
@ LAST_VALID_COND
Definition X86BaseInfo.h:94
@ COND_GE
Definition X86BaseInfo.h:91
@ COND_E_AND_NP
Definition X86BaseInfo.h:101
@ COND_NP
Definition X86BaseInfo.h:89
@ COND_NS
Definition X86BaseInfo.h:87
@ COND_E
Definition X86BaseInfo.h:82
@ COND_G
Definition X86BaseInfo.h:93
@ COND_NE_OR_P
Definition X86BaseInfo.h:100
@ COND_O
Definition X86BaseInfo.h:78
@ COND_BE
Definition X86BaseInfo.h:84
@ COND_INVALID
Definition X86BaseInfo.h:102
@ COND_B
Definition X86BaseInfo.h:80
@ COND_NE
Definition X86BaseInfo.h:83
@ COND_NO
Definition X86BaseInfo.h:79
@ COND_A
Definition X86BaseInfo.h:85
@ COND_LE
Definition X86BaseInfo.h:92
@ COND_S
Definition X86BaseInfo.h:86
@ COND_L
Definition X86BaseInfo.h:90
@ COND_AE
Definition X86BaseInfo.h:81
@ COND_P
Definition X86BaseInfo.h:88
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
Definition X86BaseInfo.h:309
@ AlignBranchJmp
Definition X86BaseInfo.h:313
@ AlignBranchIndirect
Definition X86BaseInfo.h:316
@ AlignBranchJcc
Definition X86BaseInfo.h:312
@ AlignBranchCall
Definition X86BaseInfo.h:314
@ AlignBranchRet
Definition X86BaseInfo.h:315
@ AlignBranchNone
Definition X86BaseInfo.h:310
@ AlignBranchFused
Definition X86BaseInfo.h:311
@ AddrBaseReg
Definition X86BaseInfo.h:29
@ AddrScaleAmt
Definition X86BaseInfo.h:30
@ AddrSegmentReg
Definition X86BaseInfo.h:34
@ AddrDisp
Definition X86BaseInfo.h:32
@ AddrIndexReg
Definition X86BaseInfo.h:31
@ AddrNumOperands
Definition X86BaseInfo.h:36
STATIC_ROUNDING
AVX512 static rounding constants.
Definition X86BaseInfo.h:41
@ TO_POS_INF
Definition X86BaseInfo.h:44
@ TO_NEAREST_INT
Definition X86BaseInfo.h:42
@ NO_EXC
Definition X86BaseInfo.h:47
@ CUR_DIRECTION
Definition X86BaseInfo.h:46
@ TO_ZERO
Definition X86BaseInfo.h:45
@ TO_NEG_INF
Definition X86BaseInfo.h:43
EncodingOfSegmentOverridePrefix
Defines the encoding values for segment override prefix.
Definition X86BaseInfo.h:320
@ GS_Encoding
Definition X86BaseInfo.h:325
@ ES_Encoding
Definition X86BaseInfo.h:323
@ CS_Encoding
Definition X86BaseInfo.h:321
@ SS_Encoding
Definition X86BaseInfo.h:326
@ FS_Encoding
Definition X86BaseInfo.h:324
@ DS_Encoding
Definition X86BaseInfo.h:322
SecondMacroFusionInstKind
Definition X86BaseInfo.h:116
@ Invalid
Definition X86BaseInfo.h:120
@ SPO
Definition X86BaseInfo.h:119
@ AB
Definition X86BaseInfo.h:117
@ ELG
Definition X86BaseInfo.h:118
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(MCRegister Reg)
Given a segment register, return the encoding of the segment override prefix for it.
Definition X86BaseInfo.h:332
FirstMacroFusionInstKind
Definition X86BaseInfo.h:107
@ Test
Definition X86BaseInfo.h:108
@ IncDec
Definition X86BaseInfo.h:112
@ Invalid
Definition X86BaseInfo.h:113
@ And
Definition X86BaseInfo.h:110
@ Cmp
Definition X86BaseInfo.h:109
@ AddSub
Definition X86BaseInfo.h:111
IPREFIXES
The constants to describe instr prefixes if there are.
Definition X86BaseInfo.h:51
@ IP_HAS_LOCK
Definition X86BaseInfo.h:57
@ IP_HAS_NOTRACK
Definition X86BaseInfo.h:58
@ IP_USE_VEX3
Definition X86BaseInfo.h:63
@ IP_USE_DISP8
Definition X86BaseInfo.h:65
@ IP_USE_EVEX
Definition X86BaseInfo.h:64
@ IP_HAS_AD_SIZE
Definition X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition X86BaseInfo.h:56
@ IP_USE_REX
Definition X86BaseInfo.h:59
@ IP_USE_VEX2
Definition X86BaseInfo.h:62
@ IP_USE_REX2
Definition X86BaseInfo.h:60
@ IP_USE_DISP32
Definition X86BaseInfo.h:66
@ IP_HAS_OP_SIZE
Definition X86BaseInfo.h:53
@ IP_NO_PREFIX
Definition X86BaseInfo.h:52
@ IP_HAS_REPEAT_NE
Definition X86BaseInfo.h:55
@ IP_USE_VEX
Definition X86BaseInfo.h:61
SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion(X86::CondCode CC)
Definition X86BaseInfo.h:258
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
Definition X86BaseInfo.h:290
This is an optimization pass for GlobalISel generic memory operations.