LLVM: llvm::X86 Namespace Reference (original) (raw)
Define some predicates that are used for node matching. More...
| Functions | |
|---|---|
| LLVM_ABI CPUKind | parseArchX86 (StringRef CPU, bool Only64Bit=false) |
| Parse CPU string into a CPUKind. | |
| LLVM_ABI CPUKind | parseTuneCPU (StringRef CPU, bool Only64Bit=false) |
| LLVM_ABI void | fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false) |
| Provide a list of valid CPU names. | |
| LLVM_ABI void | fillValidTuneCPUList (SmallVectorImpl< StringRef > &Values, bool Only64Bit=false) |
| Provide a list of valid -mtune names. | |
| LLVM_ABI ProcessorFeatures | getKeyFeature (CPUKind Kind) |
| Get the key feature prioritizing target multiversioning. | |
| LLVM_ABI void | getFeaturesForCPU (StringRef CPU, SmallVectorImpl< StringRef > &Features, bool NeedPlus=false) |
| Fill in the features that CPU supports into Features. | |
| LLVM_ABI void | updateImpliedFeatures (StringRef Feature, bool Enabled, StringMap< bool > &Features) |
| Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature. | |
| LLVM_ABI char | getCPUDispatchMangling (StringRef Name) |
| LLVM_ABI bool | validateCPUSpecificCPUDispatch (StringRef Name) |
| LLVM_ABI std::array< uint32_t, 4 > | getCpuSupportsMask (ArrayRef< StringRef > FeatureStrs) |
| LLVM_ABI unsigned | getFeaturePriority (ProcessorFeatures Feat) |
| FirstMacroFusionInstKind | classifyFirstOpcodeInMacroFusion (unsigned Opcode) |
| SecondMacroFusionInstKind | classifySecondCondCodeInMacroFusion (X86::CondCode CC) |
| bool | isMacroFused (FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind) |
| EncodingOfSegmentOverridePrefix | getSegmentOverridePrefixForReg (MCRegister Reg) |
| Given a segment register, return the encoding of the segment override prefix for it. | |
| bool | optimizeInstFromVEX3ToVEX2 (MCInst &MI, const MCInstrDesc &Desc) |
| bool | optimizeShiftRotateWithImmediateOne (MCInst &MI) |
| bool | optimizeVPCMPWithImmediateOneOrSix (MCInst &MI) |
| bool | optimizeMOVSX (MCInst &MI) |
| bool | optimizeINCDEC (MCInst &MI, bool In64BitMode) |
| bool | optimizeMOV (MCInst &MI, bool In64BitMode) |
| Simplify things like MOV32rm to MOV32o32a. | |
| bool | optimizeToFixedRegisterOrShortImmediateForm (MCInst &MI) |
| unsigned | getOpcodeForShortImmediateForm (unsigned Opcode) |
| unsigned | getOpcodeForLongImmediateForm (unsigned Opcode) |
| std::pair< CondCode, bool > | getX86ConditionCode (CmpInst::Predicate Predicate) |
| Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code. | |
| unsigned | getCMovOpcode (unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false) |
| Return a cmov opcode for the given register size in bytes, and operand type. | |
| int | getCondSrcNoFromDesc (const MCInstrDesc &MCID) |
| Return the source operand # for condition code by MCID. | |
| CondCode | getCondFromMI (const MachineInstr &MI) |
| Return the condition code of the instruction. | |
| CondCode | getCondFromBranch (const MachineInstr &MI) |
| CondCode | getCondFromSETCC (const MachineInstr &MI) |
| CondCode | getCondFromCMov (const MachineInstr &MI) |
| CondCode | getCondFromCFCMov (const MachineInstr &MI) |
| CondCode | getCondFromCCMP (const MachineInstr &MI) |
| int | getCCMPCondFlagsFromCondCode (CondCode CC) |
| unsigned | getNFVariant (unsigned Opc) |
| unsigned | getNonNDVariant (unsigned Opc) |
| CondCode | GetOppositeBranchCondition (CondCode CC) |
| GetOppositeBranchCondition - Return the inverse of the specified cond, e.g. | |
| unsigned | getVPCMPImmForCond (ISD::CondCode CC) |
| Get the VPCMP immediate for the given condition. | |
| unsigned | getSwappedVPCMPImm (unsigned Imm) |
| Get the VPCMP immediate if the opcodes are swapped. | |
| unsigned | getSwappedVPCOMImm (unsigned Imm) |
| Get the VPCOM immediate if the opcodes are swapped. | |
| unsigned | getSwappedVCMPImm (unsigned Imm) |
| Get the VCMP immediate if the opcodes are swapped. | |
| unsigned | getVectorRegisterWidth (const MCOperandInfo &Info) |
| Get the width of the vector register operand. | |
| bool | isX87Instruction (MachineInstr &MI) |
| Check if the instruction is X87 instruction. | |
| int | getFirstAddrOperandIdx (const MachineInstr &MI) |
| Return the index of the instruction's first address operand, if it has a memory reference, or -1 if it has none. | |
| const Constant * | getConstantFromPool (const MachineInstr &MI, unsigned OpNo) |
| Find any constant pool entry associated with a specific instruction operand. | |
| bool | isConstantSplat (SDValue Op, APInt &SplatVal, bool AllowPartialUndefs=true) |
| If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal. | |
| int | getRoundingModeX86 (unsigned RM) |
| Convert LLVM rounding mode to X86 rounding mode. | |
| bool | isZeroNode (SDValue Elt) |
| Returns true if Elt is a constant zero or floating point constant +0.0. | |
| bool | isOffsetSuitableForCodeModel (int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement) |
| Returns true of the given offset can be fit into displacement field of the instruction. | |
| bool | isCalleePop (CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO) |
| Determines whether the callee is required to pop its own arguments. | |
| bool | mayFoldLoad (SDValue Op, const X86Subtarget &Subtarget, bool AssumeSingleUse=false) |
| Check if Op is a load operation that could be folded into some other x86 instruction as a memory operand. | |
| bool | mayFoldLoadIntoBroadcastFromMem (SDValue Op, MVT EltVT, const X86Subtarget &Subtarget, bool AssumeSingleUse=false) |
| Check if Op is a load operation that could be folded into a vector splat instruction as a memory operand. | |
| bool | mayFoldIntoStore (SDValue Op) |
| Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory operand. | |
| bool | mayFoldIntoZeroExtend (SDValue Op) |
| Check if Op is an operation that could be folded into a zero extend x86 instruction. | |
| bool | isExtendedSwiftAsyncFrameSupported (const X86Subtarget &Subtarget, const MachineFunction &MF) |
| True if the target supports the extended frame for async Swift functions. | |
| FastISel * | createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) |
Define some predicates that are used for node matching.
◆ Specifier
◆ anonymous enum
| Enumerator |
|---|
| AddrBaseReg |
| AddrScaleAmt |
| AddrIndexReg |
| AddrDisp |
| AddrSegmentReg |
| AddrNumOperands |
Definition at line 28 of file X86BaseInfo.h.
◆ anonymous enum
◆ anonymous enum
◆ anonymous enum
| Enumerator |
|---|
| S_None |
| S_COFF_SECREL |
| S_ABS8 |
| S_DTPOFF |
| S_DTPREL |
| S_GOT |
| S_GOTENT |
| S_GOTNTPOFF |
| S_GOTOFF |
| S_GOTPCREL |
| S_GOTPCREL_NORELAX |
| S_GOTREL |
| S_GOTTPOFF |
| S_INDNTPOFF |
| S_NTPOFF |
| S_PCREL |
| S_PLT |
| S_PLTOFF |
| S_SIZE |
| S_TLSCALL |
| S_TLSDESC |
| S_TLSGD |
| S_TLSLD |
| S_TLSLDM |
| S_TLVP |
| S_TLVPPAGE |
| S_TLVPPAGEOFF |
| S_TPOFF |
Definition at line 70 of file X86MCAsmInfo.h.
◆ AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
| Enumerator |
|---|
| AlignBranchNone |
| AlignBranchFused |
| AlignBranchJcc |
| AlignBranchJmp |
| AlignBranchCall |
| AlignBranchRet |
| AlignBranchIndirect |
Definition at line 309 of file X86BaseInfo.h.
◆ AsmComments
| Enumerator |
|---|
| AC_EVEX_2_LEGACY |
| AC_EVEX_2_VEX |
| AC_EVEX_2_EVEX |
Definition at line 37 of file X86InstrInfo.h.
◆ CondCode
| Enumerator |
|---|
| COND_O |
| COND_NO |
| COND_B |
| COND_AE |
| COND_E |
| COND_NE |
| COND_BE |
| COND_A |
| COND_S |
| COND_NS |
| COND_P |
| COND_NP |
| COND_L |
| COND_GE |
| COND_LE |
| COND_G |
| LAST_VALID_COND |
| COND_NE_OR_P |
| COND_E_AND_NP |
| COND_INVALID |
Definition at line 77 of file X86BaseInfo.h.
◆ CPUKind
| Enumerator |
|---|
| CK_None |
| CK_i386 |
| CK_i486 |
| CK_WinChipC6 |
| CK_WinChip2 |
| CK_C3 |
| CK_i586 |
| CK_Pentium |
| CK_PentiumMMX |
| CK_PentiumPro |
| CK_i686 |
| CK_Pentium2 |
| CK_Pentium3 |
| CK_PentiumM |
| CK_C3_2 |
| CK_Yonah |
| CK_Pentium4 |
| CK_Prescott |
| CK_Nocona |
| CK_Core2 |
| CK_Penryn |
| CK_Bonnell |
| CK_Silvermont |
| CK_Goldmont |
| CK_GoldmontPlus |
| CK_Tremont |
| CK_Gracemont |
| CK_Nehalem |
| CK_Westmere |
| CK_SandyBridge |
| CK_IvyBridge |
| CK_Haswell |
| CK_Broadwell |
| CK_SkylakeClient |
| CK_SkylakeServer |
| CK_Cascadelake |
| CK_Cooperlake |
| CK_Cannonlake |
| CK_IcelakeClient |
| CK_Rocketlake |
| CK_IcelakeServer |
| CK_Tigerlake |
| CK_SapphireRapids |
| CK_Alderlake |
| CK_Raptorlake |
| CK_Meteorlake |
| CK_Arrowlake |
| CK_ArrowlakeS |
| CK_Lunarlake |
| CK_Pantherlake |
| CK_Wildcatlake |
| CK_Novalake |
| CK_Sierraforest |
| CK_Grandridge |
| CK_Graniterapids |
| CK_GraniterapidsD |
| CK_Emeraldrapids |
| CK_Clearwaterforest |
| CK_Diamondrapids |
| CK_KNL |
| CK_KNM |
| CK_Lakemont |
| CK_K6 |
| CK_K6_2 |
| CK_K6_3 |
| CK_Athlon |
| CK_AthlonXP |
| CK_K8 |
| CK_K8SSE3 |
| CK_AMDFAM10 |
| CK_BTVER1 |
| CK_BTVER2 |
| CK_BDVER1 |
| CK_BDVER2 |
| CK_BDVER3 |
| CK_BDVER4 |
| CK_ZNVER1 |
| CK_ZNVER2 |
| CK_ZNVER3 |
| CK_ZNVER4 |
| CK_ZNVER5 |
| CK_x86_64 |
| CK_x86_64_v2 |
| CK_x86_64_v3 |
| CK_x86_64_v4 |
| CK_Geode |
Definition at line 67 of file X86TargetParser.h.
◆ EncodingOfSegmentOverridePrefix
Defines the encoding values for segment override prefix.
| Enumerator |
|---|
| CS_Encoding |
| DS_Encoding |
| ES_Encoding |
| FS_Encoding |
| GS_Encoding |
| SS_Encoding |
Definition at line 320 of file X86BaseInfo.h.
◆ FirstMacroFusionInstKind
| Enumerator |
|---|
| Test |
| Cmp |
| And |
| AddSub |
| IncDec |
| Invalid |
Definition at line 107 of file X86BaseInfo.h.
◆ Fixups
| Enumerator |
|---|
| reloc_riprel_4byte |
| reloc_riprel_4byte_movq_load |
| reloc_riprel_4byte_movq_load_rex2 |
| reloc_riprel_4byte_relax |
| reloc_riprel_4byte_relax_rex |
| reloc_riprel_4byte_relax_rex2 |
| reloc_riprel_4byte_relax_evex |
| reloc_signed_4byte |
| reloc_signed_4byte_relax |
| reloc_global_offset_table |
| reloc_branch_4byte_pcrel |
| LastTargetFixupKind |
| NumTargetFixupKinds |
Definition at line 16 of file X86FixupKinds.h.
◆ IPREFIXES
The constants to describe instr prefixes if there are.
| Enumerator |
|---|
| IP_NO_PREFIX |
| IP_HAS_OP_SIZE |
| IP_HAS_AD_SIZE |
| IP_HAS_REPEAT_NE |
| IP_HAS_REPEAT |
| IP_HAS_LOCK |
| IP_HAS_NOTRACK |
| IP_USE_REX |
| IP_USE_REX2 |
| IP_USE_VEX |
| IP_USE_VEX2 |
| IP_USE_VEX3 |
| IP_USE_EVEX |
| IP_USE_DISP8 |
| IP_USE_DISP32 |
Definition at line 51 of file X86BaseInfo.h.
◆ OperandType
| Enumerator |
|---|
| OPERAND_ROUNDING_CONTROL |
| OPERAND_COND_CODE |
Definition at line 69 of file X86BaseInfo.h.
◆ ProcessorFeatures
◆ ProcessorSubtypes
◆ ProcessorTypes
◆ ProcessorVendors
◆ RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
These values are same as corresponding constants for rounding mode used in glibc.
| Enumerator |
|---|
| rmInvalid |
| rmToNearest |
| rmDownward |
| rmUpward |
| rmTowardZero |
| rmMask |
Definition at line 1010 of file X86ISelLowering.h.
◆ SecondMacroFusionInstKind
◆ STATIC_ROUNDING
AVX512 static rounding constants.
These need to match the values in avx512fintrin.h.
| Enumerator |
|---|
| TO_NEAREST_INT |
| TO_NEG_INF |
| TO_POS_INF |
| TO_ZERO |
| CUR_DIRECTION |
| NO_EXC |
Definition at line 41 of file X86BaseInfo.h.
◆ classifyFirstOpcodeInMacroFusion()
| FirstMacroFusionInstKind llvm::X86::classifyFirstOpcodeInMacroFusion ( unsigned Opcode) | inline |
|---|
◆ classifySecondCondCodeInMacroFusion()
| SecondMacroFusionInstKind llvm::X86::classifySecondCondCodeInMacroFusion ( X86::CondCode CC) | inline |
|---|
Returns
the type of the second instruction in macro-fusion.
Definition at line 258 of file X86BaseInfo.h.
References AB, COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_INVALID, COND_L, COND_LE, COND_NE, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, ELG, Invalid, and SPO.
Referenced by classifySecond().
◆ createFastISel()
◆ fillValidCPUArchList()
◆ fillValidTuneCPUList()
◆ getCCMPCondFlagsFromCondCode()
| int llvm::X86::getCCMPCondFlagsFromCondCode | ( | X86::CondCode | CC | ) |
|---|
Definition at line 3217 of file X86InstrInfo.cpp.
References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, and llvm_unreachable.
Referenced by combineAndOrForCcmpCtest().
◆ getCMovOpcode()
◆ getCondFromBranch()
◆ getCondFromCCMP()
◆ getCondFromCFCMov()
◆ getCondFromCMov()
◆ getCondFromMI()
◆ getCondFromSETCC()
◆ getCondSrcNoFromDesc()
Return the source operand # for condition code by [MCID](namespacellvm%5F1%5F1MCID.html).
If the instruction doesn't have a condition code, return -1.
Definition at line 3170 of file X86InstrInfo.cpp.
Referenced by getCondFromMI().
◆ getConstantFromPool()
Find any constant pool entry associated with a specific instruction operand.
Definition at line 3671 of file X86InstrInfo.cpp.
References AddrDisp, AddrIndexReg, AddrNumOperands, assert(), llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineOperand::getIndex(), llvm::MachineOperand::getOffset(), llvm::MachineOperand::isCPI(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), MI, and llvm::MachineConstantPoolEntry::Val.
Referenced by addConstantComments(), printBroadcast(), printExtend(), and printZeroUpperMove().
◆ getCPUDispatchMangling()
◆ getCpuSupportsMask()
◆ getFeaturePriority()
◆ getFeaturesForCPU()
◆ getFirstAddrOperandIdx()
Return the index of the instruction's first address operand, if it has a memory reference, or -1 if it has none.
Unlike X86II::getMemoryOperandNo(), this also works for both pseudo instructions (e.g., TCRETURNmi) as well as real instructions (e.g., JMP64m).
Definition at line 3620 of file X86InstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, AddrNumOperands, assert(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), I, llvm::X86II::isPseudo(), MI, llvm::none_of(), and llvm::MCOI::OPERAND_MEMORY.
Referenced by CompressEVEXImpl().
◆ getKeyFeature()
| ProcessorFeatures llvm::X86::getKeyFeature | ( | X86::CPUKind | Kind | ) |
|---|
◆ getNFVariant()
◆ getNonNDVariant()
◆ getOpcodeForLongImmediateForm()
◆ getOpcodeForShortImmediateForm()
◆ GetOppositeBranchCondition()
| X86::CondCode llvm::X86::GetOppositeBranchCondition | ( | X86::CondCode | CC | ) |
|---|
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
Return the inverse of the specified condition, e.g.
turning COND_E to COND_NE.
Definition at line 3311 of file X86InstrInfo.cpp.
References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_E_AND_NP, COND_G, COND_GE, COND_L, COND_LE, COND_NE, COND_NE_OR_P, COND_NO, COND_NP, COND_NS, COND_O, COND_P, COND_S, and llvm_unreachable.
Referenced by checkBoolTestSetCCCombine(), combineAndOrForCcmpCtest(), combineCMov(), combineOr(), combineSubSetcc(), combineX86SubCmpForFlags(), llvm::X86InstrInfo::commuteInstructionImpl(), createPHIsForCMOVsInSinkBB(), and foldXor1SetCC().
◆ getRoundingModeX86()
| int llvm::X86::getRoundingModeX86 | ( | unsigned | RM | ) |
|---|
◆ getSegmentOverridePrefixForReg()
| EncodingOfSegmentOverridePrefix llvm::X86::getSegmentOverridePrefixForReg ( MCRegister Reg) | inline |
|---|
◆ getSwappedVCMPImm()
◆ getSwappedVPCMPImm()
◆ getSwappedVPCOMImm()
◆ getVectorRegisterWidth()
◆ getVPCMPImmForCond()
Get the VPCMP immediate for the given condition.
Definition at line 3489 of file X86InstrInfo.cpp.
References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
◆ getX86ConditionCode()
Return a pair of condition code for the given predicate and whether the instruction operands should be swaped to match the condition code.
Definition at line 3384 of file X86InstrInfo.cpp.
References COND_A, COND_AE, COND_B, COND_BE, COND_E, COND_G, COND_GE, COND_INVALID, COND_L, COND_LE, COND_NE, COND_NP, COND_P, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, and llvm::CmpInst::ICMP_ULT.
◆ isCalleePop()
◆ isConstantSplat()
If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal.
If we have undef bits that don't cover an entire element, we treat these as zero if AllowPartialUndefs is set, else we fail and return false.
Definition at line 5358 of file X86ISelLowering.cpp.
References getTargetConstantBitsFromNode(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by combineAndMaskToShift(), combineFunnelShift(), combineVPMADD52LH(), LowerFunnelShift(), LowerRotate(), LowerShift(), and LowerShiftByScalarImmediate().
◆ isExtendedSwiftAsyncFrameSupported()
◆ isMacroFused()
| bool llvm::X86::isMacroFused ( FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind ) | inline |
|---|
◆ isOffsetSuitableForCodeModel()
◆ isX87Instruction()
◆ isZeroNode()
Returns true if Elt is a constant zero or floating point constant +0.0.
Returns true if Elt is a constant zero or a floating point constant +0.0.
Definition at line 4009 of file X86ISelLowering.cpp.
References llvm::isNullConstant(), and llvm::isNullFPConstant().
Referenced by combineAdd(), combineAddOrSubToADCOrSBB(), combineSub(), combineX86CloadCstore(), computeZeroableShuffleElements(), EltsFromConsecutiveLoads(), getFauxShuffleMask(), getMaskNode(), getTargetShuffleAndZeroables(), LowerBuildVectorv4x32(), LowerSCALAR_TO_VECTOR(), and widenSubVector().
◆ mayFoldIntoStore()
◆ mayFoldIntoZeroExtend()
◆ mayFoldLoad()
Check if Op is a load operation that could be folded into some other x86 instruction as a memory operand.
Example: vpaddd (rdi), xmm0, xmm0.
Definition at line 2795 of file X86ISelLowering.cpp.
References llvm::cast(), llvm::X86Subtarget::hasAVX(), and llvm::ISD::isNormalLoad().
Referenced by combineCommutableSHUFP(), combineConcatVectorOps(), combineTargetShuffle(), combineX86ShuffleChain(), EmitCmp(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), lowerShuffleAsDecomposedShuffleMerge(), lowerV2X128Shuffle(), mayFoldLoadIntoBroadcastFromMem(), pushAddIntoCmovOfConsts(), and llvm::X86TargetLowering::ReplaceNodeResults().
◆ mayFoldLoadIntoBroadcastFromMem()
◆ optimizeINCDEC()
◆ optimizeInstFromVEX3ToVEX2()
Definition at line 23 of file X86EncodingOptimization.cpp.
References llvm::X86II::EncodingMask, llvm::X86II::FormMask, FROM_TO, llvm::X86II::isX86_64ExtendedReg(), MI, llvm::X86II::MRMSrcReg, llvm::X86II::OpMapMask, llvm::X86II::REX_W, std::swap(), llvm::X86II::TB, TO_REV, llvm::X86II::VEX, and llvm::X86II::VEX_4V.
◆ optimizeMOV()
◆ optimizeMOVSX()
◆ optimizeShiftRotateWithImmediateOne()
| bool llvm::X86::optimizeShiftRotateWithImmediateOne | ( | MCInst & | MI | ) |
|---|
◆ optimizeToFixedRegisterOrShortImmediateForm()
| bool llvm::X86::optimizeToFixedRegisterOrShortImmediateForm | ( | MCInst & | MI | ) |
|---|
◆ optimizeVPCMPWithImmediateOneOrSix()
| bool llvm::X86::optimizeVPCMPWithImmediateOneOrSix | ( | MCInst & | MI | ) |
|---|