X86InstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H

14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H

21#include

23#define GET_INSTRINFO_HEADER

24#include "X86GenInstrInfo.inc"

26namespace llvm {

27class X86Subtarget;

35namespace X86 {

51unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,

52 bool HasNDD = false);

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117}

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119

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122 switch (TargetFlag) {

130 return true;

131 default:

132 return false;

133 }

134}

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138

140 switch (TargetFlag) {

142 case X86II::MO_GOT:

146 return true;

147 default:

148 return false;

149 }

150}

151

156

158 if (MI.getOperand(Op).isFI())

159 return true;

168}

169

171 if (MI.getOperand(Op).isFI())

172 return true;

175}

176

178 unsigned Op = MI.getOpcode();

179 if (Op == X86::ADD64rm || Op == X86::ADD64mr_ND || Op == X86::ADD64rm_ND) {

184 return true;

185 }

186

187 return false;

188}

189

191 unsigned Op = MI.getOpcode();

192 switch (Op) {

193 case X86::TEST32mr:

194 case X86::TEST64mr:

195 case X86::CMP32rm:

196 case X86::CMP64rm:

197 case X86::MOV32rm:

198 case X86::MOV64rm:

199 case X86::ADC32rm:

200 case X86::ADD32rm:

201 case X86::AND32rm:

202 case X86::OR32rm:

203 case X86::SBB32rm:

204 case X86::SUB32rm:

205 case X86::XOR32rm:

206 case X86::ADC64rm:

207 case X86::ADD64rm:

208 case X86::AND64rm:

209 case X86::OR64rm:

210 case X86::SBB64rm:

211 case X86::SUB64rm:

212 case X86::XOR64rm: {

217 return true;

218 break;

219 }

220 }

221 return false;

222}

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234 bool AllowModify) const;

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238 bool MakeChange) const;

239

240public:

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250 unsigned OpNum) const override;

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262 if (isFrameSetup(I))

263 return I.getOperand(2).getImm();

264 return I.getOperand(1).getImm();

265 }

266

267

268

271 if (isFrameSetup(I))

272 I.getOperand(2).setImm(V);

273 else

274 I.getOperand(1).setImm(V);

275 }

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289 Register &DstReg, unsigned &SubIdx) const override;

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321 int &FrameIndex) const override;

323 int &FrameIndex,

324 TypeSize &MemBytes) const override;

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329 int &FrameIndex) const override;

330

332 int &FrameIndex) const override;

334 int &FrameIndex,

335 TypeSize &MemBytes) const override;

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340 int &FrameIndex) const override;

341

344 Register DestReg, unsigned SubIdx,

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356 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,

357 unsigned &NewSrcSubReg, bool &isKill,

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390 unsigned &SrcOpIdx2) const override;

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411 unsigned

413 unsigned SrcOpIdx2,

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419 const MachineInstr &TailCall) const override;

422 const MachineInstr &TailCall) const override;

423

427 bool AllowModify) const override;

428

430

431 std::optional

434

436 int64_t &ImmVal) const override;

437

441

449 bool AllowModify = false) const override;

450

452 int *BytesRemoved = nullptr) const override;

456 int *BytesAdded = nullptr) const override;

459 int &) const override;

463 Register FalseReg) const override;

466 bool KillSrc, bool RenamableDest = false,

467 bool RenamableSrc = false) const override;

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482 bool isKill = false) const;

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500 VirtRegMap *VRM = nullptr) const override;

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509 bool

511 bool UnfoldLoad, bool UnfoldStore,

513

516

517 unsigned

519 unsigned *LoadRegIndex = nullptr) const override;

520

522 int64_t &Offset2) const override;

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540 int64_t Offset2,

541 unsigned NumLoads) const override;

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548 bool

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563 std::pair<uint16_t, uint16_t>

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572 unsigned

579

581 unsigned OpNum,

585 bool AllowCommute) const;

586

588

593 unsigned UseIdx) const override;

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598 bool Invert) const override;

599

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608 Register &SrcReg2, int64_t &CmpMask,

609 int64_t &CmpValue) const override;

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615 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,

617

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621 std::pair<unsigned, unsigned>

623

626

627 std::optional<std::unique_ptroutliner::OutlinedFunction>

630 std::vectoroutliner::Candidate &RepeatedSequenceLocs,

631 unsigned MinRepeats) const override;

632

634 bool OutlineFromLinkOnceODRs) const override;

635

638 unsigned Flags) const override;

639

642

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650 bool AllowSideEffects = true) const override;

651

653 StringRef &ErrInfo) const override;

654#define GET_INSTRINFO_HELPER_DECLS

655#include "X86GenInstrInfo.inc"

656

660

661 std::optional

663

664protected:

666 unsigned CommuteOpIdx1,

667 unsigned CommuteOpIdx2) const override;

668

669 std::optional

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674 bool DoRegPressureReduce) const override;

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695 int FI) const override;

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697private:

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704 bool Is8BitOp) const;

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709 unsigned OpNum,

712 unsigned Size, Align Alignment) const;

713

715 unsigned OpNum,

718 unsigned BitsSize, bool AllowCommute) const;

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723 int &FrameIndex) const;

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742 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,

743 unsigned &SrcOpIdx1,

744 unsigned &SrcOpIdx2,

745 bool IsIntrinsic = false) const;

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759 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,

761 int64_t *ImmDelta) const;

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769 unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;

770};

771}

772

773#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isRedundantFlagInstr(const MachineInstr *CmpI, Register SrcReg, Register SrcReg2, int64_t ImmValue, const MachineInstr *OI, bool &IsThumb1)

isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags,...

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Analysis containing CSE Info

#define LLVM_DECLARE_VIRTUAL_ANCHOR_FUNCTION()

\macro LLVM_VIRTUAL_ANCHOR_FUNCTION This macro is used to adhere to LLVM's policy that each class wit...

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

This is an important base class in LLVM.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

This holds information about one operand of a machine instruction, indicating the register class for ...

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

This class contains meta information specific to a module.

MachineOperand class - Representation of each machine instruction operand.

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

unsigned getTargetFlags() const

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

Represents one node in the SelectionDAG.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Provide an instruction scheduling machine model to CodeGen passes.

bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override

When calculate the latency of the root instruction, accumulate the latency of the sequence to the roo...

Definition X86InstrInfo.h:690

void getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const override

bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override

Check if there exists an earlier instruction that operates on the same source operands and sets eflag...

bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying...

MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override

void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override

void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override

bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

Returns true iff the routine could find two commutable operands in the given machine instruction.

bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override

X86InstrInfo(const X86Subtarget &STI)

static bool isDataInvariantLoad(MachineInstr &MI)

Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override

bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override

const X86RegisterInfo & getRegisterInfo() const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

Definition X86InstrInfo.h:256

bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override

Returns true if we have preference on the operands order in MI, the commute decision is returned in C...

bool hasLiveCondCodeDef(MachineInstr &MI) const

True if MI has a condition code def, e.g.

std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override

bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override

bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override

bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override

MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...

static bool hasLockPrefix(const MachineInstr &MI)

Definition X86InstrInfo.h:657

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

bool expandPostRAPseudo(MachineInstr &MI) const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override

MCInst getNop() const override

Return the noop instruction to use for a noop.

void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig) const override

outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override

bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override

This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...

MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override

Fold a load or store of the specified stack slot into the specified machine instruction for the speci...

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override

bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override

std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.

const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum) const override

Given a machine instruction descriptor, returns the register class constraint for OpNum,...

bool isUnconditionalTailCall(const MachineInstr &MI) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

std::optional< std::unique_ptr< outliner::OutlinedFunction > > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override

bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, unsigned &NewSrcSubReg, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const

Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.

void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override

bool useMachineCombiner() const override

Definition X86InstrInfo.h:595

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const

int getSPAdjust(const MachineInstr &MI) const override

getSPAdjust - This returns the stack pointer adjustment made by this instruction.

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

bool isReMaterializableImpl(const MachineInstr &MI) const override

getGlobalBaseReg - Return a virtual register initialized with the the global base register value.

int getJumpTableIndex(const MachineInstr &MI) const override

void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override

This is an architecture-specific helper function of reassociateOps.

void setFrameAdjustment(MachineInstr &I, int64_t V) const

Sets the stack pointer adjustment made inside the frame made up by this instruction.

Definition X86InstrInfo.h:269

std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override

bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override

isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.

void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const

void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override

When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions ...

bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override

bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override

static bool isDataInvariant(MachineInstr &MI)

Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...

unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...

void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override

void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override

int64_t getFrameAdjustment(const MachineInstr &I) const

Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....

Definition X86InstrInfo.h:260

bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override

bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override

bool isSubregFoldable() const override

Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...

Definition X86InstrInfo.h:488

uint16_t getExecutionDomainCustom(const MachineInstr &MI) const

bool isHighLatencyDef(int opc) const override

void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...

bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override

unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...

@ C

The default llvm calling convention, compatible with C.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

@ MO_GOTPCREL_NORELAX

MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...

@ MO_GOTOFF

MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...

@ MO_DARWIN_NONLAZY_PIC_BASE

MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...

@ MO_COFFSTUB

MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....

@ MO_DARWIN_NONLAZY

MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...

@ MO_GOT

MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...

@ MO_TLVP

MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.

@ MO_DLLIMPORT

MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...

@ MO_GOTTPOFF

MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...

@ MO_PIC_BASE_OFFSET

MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...

@ MO_GOTPCREL

MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...

int getMemoryOperandNo(uint64_t TSFlags)

unsigned getOperandBias(const MCInstrDesc &Desc)

Compute whether all of the def operands are repeated in the uses and therefore should be skipped.

CondCode getCondFromBranch(const MachineInstr &MI)

CondCode getCondFromCFCMov(const MachineInstr &MI)

CondCode getCondFromMI(const MachineInstr &MI)

Return the condition code of the instruction.

int getFirstAddrOperandIdx(const MachineInstr &MI)

Return the index of the instruction's first address operand, if it has a memory reference,...

unsigned getSwappedVCMPImm(unsigned Imm)

Get the VCMP immediate if the opcodes are swapped.

CondCode GetOppositeBranchCondition(CondCode CC)

GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.

unsigned getSwappedVPCOMImm(unsigned Imm)

Get the VPCOM immediate if the opcodes are swapped.

bool isX87Instruction(MachineInstr &MI)

Check if the instruction is X87 instruction.

unsigned getNonNDVariant(unsigned Opc)

unsigned getVPCMPImmForCond(ISD::CondCode CC)

Get the VPCMP immediate for the given condition.

std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)

Return a pair of condition code for the given predicate and whether the instruction operands should b...

CondCode getCondFromSETCC(const MachineInstr &MI)

unsigned getSwappedVPCMPImm(unsigned Imm)

Get the VPCMP immediate if the opcodes are swapped.

CondCode getCondFromCCMP(const MachineInstr &MI)

int getCCMPCondFlagsFromCondCode(CondCode CC)

int getCondSrcNoFromDesc(const MCInstrDesc &MCID)

Return the source operand # for condition code by MCID.

const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)

Find any constant pool entry associated with a specific instruction operand.

AsmComments

Definition X86InstrInfo.h:37

@ AC_EVEX_2_EVEX

Definition X86InstrInfo.h:43

@ AC_EVEX_2_VEX

Definition X86InstrInfo.h:41

@ AC_EVEX_2_LEGACY

Definition X86InstrInfo.h:39

unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false)

Return a cmov opcode for the given register size in bytes, and operand type.

unsigned getNFVariant(unsigned Opc)

unsigned getVectorRegisterWidth(const MCOperandInfo &Info)

Get the width of the vector register operand.

CondCode getCondFromCMov(const MachineInstr &MI)

InstrType

Represents how an instruction should be mapped by the outliner.

This is an optimization pass for GlobalISel generic memory operations.

static bool isGlobalStubReference(unsigned char TargetFlag)

isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...

Definition X86InstrInfo.h:121

static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)

isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...

Definition X86InstrInfo.h:139

static bool isAddMemInstrWithRelocation(const MachineInstr &MI)

Definition X86InstrInfo.h:177

static bool isMem(const MachineInstr &MI, unsigned Op)

Definition X86InstrInfo.h:170

static bool isScale(const MachineOperand &MO)

Definition X86InstrInfo.h:152

static bool isMemInstrWithGOTPCREL(const MachineInstr &MI)

Definition X86InstrInfo.h:190

static bool isLeaMem(const MachineInstr &MI, unsigned Op)

Definition X86InstrInfo.h:157

DWARFExpression::Operation Op

X86MachineCombinerPattern

Definition X86InstrInfo.h:30

@ DPWSSD

Definition X86InstrInfo.h:32

This struct is a compact representation of a valid (non-zero power of two) alignment.

Represents a predicate at the MachineFunction level.

This class is used to group {132, 213, 231} forms of FMA opcodes together.

An individual sequence of instructions to be replaced with a call to an outlined function.

The information necessary to create an outlined function for some class of candidate.