X86RegisterBankInfo.cpp Source File (original) (raw)

22#include "llvm/IR/IntrinsicsX86.h"

24#define GET_TARGET_REGBANK_IMPL

25#include "X86GenRegisterBank.inc"

27using namespace llvm;

29#define GET_TARGET_REGBANK_INFO_IMPL

30#include "X86GenRegisterBankInfo.def"

36 (void)RBGPR;

37 assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization.");

41 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) &&

42 "Subclass not added?");

44 "GPRs should hold up to 64-bit");

45}

52 default:

53 return false;

55 case Intrinsic::x86_sse_rcp_ss:

56 case Intrinsic::x86_sse_rcp_ps:

57 case Intrinsic::x86_sse_rsqrt_ss:

58 case Intrinsic::x86_sse_rsqrt_ps:

59 case Intrinsic::x86_sse_min_ss:

60 case Intrinsic::x86_sse_min_ps:

61 case Intrinsic::x86_sse_max_ss:

62 case Intrinsic::x86_sse_max_ps:

63 return true;

64 }

65 return false;

66}

68bool X86RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,

71 unsigned Depth) const {

72 unsigned Op = MI.getOpcode();

74 return true;

78 return true;

82 if (Op != TargetOpcode::COPY && .isPHI() &&

84 return false;

88 if (RB == &getRegBank(X86::PSRRegBankID))

89 return true;

90 if (RB == &getRegBank(X86::GPRRegBankID))

91 return false;

97 if (.isPHI() || Depth > MaxFPRSearchDepth)

98 return false;

100 return any_of(MI.explicit_uses(), [&](const MachineOperand &Op) {

101 return Op.isReg() &&

102 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);

103 });

104}

105

106bool X86RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,

109 unsigned Depth) const {

110 switch (MI.getOpcode()) {

111 case TargetOpcode::G_FPTOSI:

112 case TargetOpcode::G_FPTOUI:

113 case TargetOpcode::G_FCMP:

114 case X86::G_FIST:

115 case TargetOpcode::G_LROUND:

116 case TargetOpcode::G_LLROUND:

117 case TargetOpcode::G_INTRINSIC_TRUNC:

118 case TargetOpcode::G_INTRINSIC_ROUND:

119 return true;

120 default:

121 break;

122 }

124}

125

126bool X86RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,

129 unsigned Depth) const {

130 switch (MI.getOpcode()) {

131 case TargetOpcode::G_SITOFP:

132 case TargetOpcode::G_UITOFP:

133 case X86::G_FILD:

134 return true;

135 default:

136 break;

137 }

139}

140

141X86GenRegisterBankInfo::PartialMappingIdx

143 const LLT &Ty, bool isFP) {

146 bool HasSSE1 = ST->hasSSE1();

147 bool HasSSE2 = ST->hasSSE2();

148

149 if (Ty.getSizeInBits() == 80)

150 isFP = true;

151 if ((Ty.isScalar() && !isFP) || Ty.isPointer()) {

152 switch (Ty.getSizeInBits()) {

153 case 1:

154 case 8:

155 return PMI_GPR8;

156 case 16:

157 return PMI_GPR16;

158 case 32:

159 return PMI_GPR32;

160 case 64:

161 return PMI_GPR64;

162 case 128:

163 return PMI_VEC128;

164 break;

165 default:

167 }

168 } else if (Ty.isScalar()) {

169 switch (Ty.getSizeInBits()) {

170 case 32:

171 return HasSSE1 ? PMI_FP32 : PMI_PSR32;

172 case 64:

173 return HasSSE2 ? PMI_FP64 : PMI_PSR64;

174 case 128:

175 return PMI_VEC128;

176 case 80:

177 return PMI_PSR80;

178 default:

180 }

181 } else {

182 switch (Ty.getSizeInBits()) {

183 case 128:

184 return PMI_VEC128;

185 case 256:

186 return PMI_VEC256;

187 case 512:

188 return PMI_VEC512;

189 default:

191 }

192 }

193

194 return PMI_None;

195}

196

197void X86RegisterBankInfo::getInstrPartialMappingIdxs(

200

201 unsigned NumOperands = MI.getNumOperands();

202 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {

203 auto &MO = MI.getOperand(Idx);

204 if (!MO.isReg() || !MO.getReg())

205 OpRegBankIdx[Idx] = PMI_None;

206 else

207 OpRegBankIdx[Idx] =

209 }

210}

211

212bool X86RegisterBankInfo::getInstrValueMapping(

216

217 unsigned NumOperands = MI.getNumOperands();

218 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {

219 if (.getOperand(Idx).isReg())

220 continue;

221 if (.getOperand(Idx).getReg())

222 continue;

223

225 if (!Mapping->isValid())

226 return false;

227

228 OpdsMapping[Idx] = Mapping;

229 }

230 return true;

231}

232

234X86RegisterBankInfo::getSameOperandsMapping(const MachineInstr &MI,

235 bool isFP) const {

236 const MachineFunction &MF = *MI.getParent()->getParent();

237 const MachineRegisterInfo &MRI = MF.getRegInfo();

238

239 unsigned NumOperands = MI.getNumOperands();

240 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

241

242 if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) ||

243 (Ty != MRI.getType(MI.getOperand(2).getReg())))

245

248}

249

256 unsigned Opc = MI.getOpcode();

257

258

259

263 return Mapping;

264 }

265

266 switch (Opc) {

267 case TargetOpcode::G_ADD:

268 case TargetOpcode::G_SUB:

269 case TargetOpcode::G_MUL:

270 return getSameOperandsMapping(MI, false);

271 case TargetOpcode::G_FADD:

272 case TargetOpcode::G_FSUB:

273 case TargetOpcode::G_FMUL:

274 case TargetOpcode::G_FDIV:

275 return getSameOperandsMapping(MI, true);

276 case TargetOpcode::G_SHL:

277 case TargetOpcode::G_LSHR:

278 case TargetOpcode::G_ASHR: {

279 unsigned NumOperands = MI.getNumOperands();

280 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

281

284 }

285 default:

286 break;

287 }

288

289 unsigned NumOperands = MI.getNumOperands();

291

292 switch (Opc) {

293 case TargetOpcode::G_FSQRT:

294 case TargetOpcode::G_FPEXT:

295 case TargetOpcode::G_FPTRUNC:

296 case TargetOpcode::G_FCONSTANT:

297

298

299 getInstrPartialMappingIdxs(MI, MRI, true, OpRegBankIdx);

300 break;

301 case X86::G_FIST:

302 case X86::G_FILD: {

303 auto &Op0 = MI.getOperand(0);

304 auto &Op1 = MI.getOperand(1);

305 const LLT Ty0 = MRI.getType(Op0.getReg());

306 const LLT Ty1 = MRI.getType(Op1.getReg());

309 break;

310 }

311 case TargetOpcode::G_SITOFP:

312 case TargetOpcode::G_FPTOSI:

313 case TargetOpcode::G_UITOFP:

314 case TargetOpcode::G_FPTOUI: {

315

316

317 auto &Op0 = MI.getOperand(0);

318 auto &Op1 = MI.getOperand(1);

319 const LLT Ty0 = MRI.getType(Op0.getReg());

320 const LLT Ty1 = MRI.getType(Op1.getReg());

321

322 bool FirstArgIsFP =

323 Opc == TargetOpcode::G_SITOFP || Opc == TargetOpcode::G_UITOFP;

326 break;

327 }

328 case TargetOpcode::G_FCMP: {

329 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());

330 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());

331 (void)Ty2;

333 "Mismatched operand sizes for G_FCMP");

334

338 "Unsupported size for G_FCMP");

340 OpRegBankIdx = {PMI_GPR8,

341 PMI_None, FpRegBank, FpRegBank};

342 break;

343 }

344 case TargetOpcode::G_FABS:

345 case TargetOpcode::G_TRUNC:

346 case TargetOpcode::G_ANYEXT: {

347 auto &Op0 = MI.getOperand(0);

348 auto &Op1 = MI.getOperand(1);

349 const LLT Ty0 = MRI.getType(Op0.getReg());

350 const LLT Ty1 = MRI.getType(Op1.getReg());

351

354 bool isFPAnyExt =

357 Opc == TargetOpcode::G_ANYEXT;

358 bool isFAbs = (Opc == TargetOpcode::G_FABS);

359 getInstrPartialMappingIdxs(

360 MI, MRI, isFPTrunc || isFPAnyExt || isFAbs, OpRegBankIdx);

361 break;

362 }

363 case TargetOpcode::G_LOAD: {

364

365

366

369

370

371

372

373 return onlyUsesFP(UseMI, MRI, TRI);

374 });

375 getInstrPartialMappingIdxs(MI, MRI, IsFP, OpRegBankIdx);

376 break;

377 }

378 case TargetOpcode::G_STORE: {

379

381 if (!VReg)

382 break;

384 bool IsFP = onlyDefinesFP(*DefMI, MRI, TRI);

385 getInstrPartialMappingIdxs(MI, MRI, IsFP, OpRegBankIdx);

386 break;

387 }

388 default:

389

390

391 getInstrPartialMappingIdxs(MI, MRI, false, OpRegBankIdx);

392 break;

393 }

394

395

397 if (!getInstrValueMapping(MI, OpRegBankIdx, OpdsMapping))

399

402}

403

408

411

416

417 switch (MI.getOpcode()) {

418 case TargetOpcode::G_LOAD:

419 case TargetOpcode::G_STORE:

420 case TargetOpcode::G_IMPLICIT_DEF: {

421

424 break;

425

426 unsigned NumOperands = MI.getNumOperands();

427

428

430 getInstrPartialMappingIdxs(MI, MRI, true, OpRegBankIdx);

431

432

434 if (!getInstrValueMapping(MI, OpRegBankIdx, OpdsMapping))

435 break;

436

441 return AltMappings;

442 }

443 default:

444 break;

445 }

447}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

static unsigned getIntrinsicID(const SDNode *N)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

This file declares the targeting of the RegisterBankInfo class for X86.

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Helper class to build MachineInstr.

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Helper class that represents how the value of an instruction may be mapped and what is the related co...

bool isValid() const

Check whether this object is valid.

Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...

virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const

Get the alternative mappings for MI.

const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const

Method to get a uniquely generated InstructionMapping.

static void applyDefaultMapping(const OperandsMapper &OpdMapper)

Helper method to apply something that is like the default mapping.

const InstructionMapping & getInvalidInstructionMapping() const

Method to get a uniquely generated invalid InstructionMapping.

const RegisterBank & getRegBank(unsigned ID)

Get the register bank identified by ID.

unsigned getMaximumSize(unsigned RegBankID) const

Get the maximum size in bits that fits in the given register bank.

TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const

Get the size in bits of Reg.

const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

static const unsigned DefaultMappingID

Identifier used when the related instruction mapping instance is generated by target independent code...

SmallVector< const InstructionMapping *, 4 > InstructionMappings

Convenient type to represent the alternatives for mapping an instruction.

const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const

Try to get the mapping of MI.

This class implements the register bank concept.

LLVM_ABI bool covers(const TargetRegisterClass &RC) const

Check whether this register bank covers RC.

unsigned getID() const

Get the identifier of this register bank.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

static PartialMappingIdx getPartialMappingIdx(const MachineInstr &MI, const LLT &Ty, bool isFP)

Definition X86RegisterBankInfo.cpp:142

static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx Idx, unsigned NumOperands)

X86RegisterBankInfo(const TargetRegisterInfo &TRI)

Definition X86RegisterBankInfo.cpp:32

InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override

Get the alternative mappings for MI.

Definition X86RegisterBankInfo.cpp:410

const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override

Get the mapping of the different operands of MI on the register bank.

Definition X86RegisterBankInfo.cpp:251

void applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override

See RegisterBankInfo::applyMapping.

Definition X86RegisterBankInfo.cpp:404

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

bool isPreISelGenericOpcode(unsigned Opcode)

Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.

bool isPreISelGenericOptimizationHint(unsigned Opcode)

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc)

Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...