XtensaAsmBackend.cpp Source File (original) (raw)

23using namespace llvm;

25namespace llvm {

29 bool IsLittleEndian;

31public:

34 IsLittleEndian(isLE) {}

38 }

53 }

54};

55}

65 {"fixup_xtensa_call_18", 6, 18,

68 {"fixup_xtensa_l32r_16", 8, 16,

75 "Invalid kind!");

77}

81 unsigned Kind = Fixup.getKind();

82 switch (Kind) {

83 default:

92 return 0;

94 if (!isUInt<6>(Value))

96 unsigned Hi2 = (Value >> 4) & 0x3;

97 unsigned Lo4 = Value & 0xf;

98 return (Hi2 << 4) | (Lo4 << 12);

99 }

102 if (!isInt<8>(Value))

104 return (Value & 0xff);

107 if (!isInt<12>(Value))

109 return (Value & 0xfff);

112 if (!isInt<18>(Value))

114 return (Value & 0x3ffff);

117 if (!isInt<20>(Value))

120 Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");

121 return (Value & 0xffffc) >> 2;

126 if (!isInt<18>(Value) && (Value & 0x20000))

129 Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");

130 return (Value & 0x3fffc) >> 2;

131 }

132}

133

134static unsigned getSize(unsigned Kind) {

135 switch (Kind) {

136 default:

137 return 3;

139 return 4;

141 return 2;

142 }

143}

144

148 bool IsResolved,

150 MCContext &Ctx = Asm.getContext();

152

154

155

157

159 return;

160

162 unsigned FullSize = getSize(Fixup.getKind());

163

164 for (unsigned i = 0; i != FullSize; ++i) {

166 }

167}

168

171 return false;

172}

173

176

179 uint64_t NumNops24b = Count / 3;

180

181 for (uint64_t i = 0; i != NumNops24b; ++i) {

182

183

184 if (IsLittleEndian) {

188 } else {

190 }

191 Count -= 3;

192 }

193

194

195 switch (Count) {

196 default:

197 break;

198 case 1:

200 break;

201 case 2:

202

205 break;

206 }

207

208 return true;

209}

210

218}

unsigned const MachineRegisterInfo * MRI

static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)

Analysis containing CSE Info

PowerPC TLS Dynamic Call Fixup

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static unsigned getSize(unsigned Kind)

Generic interface to target specific assembler backends.

virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const

Get information on a fixup kind.

Context object for machine code objects.

void reportError(SMLoc L, const Twine &Msg)

Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...

Instances of this class represent a single low-level machine instruction.

Base class for classes that define behaviour that is specific to both the target and the object forma...

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

This represents an "assembler immediate".

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

Target - Wrapper for Target specific information.

OSType getOS() const

Get the parsed operating system type of this triple.

LLVM Value Representation.

const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override

Get information on a fixup kind.

void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override

Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...

XtensaMCAsmBackend(uint8_t osABI, bool isLE)

std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override

bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override

Write an (optimal) nop sequence of Count bytes to the given output.

unsigned getNumFixupKinds() const override

Get the number of target specific fixup kinds.

bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override

Check whether the given instruction may need relaxation.

void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override

Relax the instruction in the given fragment to the next wider instruction.

This class implements an extremely fast bulk output stream that can only output to a stream.

raw_ostream & write(unsigned char C)

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

MCFixupKind

Extensible enumeration to represent the type of a fixup.

@ FK_Data_8

A eight-byte fixup.

@ FK_Data_1

A one-byte fixup.

@ FK_Data_4

A four-byte fixup.

@ FK_Data_2

A two-byte fixup.

std::unique_ptr< MCObjectTargetWriter > createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian)

MCAsmBackend * createXtensaMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Target independent information on a fixup kind.

@ FKF_IsAlignedDownTo32Bits

Should this fixup kind force a 4-byte aligned effective PC value?

@ FKF_IsPCRel

Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...