XtensaISelLowering.cpp Source File (original) (raw)

32#include

34using namespace llvm;

36#define DEBUG_TYPE "xtensa-lower"

50 if (Reg >= Xtensa::A2 && Reg <= Xtensa::A7)

51 return Reg - Xtensa::A2 + Xtensa::A10;

52 return Reg;

53}

58 MVT PtrVT = MVT::i32;

62 if (Subtarget.hasSingleFloat()) {

64 }

66 if (Subtarget.hasBoolean()) {

68 }

101 }

102

108

109

110

112

115

119

120 if (Subtarget.hasSingleFloat()) {

123 } else {

126 }

127

130

135

136 if (Subtarget.hasMul32())

138 else

140

141 if (Subtarget.hasMul32High()) {

144 } else {

147 }

148

151

152 if (Subtarget.hasDiv32()) {

157 } else {

162 }

163

166

170

179

182

183

185

188

189

190

195

196

197 for (unsigned I = MVT::FIRST_FP_VALUETYPE; I <= MVT::LAST_FP_VALUETYPE; ++I) {

200 if (VT.getSizeInBits() == 32 && Subtarget.hasSingleFloat()) {

207 } else {

214 }

215

216

225 }

226 }

227

228

229 if (Subtarget.hasSingleFloat()) {

236 } else {

243 }

244

245

247

248 if (Subtarget.hasS32C1I()) {

251 } else if (Subtarget.hasForcedAtomics()) {

253 } else {

255 }

256

257

259}

260

263

264 return false;

265}

266

268 bool ForCodeSize) const {

269 return false;

270}

271

272

273

274

277 if (Constraint.size() == 1) {

278 switch (Constraint[0]) {

279 case 'r':

281 default:

282 break;

283 }

284 }

286}

287

290 AsmOperandInfo &Info, const char *Constraint) const {

292 Value *CallOperandVal = Info.CallOperandVal;

293

294

295 if (!CallOperandVal)

297

299

300

301 switch (*Constraint) {

302 default:

304 break;

305 case 'r':

306 if (Ty->isIntegerTy())

308 break;

309 }

310 return Weight;

311}

312

313std::pair<unsigned, const TargetRegisterClass *>

316 if (Constraint.size() == 1) {

317

318 switch (Constraint[0]) {

319 default:

320 break;

321 case 'r':

322 return std::make_pair(0U, &Xtensa::ARRegClass);

323 }

324 }

326}

327

332

333

334 if (Constraint.size() > 1)

335 return;

336

338}

339

340

341

342

343

344#include "XtensaGenCallingConv.inc"

345

347 Xtensa::A5, Xtensa::A6, Xtensa::A7};

348

353 if (ArgFlags.isByVal()) {

355 unsigned ByValSize = ArgFlags.getByValSize();

356 if (ByValSize < 4) {

357 ByValSize = 4;

358 }

359 if (ByValAlign < Align(4)) {

360 ByValAlign = Align(4);

361 }

362 unsigned Offset = State.AllocateStack(ByValSize, ByValAlign);

364

365

366 while (State.AllocateReg(IntRegs))

367 ;

368 return false;

369 }

370

371

372 if (LocVT == MVT::i8 || LocVT == MVT::i16) {

373 LocVT = MVT::i32;

374 if (ArgFlags.isSExt())

376 else if (ArgFlags.isZExt())

378 else

380 }

381

383

385 bool needs64BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(8));

386 bool needs128BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(16));

387

388 if (ValVT == MVT::i32) {

390

391

392 if (needs64BitAlign && (Register == Xtensa::A3 || Register == Xtensa::A5 ||

395

396

397 if (needs128BitAlign && (Register != Xtensa::A2))

399 ;

400 LocVT = MVT::i32;

401 } else if (ValVT == MVT::f64) {

402

407 State.AllocateReg(IntRegs);

408 LocVT = MVT::i32;

409 } else {

411 }

412

414 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);

416 } else {

418 }

419

420 return false;

421}

422

423

426 EVT VT) const {

428 return MVT::i32;

429

431}

432

434 bool IsVarArg) const {

436}

437

445

446

447 std::vector OutChains;

448

449

453

455

456 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

458

461

462 if (RegVT != MVT::i32)

463 report_fatal_error("RegVT not supported by FormalArguments Lowering");

464

465

466

468 MCRegister FrameReg = Subtarget.getRegisterInfo()->getFrameRegister(MF);

469

470

471

472 if (Subtarget.isWindowedABI() && (VA.getLocReg() == FrameReg)) {

473 Reg = MF.addLiveIn(Xtensa::A8, &Xtensa::ARRegClass);

475 } else {

477 }

478

480

481

482

483

485 unsigned Opcode = 0;

490 if (Opcode)

491 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,

493 ArgValue = DAG.getNode((VA.getValVT() == MVT::f32) ? ISD::BITCAST

496 }

497

499

500 } else {

502

504

505

507 true);

508

509 if (Ins[VA.getValNo()].Flags.isByVal()) {

510

513 } else {

514

518 ValVT, DL, Chain, FIN,

520 }

521 }

522 }

523

524 if (IsVarArg) {

526 unsigned ArgRegsNum = std::size(IntRegs);

531 MVT RegTy = MVT::i32;

533

535

538

539

540

541

542 int VaArgOffset, VarArgsSaveSize;

543

544

545

546 if (ArgRegsNum == Idx) {

548 VarArgsSaveSize = 0;

549 } else {

550 VarArgsSaveSize = RegSize * (ArgRegsNum - Idx);

551 VaArgOffset = -VarArgsSaveSize;

552

553

554

557

558

559

560 for (unsigned I = Idx; I < ArgRegsNum; ++I, VaArgOffset += RegSize) {

561 const Register Reg = RegInfo.createVirtualRegister(RC);

562 RegInfo.addLiveIn(IntRegs[I], Reg);

563

569 OutChains.push_back(Store);

570 }

571 }

572 }

573

574

575

576 if (!OutChains.empty()) {

577 OutChains.push_back(Chain);

579 }

580

581 return Chain;

582}

583

596 bool IsVarArg = CLI.IsVarArg;

597

601

602

603 IsTailCall = false;

604

605

607 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());

608

609 CCAssignFn *CC = CCAssignFnForCall(CallConv, IsVarArg);

610

612

613

615

617 unsigned NextStackOffset = alignTo(NumBytes, StackAlignment);

618

620

621

622 std::deque<std::pair<unsigned, SDValue>> RegsToPass;

625 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {

627 SDValue ArgValue = OutVals[I];

629

631

633 else if (Flags.isByVal()) {

635 assert(Flags.getByValSize() &&

636 "ByVal args of size 0 should have been ignored by front-end.");

637 assert(!IsTailCall &&

638 "Do not tail-call optimize if there is a byval argument.");

639

640 if (!StackPtr.getNode())

647 Chain, DL, Address, ArgValue, SizeNode, Flags.getNonZeroByValAlign(),

648 false, false,

652 } else {

653 assert(VA.isMemLoc() && "Argument not register or memory");

654

655

656

657 if (!StackPtr.getNode())

662

663

666 }

667 }

668

669

670 if (!MemOpChains.empty())

672

673

675 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {

676 unsigned Reg = RegsToPass[I].first;

677 if (Subtarget.isWindowedABI())

679 Chain = DAG.getCopyToReg(Chain, DL, Reg, RegsToPass[I].second, Glue);

681 }

682 std::string name;

683 unsigned char TF = 0;

684

685

686

688 name = E->getSymbol();

689 TF = E->getTargetFlags();

692 } else

697 }

698

700

705

707 *DAG.getContext(), name.c_str(), LabelId, false, Modifier);

708

709

711 SDValue CPWrap = getAddrPCRel(CPAddr, DAG);

715 }

716

717

719 Ops.push_back(Chain);

720 Ops.push_back(Callee);

721

722

724 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);

725 assert(Mask && "Missing call preserved mask for calling convention");

727

728

729

730 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {

731 unsigned Reg = RegsToPass[I].first;

732 if (Subtarget.isWindowedABI())

734 Ops.push_back(DAG.getRegister(Reg, RegsToPass[I].second.getValueType()));

735 }

736

737

739 Ops.push_back(Glue);

740

742 Chain = DAG.getNode(Subtarget.isWindowedABI() ? XtensaISD::CALLW8

743 : XtensaISD::CALL,

744 DL, NodeTys, Ops);

746

747

751

752

754 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());

755 RetCCInfo.AnalyzeCallResult(Ins, Subtarget.isWindowedABI() ? RetCCW8_Xtensa

756 : RetCC_Xtensa);

757

758

759 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {

761

762

765 Chain = RetValue.getValue(1);

767

769 }

770 return Chain;

771}

772

776 const Type *RetTy) const {

778 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

779 return CCInfo.CheckReturn(Outs, RetCC_Xtensa);

780}

781

784 bool IsVarArg,

789

790

792 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());

794

796

797 if (RetLocs.empty())

798 return DAG.getNode(Subtarget.isWindowedABI() ? XtensaISD::RETW

799 : XtensaISD::RET,

800 DL, MVT::Other, Chain);

801

802

805 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {

807 SDValue RetValue = OutVals[I];

808

809

810 assert(VA.isRegLoc() && "Can only return in registers!");

811

812

817 }

818

819

820 RetOps[0] = Chain;

823

824 return DAG.getNode(Subtarget.isWindowedABI() ? XtensaISD::RETW

825 : XtensaISD::RET,

826 DL, MVT::Other, RetOps);

827}

828

830 switch (Cond) {

832 return Xtensa::BEQ;

834 return Xtensa::BNE;

836 return Xtensa::BLT;

838 return Xtensa::BGE;

840 return Xtensa::BLT;

842 return Xtensa::BGE;

844 return Xtensa::BLTU;

846 return Xtensa::BGEU;

848 return Xtensa::BLTU;

850 return Xtensa::BGEU;

851 default:

853 }

854}

855

857 switch (Cond) {

859 return std::make_pair(Xtensa::BF, Xtensa::OEQ_S);

861 return std::make_pair(Xtensa::BT, Xtensa::UN_S);

863 return std::make_pair(Xtensa::BF, Xtensa::UN_S);

865 return std::make_pair(Xtensa::BT, Xtensa::UEQ_S);

867 return std::make_pair(Xtensa::BT, Xtensa::ULE_S);

869 return std::make_pair(Xtensa::BT, Xtensa::ULT_S);

872 return std::make_pair(Xtensa::BT, Xtensa::OEQ_S);

874 return std::make_pair(Xtensa::BF, Xtensa::OEQ_S);

877 return std::make_pair(Xtensa::BT, Xtensa::OLE_S);

880 return std::make_pair(Xtensa::BT, Xtensa::OLT_S);

882 return std::make_pair(Xtensa::BF, Xtensa::OLT_S);

884 return std::make_pair(Xtensa::BF, Xtensa::OLE_S);

886 return std::make_pair(Xtensa::BF, Xtensa::ULE_S);

888 return std::make_pair(Xtensa::BF, Xtensa::ULT_S);

890 return std::make_pair(Xtensa::BF, Xtensa::UEQ_S);

892 return std::make_pair(Xtensa::BF, Xtensa::OLE_S);

894 return std::make_pair(Xtensa::BF, Xtensa::OLT_S);

895 default:

897 }

898}

899

902 SDLoc DL(Op);

903 EVT Ty = Op.getValueType();

906 SDValue TrueValue = Op.getOperand(2);

907 SDValue FalseValue = Op.getOperand(3);

909

910 if (LHS.getValueType() == MVT::i32) {

913

915 FalseValue, TargetCC, Op->getFlags());

916 return Res;

917 }

918 assert(LHS.getValueType() == MVT::f32 &&

919 "We expect MVT::f32 type of the LHS Operand in SELECT_CC");

920 unsigned BrOpcode;

921 unsigned CmpOpCode;

925 return DAG.getNode(XtensaISD::SELECT_CC_FP, DL, Ty,

926 {LHS, RHS, TrueValue, FalseValue, TargetCC, TargetBC},

927 Op->getFlags());

928}

929

932

933

934

935

936

937 if (Op.getConstantOperandVal(0) != 0)

939

942 EVT VT = Op.getValueType();

944

945

946

949}

950

954 SDLoc DL(CN);

957 if (Op.getValueType() == MVT::i32) {

958

960 return Op;

961

962 SDNode &OpNode = *Op.getNode();

965 return Op;

971 return Res;

972 }

973 return Op;

974}

975

979 SDLoc DL(Op);

980 auto PtrVT = Op.getValueType();

981 const GlobalValue *GV = G->getGlobal();

982

984 SDValue CPWrap = getAddrPCRel(CPAddr, DAG);

988 return Res;

989}

990

991SDValue XtensaTargetLowering::LowerGlobalTLSAddress(SDValue Op,

994 SDLoc DL(Op);

995 EVT PtrVT = Op.getValueType();

996 const GlobalValue *GV = G->getGlobal();

997

1000

1002

1003 if (!Subtarget.hasTHREADPTR()) {

1006 DL.getDebugLoc()));

1007 return DAG.getPOISON(Op->getValueType(0));

1008 }

1009

1013 XtensaMachineFunctionInfo *XtensaFI =

1014 MF.getInfo();

1016

1017

1021

1022

1024 SDValue CPWrap = getAddrPCRel(CPAddr, DAG);

1028

1031 DAG.getNode(XtensaISD::RUR, DL, MVT::i32, TPRegister);

1032

1034 }

1035

1038 "only local-exec and initial-exec TLS mode supported", DL.getDebugLoc()));

1039

1040 return DAG.getPOISON(Op->getValueType(0));

1041}

1042

1046 SDLoc DL(Op);

1048 EVT PtrVT = Op.getValueType();

1050 XtensaMachineFunctionInfo *XtensaFI = MF.getInfo();

1052

1053 XtensaConstantPoolValue *CPV =

1056 SDValue CPWrap = getAddrPCRel(CPAddr, DAG);

1060 return Res;

1061}

1062

1064 SDValue Chain = Op.getOperand(0);

1065 SDValue Table = Op.getOperand(1);

1067 SDLoc DL(Op);

1074 unsigned EntrySize = MJTI->getEntrySize(TD);

1075

1076 assert((MJTI->getEntrySize(TD) == 4) && "Unsupported jump-table entry size");

1077

1081

1084 DAG.getLoad(PtrVT, DL, Chain, Addr,

1086

1087 return DAG.getNode(XtensaISD::BR_JT, DL, MVT::Other, LD.getValue(1), LD,

1088 TargetJT);

1089}

1090

1094 EVT PtrVT = Op.getValueType();

1095 SDLoc DL(Op);

1096

1097

1098 XtensaConstantPoolValue *CPV =

1100

1101

1103

1105 PtrVT, DL, DAG.getEntryNode(), getAddrPCRel(CPAddr, DAG),

1107 return Res;

1108}

1109

1112 SDLoc DL(Op);

1113 EVT Ty = Op.getValueType();

1114 return DAG.getNode(XtensaISD::PCREL_WRAPPER, DL, Ty, Op);

1115}

1116

1119 EVT PtrVT = Op.getValueType();

1122

1123 if (->isMachineConstantPoolEntry()) {

1125 CP->getOffset());

1126 } else {

1128 }

1129

1130 return getAddrPCRel(Result, DAG);

1131}

1132

1136 Op.getValueType());

1137}

1138

1141 SDValue Chain = Op.getOperand(0);

1142 SDValue NewSP = Op.getOperand(1);

1143

1144 if (Subtarget.isWindowedABI()) {

1145 return DAG.getNode(XtensaISD::MOVSP, SDLoc(Op), MVT::Other, Chain, NewSP);

1146 }

1147

1148 return DAG.getCopyToReg(Chain, SDLoc(Op), Xtensa::SP, NewSP);

1149}

1150

1153

1154

1155

1156

1157

1158 if (Op.getConstantOperandVal(0) != 0)

1160

1164 EVT VT = Op.getValueType();

1165 SDLoc DL(Op);

1166

1167 MCRegister FrameRegister = Subtarget.getRegisterInfo()->getFrameRegister(MF);

1170 return FrameAddr;

1171}

1172

1173SDValue XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,

1175 SDValue Chain = Op.getOperand(0);

1176 SDValue Size = Op.getOperand(1);

1177 EVT VT = Size->getValueType(0);

1178 SDLoc DL(Op);

1179

1180

1185

1186 MCRegister SPReg = Xtensa::SP;

1189 if (Subtarget.isWindowedABI()) {

1190 Chain = DAG.getNode(XtensaISD::MOVSP, SDLoc(Op), MVT::Other, SP.getValue(1),

1191 NewSP);

1192 } else {

1194 }

1195

1198

1201}

1202

1206 XtensaMachineFunctionInfo *XtensaFI = MF.getInfo();

1207 SDValue Chain = Op.getOperand(0);

1208 SDValue Addr = Op.getOperand(1);

1210 SDLoc DL(Op);

1211

1212

1213

1214

1215

1216

1217

1222

1223

1224

1225

1226

1227 if (ArgWords < 6) {

1228 VAIndex = DAG.getConstant(ArgWords * 4, DL, MVT::i32);

1229 } else {

1231 }

1232

1235 uint64_t FrameOffset = PtrVT.getStoreSize();

1237

1238

1241

1243 DAG.getStore(Chain, DL, StackPtr, Addr, MachinePointerInfo(SV));

1244

1245 uint64_t NextOffset = FrameOffset;

1248

1249

1250 SDValue StoreRegPtr = DAG.getStore(StoreStackPtr, DL, FrameIndex, NextPtr,

1251 MachinePointerInfo(SV, NextOffset));

1252 NextOffset += FrameOffset;

1254

1255

1256 return DAG.getStore(StoreRegPtr, DL, VAIndex, NextPtr,

1257 MachinePointerInfo(SV, NextOffset));

1258}

1259

1261

1262 constexpr unsigned VAListSize = 3 * 4;

1263 SDValue Chain = Op.getOperand(0);

1264 SDValue DstPtr = Op.getOperand(1);

1265 SDValue SrcPtr = Op.getOperand(2);

1268 SDLoc DL(Op);

1269

1270 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,

1271 DAG.getConstant(VAListSize, SDLoc(Op), MVT::i32),

1272 Align(4), false, true,

1273 nullptr, std::nullopt, MachinePointerInfo(DstSV),

1274 MachinePointerInfo(SrcSV));

1275}

1276

1278 SDNode *Node = Op.getNode();

1279 EVT VT = Node->getValueType(0);

1281 EVT PtrVT = Op.getValueType();

1283 SDValue VAListPtr = Node->getOperand(1);

1285 SDLoc DL(Node);

1288 unsigned ArgAlignInBytes = ArgAlignment.value();

1290 unsigned VASizeInBytes = llvm::alignTo(ArgSizeInBytes, 4);

1291

1292

1294 DAG.getLoad(MVT::i32, DL, InChain, VAListPtr, MachinePointerInfo());

1295 InChain = VAStack.getValue(1);

1296

1297

1301 DAG.getLoad(MVT::i32, DL, InChain, VARegPtr, MachinePointerInfo());

1302 InChain = VAReg.getValue(1);

1303

1304

1305 SDValue VarArgIndexPtr =

1308 DAG.getLoad(MVT::i32, DL, InChain, VarArgIndexPtr, MachinePointerInfo());

1309 InChain = VAIndex.getValue(1);

1310

1311 SDValue OrigIndex = VAIndex;

1312

1313 if (ArgAlignInBytes > 4) {

1315 DAG.getConstant(ArgAlignInBytes - 1, DL, MVT::i32));

1316 OrigIndex =

1319 }

1320

1323

1326

1329 DAG.getConstant(32 + VASizeInBytes, DL, MVT::i32));

1330

1333

1335

1337

1340

1341 SDValue VAIndexStore = DAG.getStore(InChain, DL, VAIndex, VarArgIndexPtr,

1342 MachinePointerInfo(SV));

1343 InChain = VAIndexStore;

1344

1347

1349

1350 return DAG.getLoad(VT, DL, InChain, Addr, MachinePointerInfo());

1351}

1352

1353SDValue XtensaTargetLowering::LowerShiftLeftParts(SDValue Op,

1355 SDLoc DL(Op);

1356 MVT VT = MVT::i32;

1358 SDValue Shamt = Op.getOperand(2);

1359

1360

1361

1362

1363

1364

1365

1366

1368 SDValue ShamtMinusRegisterSize =

1370

1375

1379

1381}

1382

1383SDValue XtensaTargetLowering::LowerShiftRightParts(SDValue Op,

1385 bool IsSRA) const {

1386 SDLoc DL(Op);

1388 SDValue Shamt = Op.getOperand(2);

1389 MVT VT = MVT::i32;

1390

1391

1392

1393

1394

1395

1396

1397

1398

1399

1400

1401

1402

1403

1404

1405

1406

1410 SDValue ShamtMinusRegisterSize =

1412

1417 DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);

1419

1420 if (IsSRA) {

1421 HiFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, RegisterSizeMinus1);

1422 } else {

1423 HiFalse = Zero;

1424 }

1425

1429

1431}

1432

1436}

1437

1441 unsigned EltSizeInBits;

1442

1448 Imm = ConstNode->getAPIntValue();

1449 else

1450 return false;

1451 } else {

1452 return false;

1453 }

1454

1455

1456 if (EltSizeInBits > 32)

1457 return false;

1458

1459

1460 if (Imm.isPowerOf2() && Imm.isIntN(5))

1461 return true;

1462

1463 return false;

1464}

1465

1468 switch (Op.getOpcode()) {

1469 case ISD::BR_JT:

1470 return LowerBR_JT(Op, DAG);

1472 return LowerImmediate(Op, DAG);

1474 return LowerRETURNADDR(Op, DAG);

1476 return LowerGlobalAddress(Op, DAG);

1478 return LowerGlobalTLSAddress(Op, DAG);

1480 return LowerBlockAddress(Op, DAG);

1482 return LowerJumpTable(Op, DAG);

1484 return LowerCTPOP(Op, DAG);

1486 return LowerConstantPool(Op, DAG);

1488 return LowerSELECT_CC(Op, DAG);

1489 case ISD::STACKSAVE:

1490 return LowerSTACKSAVE(Op, DAG);

1491 case ISD::STACKRESTORE:

1492 return LowerSTACKRESTORE(Op, DAG);

1494 return LowerFRAMEADDR(Op, DAG);

1495 case ISD::DYNAMIC_STACKALLOC:

1496 return LowerDYNAMIC_STACKALLOC(Op, DAG);

1497 case ISD::VASTART:

1498 return LowerVASTART(Op, DAG);

1499 case ISD::VAARG:

1500 return LowerVAARG(Op, DAG);

1501 case ISD::VACOPY:

1502 return LowerVACOPY(Op, DAG);

1504 return LowerShiftLeftParts(Op, DAG);

1506 return LowerShiftRightParts(Op, DAG, true);

1508 return LowerShiftRightParts(Op, DAG, false);

1509 default:

1511 }

1512}

1513

1518

1519

1520

1521

1522

1528

1533

1534

1535

1536

1537

1538

1539

1540

1541

1542

1543

1544

1545

1546 const BasicBlock *LLVM_BB = MBB->getBasicBlock();

1548

1552

1553 F->insert(It, CopyMBB);

1554 F->insert(It, SinkMBB);

1555

1556

1560

1561 MBB->addSuccessor(CopyMBB);

1562 MBB->addSuccessor(SinkMBB);

1563

1564 if (MI.getOpcode() == Xtensa::SELECT_CC_FP_FP ||

1565 MI.getOpcode() == Xtensa::SELECT_CC_FP_INT) {

1566 unsigned CmpKind = MI.getOperand(5).getImm();

1567 unsigned BrKind = MI.getOperand(6).getImm();

1569

1571 .addReg(LHS.getReg())

1572 .addReg(RHS.getReg());

1576 } else {

1577 unsigned BrKind = MI.getOperand(5).getImm();

1582 }

1583

1585

1586

1587

1588

1589

1591 MI.getOperand(0).getReg())

1596

1597 MI.eraseFromParent();

1598 return SinkMBB;

1599}

1600

1605

1606 switch (MI.getOpcode()) {

1607 case Xtensa::BRCC_FP: {

1612 unsigned BrKind = 0;

1613 unsigned CmpKind = 0;

1616

1619 .addReg(LHS.getReg())

1620 .addReg(RHS.getReg());

1624

1625 MI.eraseFromParent();

1626 return MBB;

1627 }

1628 case Xtensa::SELECT_CC_FP_FP:

1629 case Xtensa::SELECT_CC_FP_INT:

1630 case Xtensa::SELECT_CC_INT_FP:

1631 case Xtensa::SELECT:

1632 return emitSelectCC(MI, MBB);

1633 case Xtensa::S8I:

1634 case Xtensa::S16I:

1635 case Xtensa::S32I:

1636 case Xtensa::S32I_N:

1637 case Xtensa::SSI:

1638 case Xtensa::SSIP:

1639 case Xtensa::SSX:

1640 case Xtensa::SSXP:

1641 case Xtensa::L8UI:

1642 case Xtensa::L16SI:

1643 case Xtensa::L16UI:

1644 case Xtensa::L32I:

1645 case Xtensa::L32I_N:

1646 case Xtensa::LSI:

1647 case Xtensa::LSIP:

1648 case Xtensa::LSX:

1649 case Xtensa::LSXP: {

1650

1651

1652

1653 if (MI.memoperands_empty() || (*MI.memoperands_begin())->isVolatile()) {

1655 }

1656 return MBB;

1657 }

1658 case Xtensa::MOVSP_P: {

1660

1663 MI.eraseFromParent();

1664

1665 return MBB;

1666 }

1667 case Xtensa::ATOMIC_CMP_SWAP_32_P: {

1672

1674 .addReg(Cmp.getReg());

1675

1680

1681 MI.eraseFromParent();

1682 return MBB;

1683 }

1684 default:

1686 }

1687}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Promote Memory to Register

static constexpr MCPhysReg SPReg

const SmallVectorImpl< MachineOperand > & Cond

SI optimize exec mask operations pre RA

static const MCPhysReg IntRegs[32]

static unsigned toCallerWindow(unsigned Reg)

static bool isLongCall(const char *str)

Definition XtensaISelLowering.cpp:41

static unsigned toCallerWindow(unsigned Reg)

Definition XtensaISelLowering.cpp:49

static std::pair< unsigned, unsigned > getFPBranchKind(ISD::CondCode Cond)

Definition XtensaISelLowering.cpp:856

static unsigned getBranchOpcode(ISD::CondCode Cond)

Definition XtensaISelLowering.cpp:829

static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

Definition XtensaISelLowering.cpp:349

Class for arbitrary precision integers.

int64_t getSExtValue() const

Get sign extended value.

an instruction that atomically reads a memory location, combines it with another value,...

LLVM Basic Block Representation.

CCState - This class holds information needed while lowering arguments and return values.

unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const

getFirstUnallocated - Return the index of the first unallocated register in the set,...

LLVM_ABI void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)

AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...

LLVM_ABI bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)

CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...

LLVM_ABI void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)

AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...

LLVM_ABI void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)

AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...

uint64_t getStackSize() const

Returns the size of the currently allocated portion of the stack.

LLVM_ABI void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)

AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...

CCValAssign - Represent assignment of one arg/retval to a location.

LocInfo getLocInfo() const

static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP, bool IsCustom=false)

static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)

int64_t getLocMemOffset() const

unsigned getValNo() const

const APInt & getAPIntValue() const

LLVM_ABI Align getABITypeAlign(Type *Ty) const

Returns the minimum ABI-required alignment for the specified type.

LLVM_ABI TypeSize getTypeAllocSize(Type *Ty) const

Returns the offset in bytes between successive objects of the specified type, including alignment pad...

LinkageTypes getLinkage() const

static bool isPrivateLinkage(LinkageTypes Linkage)

This is an important class for using LLVM in a threaded context.

LLVM_ABI void diagnose(const DiagnosticInfo &DI)

Report a message to the currently installed diagnostic handler.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Wrapper class representing physical registers. Should be passed by value.

static auto integer_valuetypes()

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

TypeSize getStoreSize() const

Return the number of bytes overwritten by a store of the specified value type.

LLVM_ABI void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)

Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...

LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

LLVM_ABI int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)

Create a new object at a fixed location on the stack.

void setFrameAddressIsTaken(bool T)

void setReturnAddressIsTaken(bool s)

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

BasicBlockListType::iterator iterator

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...

const MachineJumpTableInfo * getJumpTableInfo() const

getJumpTableInfo - Return the jump table info object for the current function.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

LLVM_ABI unsigned getEntrySize(const DataLayout &TD) const

getEntrySize - Return the size of each entry in the jump table.

MachineOperand class - Representation of each machine instruction operand.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

unsigned getOpcode() const

Return the SelectionDAG opcode value for this node.

bool hasOneUse() const

Return true if there is exactly one use of this node.

user_iterator user_begin() const

Provide iteration support to walk over all users of an SDNode.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SDNode * getNode() const

get the SDNode which holds the desired result

SDValue getValue(unsigned R) const

EVT getValueType() const

Return the ValueType of the referenced return value.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)

LLVM_ABI SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)

Create a MERGE_VALUES node from the given operands.

LLVM_ABI SDVTList getVTList(EVT VT)

Return an SDVTList that represents the list of values specified.

LLVM_ABI SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)

SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)

Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...

LLVM_ABI SDValue getRegister(Register Reg, EVT VT)

LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)

Loads are not normal binary operators: their result type is not determined by their operands,...

LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)

const TargetLowering & getTargetLoweringInfo() const

SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)

SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)

Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).

SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)

const DataLayout & getDataLayout() const

LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

Helper function to build ISD::STORE nodes.

LLVM_ABI SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)

Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...

const TargetMachine & getTarget() const

LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)

LLVM_ABI SDValue getValueType(EVT)

LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

MachineFunction & getMachineFunction() const

SDValue getPOISON(EVT VT)

Return a POISON node. POISON does not have a useful SDLoc.

LLVM_ABI SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)

LLVM_ABI SDValue getRegisterMask(const uint32_t *RegMask)

SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)

Create an add instruction with appropriate flags when used for addressing some offset of an object.

LLVMContext * getContext() const

LLVM_ABI SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)

SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)

SDValue getEntryNode() const

Return the token chain corresponding to the entry of the function.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

constexpr size_t size() const

size - Get the string size.

Information about stack frame layout on the target.

Align getStackAlign() const

getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...

TargetInstrInfo - Interface to description of machine instruction set.

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const

Return the register class that should be used for the specified value type.

const TargetMachine & getTargetMachine() const

virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)

Set the maximum atomic operation size supported by the backend.

void setMinFunctionAlignment(Align Alignment)

Set the target's minimum function alignment.

void setBooleanContents(BooleanContent Ty)

Specify how the target extends the result of integer and floating point boolean values from i1 to a w...

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

void addRegisterClass(MVT VT, const TargetRegisterClass *RC)

Add the specified register class as an available regclass for the specified value type.

bool isTypeLegal(EVT VT) const

Return true if the target has native support for the specified value type.

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

@ ZeroOrOneBooleanContent

void setMinCmpXchgSizeInBits(unsigned SizeInBits)

Sets the minimum cmpxchg or ll/sc size supported by the backend.

void setStackPointerRegisterToSaveRestore(Register R)

If set to a physical register, this specifies the register that llvm.savestack/llvm....

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)

Indicate that the specified condition code is or isn't supported on the target and indicate what to d...

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

MVT getFrameIndexTy(const DataLayout &DL) const

Return the type for frame index, which is determined by the alloca address space specified through th...

void setSchedulingPreference(Sched::Preference Pref)

Specify the target scheduling preference.

virtual ConstraintType getConstraintType(StringRef Constraint) const

Given a constraint, return the type of constraint it is for this target.

virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const

Lower TLS global address SDNode for target independent emulated TLS model.

SDValue expandCTPOP(SDNode *N, SelectionDAG &DAG) const

Expand CTPOP nodes.

bool isPositionIndependent() const

virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const

Examine constraint string and operand type and determine a weight value.

virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const

Given a physical register constraint (e.g.

TargetLowering(const TargetLowering &)=delete

virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const

Lower the specified operand into the Ops vector.

Primary interface to the complete machine description for the target machine.

TLSModel::Model getTLSModel(const GlobalValue *GV) const

Returns the TLS model which should be used for the given global variable.

bool useEmulatedTLS() const

Returns true if this target uses emulated TLS.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

static constexpr TypeSize getFixed(ScalarTy ExactSize)

The instances of the Type class are immutable: once they are created, they are never changed.

static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

LLVM_ABI StringRef getName() const

Return a constant reference to the value's name.

static XtensaConstantPoolConstant * Create(const Constant *C, unsigned ID, XtensaCP::XtensaCPKind Kind)

static XtensaConstantPoolJumpTable * Create(LLVMContext &C, unsigned Idx)

static XtensaConstantPoolSymbol * Create(LLVMContext &C, const char *S, unsigned ID, bool PrivLinkage, XtensaCP::XtensaCPModifier Modifier=XtensaCP::no_modifier)

XtensaConstantPoolValue - Xtensa specific constantpool value.

unsigned createCPLabelId()

int getVarArgsInRegsFrameIndex() const

void setVarArgsFirstGPR(unsigned GPR)

void setSaveFrameRegister()

int getVarArgsOnStackFrameIndex() const

unsigned getVarArgsFirstGPR() const

void setVarArgsInRegsFrameIndex(int FI)

void setVarArgsOnStackFrameIndex(int FI)

const XtensaInstrInfo * getInstrInfo() const override

const XtensaRegisterInfo * getRegisterInfo() const override

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

Definition XtensaISelLowering.cpp:773

TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override

Examine constraint string and operand type and determine a weight value.

Definition XtensaISelLowering.cpp:289

TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override

Given a constraint, return the type of constraint it is for this target.

Definition XtensaISelLowering.cpp:276

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

Definition XtensaISelLowering.cpp:261

bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override

Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...

Definition XtensaISelLowering.cpp:1438

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

Definition XtensaISelLowering.cpp:1601

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

Definition XtensaISelLowering.cpp:438

SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

Definition XtensaISelLowering.cpp:585

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

Definition XtensaISelLowering.cpp:267

XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI)

Definition XtensaISelLowering.cpp:55

AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Definition XtensaISelLowering.cpp:1515

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

Lower the specified operand into the Ops vector.

Definition XtensaISelLowering.cpp:328

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

Definition XtensaISelLowering.cpp:314

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

Definition XtensaISelLowering.cpp:783

MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Return the register type for a given MVT.

Definition XtensaISelLowering.cpp:424

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

Definition XtensaISelLowering.cpp:1466

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Align[]

Key for Kernel::Arg::Metadata::mAlign.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ SMUL_LOHI

SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...

@ BSWAP

Byte Swap and Counting operators.

@ ADD

Simple integer binary arithmetic operators.

@ FMA

FMA - Perform a * b + c with no intermediate rounding step.

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ FADD

Simple binary floating point operators.

@ SDIVREM

SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.

@ CTTZ_ZERO_UNDEF

Bit counting operators with an undefined result for zero inputs.

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ MULHU

MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...

@ SHL

Shift and rotation operations.

@ SELECT_CC

Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

@ FRAMEADDR

FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ TokenFactor

TokenFactor - This node takes multiple tokens as input and produces a single token result.

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ SHL_PARTS

SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.

@ AssertSext

AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

LLVM_ABI bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)

Node predicates.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

@ Kill

The last use of a register.

NodeAddr< NodeBase * > Node

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

unsigned Log2_32(uint32_t Value)

Return the floor log base 2 of the specified value, -1 if the value is zero.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

DWARFExpression::Operation Op

constexpr bool isShiftedInt(int64_t x)

Checks if a signed integer is an N bit number shifted left by S.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

This struct is a compact representation of a valid (non-zero power of two) alignment.

constexpr uint64_t value() const

This is a hole in the type system and should not be abused.

TypeSize getStoreSize() const

Return the number of bytes overwritten by a store of the specified value type.

bool isFloatingPoint() const

Return true if this is a FP or a vector FP type.

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

uint64_t getScalarSizeInBits() const

LLVM_ABI Type * getTypeForEVT(LLVMContext &Context) const

This method returns an LLVM type corresponding to the specified EVT.

bool isScalarInteger() const

Return true if this is an integer, but not a vector.

Align getNonZeroOrigAlign() const

unsigned getByValSize() const

Align getNonZeroByValAlign() const

This class contains a discriminated union of information about pointers in memory operands,...

static LLVM_ABI MachinePointerInfo getJumpTable(MachineFunction &MF)

Return a MachinePointerInfo record that refers to a jump table entry.

static LLVM_ABI MachinePointerInfo getConstantPool(MachineFunction &MF)

Return a MachinePointerInfo record that refers to the constant pool.

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

This represents a list of ValueType's that has been intern'd by a SelectionDAG.

This contains information for each constraint that we are lowering.

This structure contains all information that is necessary for lowering calls.

SmallVector< ISD::InputArg, 32 > Ins

SmallVector< ISD::OutputArg, 32 > Outs

SmallVector< SDValue, 32 > OutVals