LLVM: lib/Target/Hexagon/HexagonInstrInfo.cpp Source File (original) (raw)
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55#include
56#include
57#include
58#include
59#include
60#include
61#include
62#include
63
64using namespace llvm;
65
66#define DEBUG_TYPE "hexagon-instrinfo"
67
68#define GET_INSTRINFO_CTOR_DTOR
69#define GET_INSTRMAP_INFO
71#include "HexagonGenDFAPacketizer.inc"
72#include "HexagonGenInstrInfo.inc"
73
75 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
76 "packetization boundary."));
77
80
82 "disable-hexagon-nv-schedule", cl::Hidden,
83 cl::desc("Disable schedule adjustment for new value stores."));
84
87 cl::desc("Enable timing class latency"));
88
91 cl::desc("Enable vec alu forwarding"));
92
95 cl::desc("Enable vec acc forwarding"));
96
99 cl::desc("branch relax asm"));
100
103 cl::desc("Use the DFA based hazard recognizer."));
104
105
116
117
118void HexagonInstrInfo::anchor() {}
119
121 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
122 Subtarget(ST) {}
123
124namespace llvm {
125namespace HexagonFUnits {
127}
128}
129
131 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
132 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
133}
134
138}
139
140
143 unsigned Count = 0;
144 for (; MIB != MIE; ++MIB) {
145 if (!MIB->isDebugInstr())
146 ++Count;
147 }
148 return Count;
149}
150
151
152
153
155
156 if (!(MI.getMF()->getFunction().hasOptSize()))
157 return MI.isAsCheapAsAMove();
158
159 if (MI.getOpcode() == Hexagon::A2_tfrsi) {
160 auto Op = MI.getOperand(1);
161
162
163 if (Op.isGlobal())
164 return false;
165
166
167 if (Op.isImm()) {
168 int64_t Imm = Op.getImm();
169 if (!isInt<16>(Imm))
170 return false;
171 }
172 }
173 return MI.isAsCheapAsAMove();
174}
175
176
177
178
179
180
181
182
183
184
186
187
188 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
189 return false;
190 return true;
191}
192
193
194
195
196
200 unsigned LOOPi;
201 unsigned LOOPr;
202 if (EndLoopOp == Hexagon::ENDLOOP0) {
203 LOOPi = Hexagon::J2_loop0i;
204 LOOPr = Hexagon::J2_loop0r;
205 } else {
206 LOOPi = Hexagon::J2_loop1i;
207 LOOPr = Hexagon::J2_loop1r;
208 }
209
210
212
213 if (!Visited.insert(PB).second)
214 continue;
215 if (PB == BB)
216 continue;
218 unsigned Opc = I.getOpcode();
219 if (Opc == LOOPi || Opc == LOOPr)
220 return &I;
221
222
223 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
224 return nullptr;
225 }
226
229 }
230 return nullptr;
231}
232
233
234
235
239 Uses.clear();
240
242 if (!MO.isReg())
243 continue;
244
246 if (!Reg)
247 continue;
248
249 if (MO.isUse())
250 Uses.push_back(MO.getReg());
251
252 if (MO.isDef())
254 }
255}
256
257
259 switch (Ga) {
261 default:
262 return false;
279 }
280 return false;
281}
282
283
284
285
286
287
289 int &FrameIndex) const {
290 switch (MI.getOpcode()) {
291 default:
292 break;
293 case Hexagon::L2_loadri_io:
294 case Hexagon::L2_loadrd_io:
295 case Hexagon::V6_vL32b_ai:
296 case Hexagon::V6_vL32b_nt_ai:
297 case Hexagon::V6_vL32Ub_ai:
298 case Hexagon::LDriw_pred:
299 case Hexagon::LDriw_ctr:
300 case Hexagon::PS_vloadrq_ai:
301 case Hexagon::PS_vloadrw_ai:
302 case Hexagon::PS_vloadrw_nt_ai: {
304 if (!OpFI.isFI())
305 return 0;
307 if (!OpOff.isImm() || OpOff.getImm() != 0)
308 return 0;
309 FrameIndex = OpFI.getIndex();
310 return MI.getOperand(0).getReg();
311 }
312
313 case Hexagon::L2_ploadrit_io:
314 case Hexagon::L2_ploadrif_io:
315 case Hexagon::L2_ploadrdt_io:
316 case Hexagon::L2_ploadrdf_io: {
318 if (!OpFI.isFI())
319 return 0;
321 if (!OpOff.isImm() || OpOff.getImm() != 0)
322 return 0;
323 FrameIndex = OpFI.getIndex();
324 return MI.getOperand(0).getReg();
325 }
326 }
327
328 return 0;
329}
330
331
332
333
334
335
337 int &FrameIndex) const {
338 switch (MI.getOpcode()) {
339 default:
340 break;
341 case Hexagon::S2_storerb_io:
342 case Hexagon::S2_storerh_io:
343 case Hexagon::S2_storeri_io:
344 case Hexagon::S2_storerd_io:
345 case Hexagon::V6_vS32b_ai:
346 case Hexagon::V6_vS32Ub_ai:
347 case Hexagon::STriw_pred:
348 case Hexagon::STriw_ctr:
349 case Hexagon::PS_vstorerq_ai:
350 case Hexagon::PS_vstorerw_ai: {
352 if (!OpFI.isFI())
353 return 0;
355 if (!OpOff.isImm() || OpOff.getImm() != 0)
356 return 0;
357 FrameIndex = OpFI.getIndex();
358 return MI.getOperand(2).getReg();
359 }
360
361 case Hexagon::S2_pstorerbt_io:
362 case Hexagon::S2_pstorerbf_io:
363 case Hexagon::S2_pstorerht_io:
364 case Hexagon::S2_pstorerhf_io:
365 case Hexagon::S2_pstorerit_io:
366 case Hexagon::S2_pstorerif_io:
367 case Hexagon::S2_pstorerdt_io:
368 case Hexagon::S2_pstorerdf_io: {
370 if (!OpFI.isFI())
371 return 0;
373 if (!OpOff.isImm() || OpOff.getImm() != 0)
374 return 0;
375 FrameIndex = OpFI.getIndex();
376 return MI.getOperand(3).getReg();
377 }
378 }
379
380 return 0;
381}
382
383
384
385
389 if (MI.isBundle()) {
392 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
394 return true;
395 return false;
396 }
397
399}
400
401
402
403
407 if (MI.isBundle()) {
410 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
412 return true;
413 return false;
414 }
415
417}
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
438 bool AllowModify) const {
439 TBB = nullptr;
440 FBB = nullptr;
441 Cond.clear();
442
443
446 return false;
447
448
449
450
451
452
453
454
455
456
457
458
459
460 do {
461 --I;
462 if (I->isEHLabel())
463
464 return true;
466
468 --I;
469
470 while (I->isDebugInstr()) {
472 return false;
473 --I;
474 }
475
476 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
477 I->getOperand(0).isMBB();
478
479 if (AllowModify && JumpToBlock &&
481 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
482 I->eraseFromParent();
485 return false;
486 --I;
487 }
488 if (!isUnpredicatedTerminator(*I))
489 return false;
490
491
494
495 while (true) {
496 if (&*I != LastInst && ->isBundle() && isUnpredicatedTerminator(*I)) {
497 if (!SecondLastInst)
498 SecondLastInst = &*I;
499 else
500
501 return true;
502 }
504 break;
505 --I;
506 }
507
508 int LastOpcode = LastInst->getOpcode();
509 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
510
511
512 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
513 return true;
514 if (SecLastOpcode == Hexagon::J2_jump &&
516 return true;
517
519 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
520
521 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
522 return true;
523
524
525 if (LastInst && !SecondLastInst) {
526 if (LastOpcode == Hexagon::J2_jump) {
528 return false;
529 }
534 return false;
535 }
536 if (LastOpcodeHasJMP_c) {
540 return false;
541 }
542
548 return false;
549 }
551 << " with one jump\n";);
552
553 return true;
554 }
555
557 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
558 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
560 return true;
565 return false;
566 }
567
568
569 if (SecLastOpcodeHasNVJump &&
571 (LastOpcode == Hexagon::J2_jump)) {
577 return false;
578 }
579
580
581
582 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
585 if (AllowModify)
586 I->eraseFromParent();
587 return false;
588 }
589
590
591 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
596 return false;
597 }
599 << " with two jumps";);
600
601 return true;
602}
603
605 int *BytesRemoved) const {
606 assert(!BytesRemoved && "code size not handled");
607
610 unsigned Count = 0;
612 --I;
613 if (I->isDebugInstr())
614 continue;
615
616 if (->isBranch())
617 return Count;
618 if (Count && (I->getOpcode() == Hexagon::J2_jump))
619 llvm_unreachable("Malformed basic block: unconditional branch not last");
622 ++Count;
623 }
624 return Count;
625}
626
632 int *BytesAdded) const {
633 unsigned BOpc = Hexagon::J2_jump;
634 unsigned BccOpc = Hexagon::J2_jumpt;
636 assert(TBB && "insertBranch must not be told to insert a fallthrough");
637 assert(!BytesAdded && "code size not handled");
638
639
640
641
642 if (.empty() && Cond[0].isImm())
643 BccOpc = Cond[0].getImm();
644
645 if (!FBB) {
646 if (Cond.empty()) {
647
648
649
650
660 }
663 int EndLoopOp = Cond[0].getImm();
665
666
669 VisitedBBs);
670 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
671 Loop->getOperand(0).setMBB(TBB);
672
675 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
676
677
678
689 } else
691 } else {
692 assert((Cond.size() == 2) && "Malformed cond vector");
696 }
697 return 1;
698 }
700 "Cond. cannot be empty when multiple branchings are required");
702 "NV-jump cannot be inserted with another branch");
703
705 int EndLoopOp = Cond[0].getImm();
707
708
711 VisitedBBs);
712 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
713 Loop->getOperand(0).setMBB(TBB);
714
716 } else {
720 }
722
723 return 2;
724}
725
726namespace {
731 int64_t TripCount;
734
735public:
740
741
742 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
743 ? -1
744 : Loop->getOperand(1).getImm();
745 if (TripCount == -1)
746 LoopCount = Loop->getOperand(1).getReg();
747 }
748
749 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
750
751 return MI == EndLoop;
752 }
753
754 std::optional createTripCountGreaterCondition(
757 if (TripCount == -1) {
758
761 TII->get(Hexagon::C2_cmpgtui), Done)
766 return {};
767 }
768
769 return TripCount > TC;
770 }
771
775 }
776
777 void adjustTripCount(int TripCountAdjust) override {
778
779
780 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
781 Loop->getOpcode() == Hexagon::J2_loop1i) {
782 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
783 assert(TripCount > 0 && "Can't create an empty or negative loop!");
784 Loop->getOperand(1).setImm(TripCount);
785 return;
786 }
787
788
789
790 Register LoopCount = Loop->getOperand(1).getReg();
793 TII->get(Hexagon::A2_addi), NewLoopCount)
795 .addImm(TripCountAdjust);
796 Loop->getOperand(1).setReg(NewLoopCount);
797 }
798
800 if (LIS)
802 Loop->eraseFromParent();
803 }
804};
805}
806
807std::unique_ptrTargetInstrInfo::PipelinerLoopInfo
809
811
815 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
816 if (LoopInst)
817 return std::make_unique(LoopInst, &*I);
818 }
819 return nullptr;
820}
821
823 unsigned NumCycles, unsigned ExtraPredCycles,
826}
827
829 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
830 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
831 const {
833}
834
837 return NumInstrs <= 4;
838}
839
845 for (auto I = B.begin(); I != E; ++I) {
846 Clobbers.clear();
848 }
849}
850
855 for (auto I = B.rbegin(); I != E; ++I)
857}
858
863 bool RenamableDest,
864 bool RenamableSrc) const {
867
868 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
870 .addReg(SrcReg, KillFlag);
871 return;
872 }
873 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
875 .addReg(SrcReg, KillFlag);
876 return;
877 }
878 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
879
882 return;
883 }
884 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
885 Hexagon::IntRegsRegClass.contains(SrcReg)) {
887 .addReg(SrcReg, KillFlag);
888 return;
889 }
890 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
891 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
893 .addReg(SrcReg, KillFlag);
894 return;
895 }
896 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
897 Hexagon::IntRegsRegClass.contains(SrcReg)) {
899 .addReg(SrcReg, KillFlag);
900 return;
901 }
902 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
903 Hexagon::IntRegsRegClass.contains(DestReg)) {
905 .addReg(SrcReg, KillFlag);
906 return;
907 }
908 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
909 Hexagon::PredRegsRegClass.contains(DestReg)) {
911 .addReg(SrcReg, KillFlag);
912 return;
913 }
914 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
915 Hexagon::IntRegsRegClass.contains(DestReg)) {
917 .addReg(SrcReg, KillFlag);
918 return;
919 }
920 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
922 addReg(SrcReg, KillFlag);
923 return;
924 }
925 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
928 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
929 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
933 .addReg(SrcHi, KillFlag | UndefHi)
934 .addReg(SrcLo, KillFlag | UndefLo);
935 return;
936 }
937 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
940 .addReg(SrcReg, KillFlag);
941 return;
942 }
943 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
944 Hexagon::HvxVRRegClass.contains(DestReg)) {
946 return;
947 }
948 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
949 Hexagon::HvxVRRegClass.contains(SrcReg)) {
951 return;
952 }
953
954#ifndef NDEBUG
955
957 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
958#endif
960}
961
964 Register SrcReg, bool isKill, int FI,
973
977
978 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
982 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
986 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
990 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
994 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
998 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1002 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1006 } else {
1008 }
1009}
1010
1018
1022
1023 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1026 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1029 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1032 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1035 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1038 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1041 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1044 } else {
1045 llvm_unreachable("Can't store this register to stack slot");
1046 }
1047}
1048
1049
1050
1051
1052
1053
1054
1062 unsigned Opc = MI.getOpcode();
1063
1064 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1065 Register Mx = MI.getOperand(MxOp).getReg();
1066 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1068 .add(MI.getOperand((HasImm ? 5 : 4)));
1070 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1071 if (HasImm)
1072 MIB.add(MI.getOperand(4));
1075 return true;
1076 };
1077
1079 if (MI.memoperands().empty())
1080 return false;
1082 return MMO->getAlign() >= NeedAlign;
1083 });
1084 };
1085
1086 switch (Opc) {
1087 case Hexagon::PS_call_instrprof_custom: {
1088 auto Op0 = MI.getOperand(0);
1089 assert(Op0.isGlobal() &&
1090 "First operand must be a global containing handler name.");
1091 const GlobalValue *NameVar = Op0.getGlobal();
1092 const GlobalVariable *GV = dyn_cast(NameVar);
1093 auto *Arr = cast(GV->getInitializer());
1094 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1095
1097
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1120 MIB.addExternalSymbol(cstr);
1122 return true;
1123 }
1124 case TargetOpcode::COPY: {
1131 }
1133 return true;
1134 }
1135 case Hexagon::PS_aligna:
1138 .addImm(-MI.getOperand(1).getImm());
1140 return true;
1141 case Hexagon::V6_vassignp: {
1142 Register SrcReg = MI.getOperand(1).getReg();
1143 Register DstReg = MI.getOperand(0).getReg();
1144 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1145 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1147 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1148 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1151 .addReg(SrcHi, UndefHi)
1152 .addReg(SrcLo, Kill | UndefLo);
1154 return true;
1155 }
1156 case Hexagon::V6_lo: {
1157 Register SrcReg = MI.getOperand(1).getReg();
1158 Register DstReg = MI.getOperand(0).getReg();
1159 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1162 MRI.clearKillFlags(SrcSubLo);
1163 return true;
1164 }
1165 case Hexagon::V6_hi: {
1166 Register SrcReg = MI.getOperand(1).getReg();
1167 Register DstReg = MI.getOperand(0).getReg();
1168 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1171 MRI.clearKillFlags(SrcSubHi);
1172 return true;
1173 }
1174 case Hexagon::PS_vloadrv_ai: {
1175 Register DstReg = MI.getOperand(0).getReg();
1178 int Offset = MI.getOperand(2).getImm();
1179 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1180 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1181 : Hexagon::V6_vL32Ub_ai;
1187 return true;
1188 }
1189 case Hexagon::PS_vloadrw_ai: {
1190 Register DstReg = MI.getOperand(0).getReg();
1193 int Offset = MI.getOperand(2).getImm();
1194 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1195 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1196 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1197 : Hexagon::V6_vL32Ub_ai;
1199 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1204 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1209 return true;
1210 }
1211 case Hexagon::PS_vstorerv_ai: {
1216 int Offset = MI.getOperand(1).getImm();
1217 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1218 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1219 : Hexagon::V6_vS32Ub_ai;
1226 return true;
1227 }
1228 case Hexagon::PS_vstorerw_ai: {
1229 Register SrcReg = MI.getOperand(2).getReg();
1232 int Offset = MI.getOperand(1).getImm();
1233 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1234 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1235 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1236 : Hexagon::V6_vS32Ub_ai;
1240 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1245 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1248 return true;
1249 }
1250 case Hexagon::PS_true: {
1251 Register Reg = MI.getOperand(0).getReg();
1256 return true;
1257 }
1258 case Hexagon::PS_false: {
1259 Register Reg = MI.getOperand(0).getReg();
1264 return true;
1265 }
1266 case Hexagon::PS_qtrue: {
1271 return true;
1272 }
1273 case Hexagon::PS_qfalse: {
1278 return true;
1279 }
1280 case Hexagon::PS_vdd0: {
1281 Register Vd = MI.getOperand(0).getReg();
1286 return true;
1287 }
1288 case Hexagon::PS_vmulw: {
1289
1290 Register DstReg = MI.getOperand(0).getReg();
1291 Register Src1Reg = MI.getOperand(1).getReg();
1292 Register Src2Reg = MI.getOperand(2).getReg();
1293 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1294 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1295 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1296 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1298 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1302 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1306 MRI.clearKillFlags(Src1SubHi);
1307 MRI.clearKillFlags(Src1SubLo);
1308 MRI.clearKillFlags(Src2SubHi);
1309 MRI.clearKillFlags(Src2SubLo);
1310 return true;
1311 }
1312 case Hexagon::PS_vmulw_acc: {
1313
1314 Register DstReg = MI.getOperand(0).getReg();
1315 Register Src1Reg = MI.getOperand(1).getReg();
1316 Register Src2Reg = MI.getOperand(2).getReg();
1317 Register Src3Reg = MI.getOperand(3).getReg();
1318 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1319 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1320 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1321 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1322 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1323 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1325 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1330 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1335 MRI.clearKillFlags(Src1SubHi);
1336 MRI.clearKillFlags(Src1SubLo);
1337 MRI.clearKillFlags(Src2SubHi);
1338 MRI.clearKillFlags(Src2SubLo);
1339 MRI.clearKillFlags(Src3SubHi);
1340 MRI.clearKillFlags(Src3SubLo);
1341 return true;
1342 }
1343 case Hexagon::PS_pselect: {
1356 if (Rd != Rs)
1358 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1360 if (Rd != Rt)
1365 return true;
1366 }
1367 case Hexagon::PS_vselect: {
1377
1379 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1380 : PState;
1382 .add(Op0)
1384 .add(Op2);
1385 if (IsDestLive)
1387 IsDestLive = true;
1388 }
1391 .add(Op0)
1392 .addReg(PReg, PState)
1393 .add(Op3);
1394 if (IsDestLive)
1396 }
1398 return true;
1399 }
1400 case Hexagon::PS_wselect: {
1410
1412 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1413 : PState;
1414 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1415 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1417 .add(Op0)
1421 if (IsDestLive)
1423 IsDestLive = true;
1424 }
1426 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1427 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1429 .add(Op0)
1430 .addReg(PReg, PState)
1433 if (IsDestLive)
1435 }
1437 return true;
1438 }
1439
1440 case Hexagon::PS_crash: {
1441
1443 public:
1446
1448 return false;
1449 }
1451 return false;
1452 }
1454 return false;
1455 }
1456 void printCustom(raw_ostream &OS) const override {
1457 OS << "MisalignedCrash";
1458 }
1459 };
1460
1461 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1467 .addImm(0xBADC0FEE)
1470 return true;
1471 }
1472
1473 case Hexagon::PS_tailcall_i:
1474 MI.setDesc(get(Hexagon::J2_jump));
1475 return true;
1476 case Hexagon::PS_tailcall_r:
1477 case Hexagon::PS_jmpret:
1478 MI.setDesc(get(Hexagon::J2_jumpr));
1479 return true;
1480 case Hexagon::PS_jmprett:
1481 MI.setDesc(get(Hexagon::J2_jumprt));
1482 return true;
1483 case Hexagon::PS_jmpretf:
1484 MI.setDesc(get(Hexagon::J2_jumprf));
1485 return true;
1486 case Hexagon::PS_jmprettnewpt:
1487 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1488 return true;
1489 case Hexagon::PS_jmpretfnewpt:
1490 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1491 return true;
1492 case Hexagon::PS_jmprettnew:
1493 MI.setDesc(get(Hexagon::J2_jumprtnew));
1494 return true;
1495 case Hexagon::PS_jmpretfnew:
1496 MI.setDesc(get(Hexagon::J2_jumprfnew));
1497 return true;
1498
1499 case Hexagon::PS_loadrub_pci:
1500 return RealCirc(Hexagon::L2_loadrub_pci, true, 4);
1501 case Hexagon::PS_loadrb_pci:
1502 return RealCirc(Hexagon::L2_loadrb_pci, true, 4);
1503 case Hexagon::PS_loadruh_pci:
1504 return RealCirc(Hexagon::L2_loadruh_pci, true, 4);
1505 case Hexagon::PS_loadrh_pci:
1506 return RealCirc(Hexagon::L2_loadrh_pci, true, 4);
1507 case Hexagon::PS_loadri_pci:
1508 return RealCirc(Hexagon::L2_loadri_pci, true, 4);
1509 case Hexagon::PS_loadrd_pci:
1510 return RealCirc(Hexagon::L2_loadrd_pci, true, 4);
1511 case Hexagon::PS_loadrub_pcr:
1512 return RealCirc(Hexagon::L2_loadrub_pcr, false, 3);
1513 case Hexagon::PS_loadrb_pcr:
1514 return RealCirc(Hexagon::L2_loadrb_pcr, false, 3);
1515 case Hexagon::PS_loadruh_pcr:
1516 return RealCirc(Hexagon::L2_loadruh_pcr, false, 3);
1517 case Hexagon::PS_loadrh_pcr:
1518 return RealCirc(Hexagon::L2_loadrh_pcr, false, 3);
1519 case Hexagon::PS_loadri_pcr:
1520 return RealCirc(Hexagon::L2_loadri_pcr, false, 3);
1521 case Hexagon::PS_loadrd_pcr:
1522 return RealCirc(Hexagon::L2_loadrd_pcr, false, 3);
1523 case Hexagon::PS_storerb_pci:
1524 return RealCirc(Hexagon::S2_storerb_pci, true, 3);
1525 case Hexagon::PS_storerh_pci:
1526 return RealCirc(Hexagon::S2_storerh_pci, true, 3);
1527 case Hexagon::PS_storerf_pci:
1528 return RealCirc(Hexagon::S2_storerf_pci, true, 3);
1529 case Hexagon::PS_storeri_pci:
1530 return RealCirc(Hexagon::S2_storeri_pci, true, 3);
1531 case Hexagon::PS_storerd_pci:
1532 return RealCirc(Hexagon::S2_storerd_pci, true, 3);
1533 case Hexagon::PS_storerb_pcr:
1534 return RealCirc(Hexagon::S2_storerb_pcr, false, 2);
1535 case Hexagon::PS_storerh_pcr:
1536 return RealCirc(Hexagon::S2_storerh_pcr, false, 2);
1537 case Hexagon::PS_storerf_pcr:
1538 return RealCirc(Hexagon::S2_storerf_pcr, false, 2);
1539 case Hexagon::PS_storeri_pcr:
1540 return RealCirc(Hexagon::S2_storeri_pcr, false, 2);
1541 case Hexagon::PS_storerd_pcr:
1542 return RealCirc(Hexagon::S2_storerd_pcr, false, 2);
1543 }
1544
1545 return false;
1546}
1547
1552 unsigned Opc = MI.getOpcode();
1554
1555 switch (Opc) {
1556 case Hexagon::V6_vgathermh_pseudo:
1563 .addImm(MI.getOperand(1).getImm())
1564 .addReg(Hexagon::VTMP);
1566 return First.getInstrIterator();
1567
1568 case Hexagon::V6_vgathermw_pseudo:
1575 .addImm(MI.getOperand(1).getImm())
1576 .addReg(Hexagon::VTMP);
1578 return First.getInstrIterator();
1579
1580 case Hexagon::V6_vgathermhw_pseudo:
1587 .addImm(MI.getOperand(1).getImm())
1588 .addReg(Hexagon::VTMP);
1590 return First.getInstrIterator();
1591
1592 case Hexagon::V6_vgathermhq_pseudo:
1600 .addImm(MI.getOperand(1).getImm())
1601 .addReg(Hexagon::VTMP);
1603 return First.getInstrIterator();
1604
1605 case Hexagon::V6_vgathermwq_pseudo:
1613 .addImm(MI.getOperand(1).getImm())
1614 .addReg(Hexagon::VTMP);
1616 return First.getInstrIterator();
1617
1618 case Hexagon::V6_vgathermhwq_pseudo:
1626 .addImm(MI.getOperand(1).getImm())
1627 .addReg(Hexagon::VTMP);
1629 return First.getInstrIterator();
1630 }
1631
1632 return MI.getIterator();
1633}
1634
1635
1636
1639 if (Cond.empty())
1640 return true;
1641 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1642 unsigned opcode = Cond[0].getImm();
1643
1644 assert(get(opcode).isBranch() && "Should be a branching condition.");
1646 return true;
1648 Cond[0].setImm(NewOpcode);
1649 return false;
1650}
1651
1656}
1657
1660}
1661
1662
1663
1664
1665
1666
1667
1668
1669
1671 const uint64_t F = MI.getDesc().TSFlags;
1673}
1674
1680 return false;
1681 }
1682 int Opc = MI.getOpcode();
1685
1686
1687
1688
1689
1690
1693 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1695 unsigned NOp = 0, NumOps = MI.getNumOperands();
1696 while (NOp < NumOps) {
1698 if (.isReg() ||
.isDef() || Op.isImplicit())
1699 break;
1701 NOp++;
1702 }
1703
1705 unsigned PredRegPos, PredRegFlags;
1706 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1707 (void)GotPredReg;
1709 T.addReg(PredReg, PredRegFlags);
1710 while (NOp < NumOps)
1711 T.add(MI.getOperand(NOp++));
1712
1713 MI.setDesc(get(PredOpc));
1714 while (unsigned n = MI.getNumOperands())
1715 MI.removeOperand(n-1);
1716 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1717 MI.addOperand(T->getOperand(i));
1718
1720 B.erase(TI);
1721
1723 MRI.clearKillFlags(PredReg);
1724 return true;
1725}
1726
1729
1730 return false;
1731}
1732
1734 std::vector &Pred,
1735 bool SkipDead) const {
1737
1739 if (MO.isReg()) {
1740 if (!MO.isDef())
1741 continue;
1742 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1743 if (RC == &Hexagon::PredRegsRegClass) {
1744 Pred.push_back(MO);
1745 return true;
1746 }
1747 continue;
1748 } else if (MO.isRegMask()) {
1749 for (Register PR : Hexagon::PredRegsRegClass) {
1750 if (.modifiesRegister(PR, &HRI))
1751 continue;
1752 Pred.push_back(MO);
1753 return true;
1754 }
1755 }
1756 }
1757 return false;
1758}
1759
1761 if (.getDesc().isPredicable())
1762 return false;
1763
1766 return false;
1767 }
1768
1769
1771 switch (MI.getOpcode()) {
1772 case Hexagon::V6_vL32b_ai:
1773 case Hexagon::V6_vL32b_pi:
1774 case Hexagon::V6_vL32b_ppu:
1775 case Hexagon::V6_vL32b_cur_ai:
1776 case Hexagon::V6_vL32b_cur_pi:
1777 case Hexagon::V6_vL32b_cur_ppu:
1778 case Hexagon::V6_vL32b_nt_ai:
1779 case Hexagon::V6_vL32b_nt_pi:
1780 case Hexagon::V6_vL32b_nt_ppu:
1781 case Hexagon::V6_vL32b_tmp_ai:
1782 case Hexagon::V6_vL32b_tmp_pi:
1783 case Hexagon::V6_vL32b_tmp_ppu:
1784 case Hexagon::V6_vL32b_nt_cur_ai:
1785 case Hexagon::V6_vL32b_nt_cur_pi:
1786 case Hexagon::V6_vL32b_nt_cur_ppu:
1787 case Hexagon::V6_vL32b_nt_tmp_ai:
1788 case Hexagon::V6_vL32b_nt_tmp_pi:
1789 case Hexagon::V6_vL32b_nt_tmp_ppu:
1790 return false;
1791 }
1792 }
1793 return true;
1794}
1795
1799
1800
1801
1802
1803
1804
1805 if (MI.isDebugInstr())
1806 return false;
1807
1808
1809 if (MI.isCall()) {
1810
1812 return true;
1813
1814
1816 if (I->isEHPad())
1817 return true;
1818 }
1819
1820
1821 if (MI.getDesc().isTerminator() || MI.isPosition())
1822 return true;
1823
1824
1825 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1826 return true;
1827
1829 return true;
1830
1831 return false;
1832}
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1848
1849 bool atInsnStart = true;
1850 unsigned Length = 0;
1852 for (; *Str; ++Str) {
1855 atInsnStart = true;
1856 if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1857 Length += MaxInstLength;
1858 atInsnStart = false;
1859 }
1862 atInsnStart = false;
1863 }
1864
1865
1869}
1870
1877}
1878
1879
1880
1881
1882
1884 Register &SrcReg2, int64_t &Mask,
1885 int64_t &Value) const {
1886 unsigned Opc = MI.getOpcode();
1887
1888
1889 switch (Opc) {
1890 case Hexagon::C2_cmpeq:
1891 case Hexagon::C2_cmpeqp:
1892 case Hexagon::C2_cmpgt:
1893 case Hexagon::C2_cmpgtp:
1894 case Hexagon::C2_cmpgtu:
1895 case Hexagon::C2_cmpgtup:
1896 case Hexagon::C4_cmpneq:
1897 case Hexagon::C4_cmplte:
1898 case Hexagon::C4_cmplteu:
1899 case Hexagon::C2_cmpeqi:
1900 case Hexagon::C2_cmpgti:
1901 case Hexagon::C2_cmpgtui:
1902 case Hexagon::C4_cmpneqi:
1903 case Hexagon::C4_cmplteui:
1904 case Hexagon::C4_cmpltei:
1905 SrcReg = MI.getOperand(1).getReg();
1906 Mask = ~0;
1907 break;
1908 case Hexagon::A4_cmpbeq:
1909 case Hexagon::A4_cmpbgt:
1910 case Hexagon::A4_cmpbgtu:
1911 case Hexagon::A4_cmpbeqi:
1912 case Hexagon::A4_cmpbgti:
1913 case Hexagon::A4_cmpbgtui:
1914 SrcReg = MI.getOperand(1).getReg();
1915 Mask = 0xFF;
1916 break;
1917 case Hexagon::A4_cmpheq:
1918 case Hexagon::A4_cmphgt:
1919 case Hexagon::A4_cmphgtu:
1920 case Hexagon::A4_cmpheqi:
1921 case Hexagon::A4_cmphgti:
1922 case Hexagon::A4_cmphgtui:
1923 SrcReg = MI.getOperand(1).getReg();
1924 Mask = 0xFFFF;
1925 break;
1926 }
1927
1928
1929 switch (Opc) {
1930 case Hexagon::C2_cmpeq:
1931 case Hexagon::C2_cmpeqp:
1932 case Hexagon::C2_cmpgt:
1933 case Hexagon::C2_cmpgtp:
1934 case Hexagon::C2_cmpgtu:
1935 case Hexagon::C2_cmpgtup:
1936 case Hexagon::A4_cmpbeq:
1937 case Hexagon::A4_cmpbgt:
1938 case Hexagon::A4_cmpbgtu:
1939 case Hexagon::A4_cmpheq:
1940 case Hexagon::A4_cmphgt:
1941 case Hexagon::A4_cmphgtu:
1942 case Hexagon::C4_cmpneq:
1943 case Hexagon::C4_cmplte:
1944 case Hexagon::C4_cmplteu:
1945 SrcReg2 = MI.getOperand(2).getReg();
1947 return true;
1948
1949 case Hexagon::C2_cmpeqi:
1950 case Hexagon::C2_cmpgtui:
1951 case Hexagon::C2_cmpgti:
1952 case Hexagon::C4_cmpneqi:
1953 case Hexagon::C4_cmplteui:
1954 case Hexagon::C4_cmpltei:
1955 case Hexagon::A4_cmpbeqi:
1956 case Hexagon::A4_cmpbgti:
1957 case Hexagon::A4_cmpbgtui:
1958 case Hexagon::A4_cmpheqi:
1959 case Hexagon::A4_cmphgti:
1960 case Hexagon::A4_cmphgtui: {
1961 SrcReg2 = 0;
1963 if (!Op2.isImm())
1964 return false;
1965 Value = MI.getOperand(2).getImm();
1966 return true;
1967 }
1968 }
1969
1970 return false;
1971}
1972
1975 unsigned *PredCost) const {
1977}
1978
1982 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1983}
1984
1985
1986
1987
1988
1993 return false;
1994
1995
1996
1998 return true;
1999
2000
2001 unsigned BasePosA, OffsetPosA;
2003 return false;
2006 unsigned BaseSubA = BaseA.getSubReg();
2007
2008
2009 unsigned BasePosB, OffsetPosB;
2011 return false;
2014 unsigned BaseSubB = BaseB.getSubReg();
2015
2016 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2017 return false;
2018
2019
2022
2023
2028 return false;
2031
2032
2033
2034 if (OffsetA > OffsetB) {
2035 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2036 return SizeB <= OffDiff;
2037 }
2038 if (OffsetA < OffsetB) {
2039 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2040 return SizeA <= OffDiff;
2041 }
2042
2043 return false;
2044}
2045
2046
2048 int &Value) const {
2050 unsigned BasePos = 0, OffsetPos = 0;
2052 return false;
2054 if (OffsetOp.isImm()) {
2056 return true;
2057 }
2058 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2060 if (AddOp.isImm()) {
2062 return true;
2063 }
2064 }
2065
2066 return false;
2067}
2068
2069std::pair<unsigned, unsigned>
2073}
2074
2077 using namespace HexagonII;
2078
2079 static const std::pair<unsigned, const char*> Flags[] = {
2080 {MO_PCREL, "hexagon-pcrel"},
2081 {MO_GOT, "hexagon-got"},
2082 {MO_LO16, "hexagon-lo16"},
2083 {MO_HI16, "hexagon-hi16"},
2084 {MO_GPREL, "hexagon-gprel"},
2085 {MO_GDGOT, "hexagon-gdgot"},
2086 {MO_GDPLT, "hexagon-gdplt"},
2087 {MO_IE, "hexagon-ie"},
2088 {MO_IEGOT, "hexagon-iegot"},
2089 {MO_TPREL, "hexagon-tprel"}
2090 };
2092}
2093
2096 using namespace HexagonII;
2097
2098 static const std::pair<unsigned, const char*> Flags[] = {
2099 {HMOTF_ConstExtended, "hexagon-ext"}
2100 };
2102}
2103
2107 if (VT == MVT::i1) {
2108 TRC = &Hexagon::PredRegsRegClass;
2109 } else if (VT == MVT::i32 || VT == MVT::f32) {
2110 TRC = &Hexagon::IntRegsRegClass;
2111 } else if (VT == MVT::i64 || VT == MVT::f64) {
2112 TRC = &Hexagon::DoubleRegsRegClass;
2113 } else {
2115 }
2116
2117 Register NewReg = MRI.createVirtualRegister(TRC);
2118 return NewReg;
2119}
2120
2123}
2124
2126 const uint64_t F = MI.getDesc().TSFlags;
2128}
2129
2132}
2133
2136 .getDesc().mayStore() &&
2137 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2138 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2139 (MI) &&
.isBranch() &&
.isReturn() &&
.isCall();
2140}
2141
2142
2145}
2146
2147
2148
2150 const uint64_t F = MI.getDesc().TSFlags;
2152 if (isExtended)
2153 return true;
2154
2158 return false;
2159
2160 if (MI.isCall())
2161 return false;
2162
2165
2166
2168 return true;
2169
2170
2172 return false;
2173
2174
2175
2176
2179 return true;
2180
2181
2182
2183 assert(MO.isImm() && "Extendable operand must be Immediate type");
2184
2187 int32_t SValue = Value;
2190 return SValue < MinValue || SValue > MaxValue;
2191 }
2195 return UValue < MinValue || UValue > MaxValue;
2196}
2197
2199 switch (MI.getOpcode()) {
2200 case Hexagon::L4_return:
2201 case Hexagon::L4_return_t:
2202 case Hexagon::L4_return_f:
2203 case Hexagon::L4_return_tnew_pnt:
2204 case Hexagon::L4_return_fnew_pnt:
2205 case Hexagon::L4_return_tnew_pt:
2206 case Hexagon::L4_return_fnew_pt:
2207 return true;
2208 }
2209 return false;
2210}
2211
2212
2216 return false;
2218
2223
2226
2227 for (auto &RegA : DefsA)
2228 for (auto &RegB : UsesB) {
2229
2230 if (RegA == RegB)
2231 return true;
2232
2233 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB))
2234 return true;
2235
2236 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA))
2237 return true;
2238 }
2239
2240 return false;
2241}
2242
2243
2245 switch (MI.getOpcode()) {
2246 case Hexagon::V6_vL32b_cur_pi:
2247 case Hexagon::V6_vL32b_cur_ai:
2248 return true;
2249 }
2250 return false;
2251}
2252
2253
2254
2257 return true;
2258
2259 return false;
2260}
2261
2262
2268}
2269
2271 return (Opcode == Hexagon::ENDLOOP0 ||
2272 Opcode == Hexagon::ENDLOOP1);
2273}
2274
2276 switch(OpType) {
2283 return true;
2284 default:
2285 return false;
2286 }
2287}
2288
2293 return true;
2294
2295
2296
2297 switch (MI.getOpcode()) {
2298
2299 case Hexagon::PS_fi:
2300 case Hexagon::PS_fia:
2301 return true;
2302 default:
2303 return false;
2304 }
2305 return false;
2306}
2307
2308
2309
2310
2312
2313 const uint64_t F = MI.getDesc().TSFlags;
2315 return true;
2316
2317
2320 return true;
2321 return false;
2322}
2323
2325 unsigned Opcode = MI.getOpcode();
2328}
2329
2330
2334 return false;
2335 if (.mayLoad() &&
.mayStore())
2336 return false;
2338}
2339
2341 switch (MI.getOpcode()) {
2342 case Hexagon::J2_callr:
2343 case Hexagon::J2_callrf:
2344 case Hexagon::J2_callrt:
2345 case Hexagon::PS_call_nr:
2346 return true;
2347 }
2348 return false;
2349}
2350
2352 switch (MI.getOpcode()) {
2353 case Hexagon::L4_return:
2354 case Hexagon::L4_return_t:
2355 case Hexagon::L4_return_f:
2356 case Hexagon::L4_return_fnew_pnt:
2357 case Hexagon::L4_return_fnew_pt:
2358 case Hexagon::L4_return_tnew_pnt:
2359 case Hexagon::L4_return_tnew_pt:
2360 return true;
2361 }
2362 return false;
2363}
2364
2366 switch (MI.getOpcode()) {
2367 case Hexagon::J2_jumpr:
2368 case Hexagon::J2_jumprt:
2369 case Hexagon::J2_jumprf:
2370 case Hexagon::J2_jumprtnewpt:
2371 case Hexagon::J2_jumprfnewpt:
2372 case Hexagon::J2_jumprtnew:
2373 case Hexagon::J2_jumprfnew:
2374 return true;
2375 }
2376 return false;
2377}
2378
2379
2380
2381
2382
2384 unsigned offset) const {
2385
2386
2388 return isInt<11>(offset);
2389
2390 switch (MI.getOpcode()) {
2391
2392 default:
2393 return false;
2394 case Hexagon::J2_jump:
2395 case Hexagon::J2_call:
2396 case Hexagon::PS_call_nr:
2397 return isInt<24>(offset);
2398 case Hexagon::J2_jumpt:
2399 case Hexagon::J2_jumpf:
2400 case Hexagon::J2_jumptnew:
2401 case Hexagon::J2_jumptnewpt:
2402 case Hexagon::J2_jumpfnew:
2403 case Hexagon::J2_jumpfnewpt:
2404 case Hexagon::J2_callt:
2405 case Hexagon::J2_callf:
2406 return isInt<17>(offset);
2407 case Hexagon::J2_loop0i:
2408 case Hexagon::J2_loop0iext:
2409 case Hexagon::J2_loop0r:
2410 case Hexagon::J2_loop0rext:
2411 case Hexagon::J2_loop1i:
2412 case Hexagon::J2_loop1iext:
2413 case Hexagon::J2_loop1r:
2414 case Hexagon::J2_loop1rext:
2415 return isInt<9>(offset);
2416
2417 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2418 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2419 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2420 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2421 return isInt<11>(offset);
2422 }
2423}
2424
2426
2427
2429}
2430
2432 unsigned Opcode = MI.getOpcode();
2433 return Opcode == Hexagon::J2_loop0i ||
2434 Opcode == Hexagon::J2_loop0r ||
2435 Opcode == Hexagon::J2_loop0iext ||
2436 Opcode == Hexagon::J2_loop0rext ||
2437 Opcode == Hexagon::J2_loop1i ||
2438 Opcode == Hexagon::J2_loop1r ||
2439 Opcode == Hexagon::J2_loop1iext ||
2440 Opcode == Hexagon::J2_loop1rext;
2441}
2442
2444 switch (MI.getOpcode()) {
2445 default: return false;
2446 case Hexagon::L4_iadd_memopw_io:
2447 case Hexagon::L4_isub_memopw_io:
2448 case Hexagon::L4_add_memopw_io:
2449 case Hexagon::L4_sub_memopw_io:
2450 case Hexagon::L4_and_memopw_io:
2451 case Hexagon::L4_or_memopw_io:
2452 case Hexagon::L4_iadd_memoph_io:
2453 case Hexagon::L4_isub_memoph_io:
2454 case Hexagon::L4_add_memoph_io:
2455 case Hexagon::L4_sub_memoph_io:
2456 case Hexagon::L4_and_memoph_io:
2457 case Hexagon::L4_or_memoph_io:
2458 case Hexagon::L4_iadd_memopb_io:
2459 case Hexagon::L4_isub_memopb_io:
2460 case Hexagon::L4_add_memopb_io:
2461 case Hexagon::L4_sub_memopb_io:
2462 case Hexagon::L4_and_memopb_io:
2463 case Hexagon::L4_or_memopb_io:
2464 case Hexagon::L4_ior_memopb_io:
2465 case Hexagon::L4_ior_memoph_io:
2466 case Hexagon::L4_ior_memopw_io:
2467 case Hexagon::L4_iand_memopb_io:
2468 case Hexagon::L4_iand_memoph_io:
2469 case Hexagon::L4_iand_memopw_io:
2470 return true;
2471 }
2472 return false;
2473}
2474
2476 const uint64_t F = MI.getDesc().TSFlags;
2478}
2479
2483}
2484
2487}
2488
2491}
2492
2495}
2496
2498 const uint64_t F = MI.getDesc().TSFlags;
2500}
2501
2505}
2506
2507
2509 unsigned OperandNum) const {
2510 const uint64_t F = MI.getDesc().TSFlags;
2512 == OperandNum;
2513}
2514
2516 const uint64_t F = MI.getDesc().TSFlags;
2519}
2520
2525}
2526
2528 const uint64_t F = MI.getDesc().TSFlags;
2531}
2532
2535
2539}
2540
2544}
2545
2549}
2550
2556}
2557
2559 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2560 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2561 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2562 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2563}
2564
2566 switch (MI.getOpcode()) {
2567
2568 case Hexagon::L2_loadrb_io:
2569 case Hexagon::L4_loadrb_ur:
2570 case Hexagon::L4_loadrb_ap:
2571 case Hexagon::L2_loadrb_pr:
2572 case Hexagon::L2_loadrb_pbr:
2573 case Hexagon::L2_loadrb_pi:
2574 case Hexagon::L2_loadrb_pci:
2575 case Hexagon::L2_loadrb_pcr:
2576 case Hexagon::L2_loadbsw2_io:
2577 case Hexagon::L4_loadbsw2_ur:
2578 case Hexagon::L4_loadbsw2_ap:
2579 case Hexagon::L2_loadbsw2_pr:
2580 case Hexagon::L2_loadbsw2_pbr:
2581 case Hexagon::L2_loadbsw2_pi:
2582 case Hexagon::L2_loadbsw2_pci:
2583 case Hexagon::L2_loadbsw2_pcr:
2584 case Hexagon::L2_loadbsw4_io:
2585 case Hexagon::L4_loadbsw4_ur:
2586 case Hexagon::L4_loadbsw4_ap:
2587 case Hexagon::L2_loadbsw4_pr:
2588 case Hexagon::L2_loadbsw4_pbr:
2589 case Hexagon::L2_loadbsw4_pi:
2590 case Hexagon::L2_loadbsw4_pci:
2591 case Hexagon::L2_loadbsw4_pcr:
2592 case Hexagon::L4_loadrb_rr:
2593 case Hexagon::L2_ploadrbt_io:
2594 case Hexagon::L2_ploadrbt_pi:
2595 case Hexagon::L2_ploadrbf_io:
2596 case Hexagon::L2_ploadrbf_pi:
2597 case Hexagon::L2_ploadrbtnew_io:
2598 case Hexagon::L2_ploadrbfnew_io:
2599 case Hexagon::L4_ploadrbt_rr:
2600 case Hexagon::L4_ploadrbf_rr:
2601 case Hexagon::L4_ploadrbtnew_rr:
2602 case Hexagon::L4_ploadrbfnew_rr:
2603 case Hexagon::L2_ploadrbtnew_pi:
2604 case Hexagon::L2_ploadrbfnew_pi:
2605 case Hexagon::L4_ploadrbt_abs:
2606 case Hexagon::L4_ploadrbf_abs:
2607 case Hexagon::L4_ploadrbtnew_abs:
2608 case Hexagon::L4_ploadrbfnew_abs:
2609 case Hexagon::L2_loadrbgp:
2610
2611 case Hexagon::L2_loadrh_io:
2612 case Hexagon::L4_loadrh_ur:
2613 case Hexagon::L4_loadrh_ap:
2614 case Hexagon::L2_loadrh_pr:
2615 case Hexagon::L2_loadrh_pbr:
2616 case Hexagon::L2_loadrh_pi:
2617 case Hexagon::L2_loadrh_pci:
2618 case Hexagon::L2_loadrh_pcr:
2619 case Hexagon::L4_loadrh_rr:
2620 case Hexagon::L2_ploadrht_io:
2621 case Hexagon::L2_ploadrht_pi:
2622 case Hexagon::L2_ploadrhf_io:
2623 case Hexagon::L2_ploadrhf_pi:
2624 case Hexagon::L2_ploadrhtnew_io:
2625 case Hexagon::L2_ploadrhfnew_io:
2626 case Hexagon::L4_ploadrht_rr:
2627 case Hexagon::L4_ploadrhf_rr:
2628 case Hexagon::L4_ploadrhtnew_rr:
2629 case Hexagon::L4_ploadrhfnew_rr:
2630 case Hexagon::L2_ploadrhtnew_pi:
2631 case Hexagon::L2_ploadrhfnew_pi:
2632 case Hexagon::L4_ploadrht_abs:
2633 case Hexagon::L4_ploadrhf_abs:
2634 case Hexagon::L4_ploadrhtnew_abs:
2635 case Hexagon::L4_ploadrhfnew_abs:
2636 case Hexagon::L2_loadrhgp:
2637 return true;
2638 default:
2639 return false;
2640 }
2641}
2642
2644 const uint64_t F = MI.getDesc().TSFlags;
2646}
2647
2649 switch (MI.getOpcode()) {
2650 case Hexagon::STriw_pred:
2651 case Hexagon::LDriw_pred:
2652 return true;
2653 default:
2654 return false;
2655 }
2656}
2657
2659 if (.isBranch())
2660 return false;
2661
2662 for (auto &Op : MI.operands())
2663 if (Op.isGlobal() || Op.isSymbol())
2664 return true;
2665 return false;
2666}
2667
2668
2670 unsigned SchedClass = MI.getDesc().getSchedClass();
2671 return is_TC1(SchedClass);
2672}
2673
2675 unsigned SchedClass = MI.getDesc().getSchedClass();
2676 return is_TC2(SchedClass);
2677}
2678
2680 unsigned SchedClass = MI.getDesc().getSchedClass();
2682}
2683
2685 unsigned SchedClass = MI.getDesc().getSchedClass();
2686 return is_TC4x(SchedClass);
2687}
2688
2689
2693
2696 for (int I = 0; I < N; I++)
2698 return true;
2699 }
2701 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2704 return true;
2705 return false;
2706}
2707
2711}
2712
2713
2717 return false;
2719
2721
2722 case MVT::i8:
2723 case MVT::i16:
2724 case MVT::i32:
2725 case MVT::i64:
2726 case MVT::f32:
2727 case MVT::f64:
2728 case MVT::v2i16:
2729 case MVT::v2i32:
2730 case MVT::v4i8:
2731 case MVT::v4i16:
2732 case MVT::v8i8:
2733 return isInt<4>(Count);
2734
2735 case MVT::v64i8:
2736 case MVT::v32i16:
2737 case MVT::v16i32:
2738 case MVT::v8i64:
2739 case MVT::v128i8:
2740 case MVT::v64i16:
2741 case MVT::v32i32:
2742 case MVT::v16i64:
2743 return isInt<3>(Count);
2744 default:
2745 break;
2746 }
2747
2749}
2750
2753
2754
2755
2756
2757
2758
2759
2760
2761 switch (Opcode) {
2762 case Hexagon::PS_vstorerq_ai:
2763 case Hexagon::PS_vstorerv_ai:
2764 case Hexagon::PS_vstorerw_ai:
2765 case Hexagon::PS_vstorerw_nt_ai:
2766 case Hexagon::PS_vloadrq_ai:
2767 case Hexagon::PS_vloadrv_ai:
2768 case Hexagon::PS_vloadrw_ai:
2769 case Hexagon::PS_vloadrw_nt_ai:
2770 case Hexagon::V6_vL32b_ai:
2771 case Hexagon::V6_vS32b_ai:
2772 case Hexagon::V6_vS32b_pred_ai:
2773 case Hexagon::V6_vS32b_npred_ai:
2774 case Hexagon::V6_vS32b_qpred_ai:
2775 case Hexagon::V6_vS32b_nqpred_ai:
2776 case Hexagon::V6_vS32b_new_ai:
2777 case Hexagon::V6_vS32b_new_pred_ai:
2778 case Hexagon::V6_vS32b_new_npred_ai:
2779 case Hexagon::V6_vS32b_nt_pred_ai:
2780 case Hexagon::V6_vS32b_nt_npred_ai:
2781 case Hexagon::V6_vS32b_nt_new_ai:
2782 case Hexagon::V6_vS32b_nt_new_pred_ai:
2783 case Hexagon::V6_vS32b_nt_new_npred_ai:
2784 case Hexagon::V6_vS32b_nt_qpred_ai:
2785 case Hexagon::V6_vS32b_nt_nqpred_ai:
2786 case Hexagon::V6_vL32b_nt_ai:
2787 case Hexagon::V6_vS32b_nt_ai:
2788 case Hexagon::V6_vL32Ub_ai:
2789 case Hexagon::V6_vS32Ub_ai:
2790 case Hexagon::V6_vL32b_cur_ai:
2791 case Hexagon::V6_vL32b_tmp_ai:
2792 case Hexagon::V6_vL32b_pred_ai:
2793 case Hexagon::V6_vL32b_npred_ai:
2794 case Hexagon::V6_vL32b_cur_pred_ai:
2795 case Hexagon::V6_vL32b_cur_npred_ai:
2796 case Hexagon::V6_vL32b_tmp_pred_ai:
2797 case Hexagon::V6_vL32b_tmp_npred_ai:
2798 case Hexagon::V6_vL32b_nt_cur_ai:
2799 case Hexagon::V6_vL32b_nt_tmp_ai:
2800 case Hexagon::V6_vL32b_nt_pred_ai:
2801 case Hexagon::V6_vL32b_nt_npred_ai:
2802 case Hexagon::V6_vL32b_nt_cur_pred_ai:
2803 case Hexagon::V6_vL32b_nt_cur_npred_ai:
2804 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
2805 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
2806 case Hexagon::V6_vgathermh_pseudo:
2807 case Hexagon::V6_vgathermw_pseudo:
2808 case Hexagon::V6_vgathermhw_pseudo:
2809 case Hexagon::V6_vgathermhq_pseudo:
2810 case Hexagon::V6_vgathermwq_pseudo:
2811 case Hexagon::V6_vgathermhwq_pseudo: {
2812 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2814 if (Offset & (VectorSize-1))
2815 return false;
2817 }
2818
2819 case Hexagon::J2_loop0i:
2820 case Hexagon::J2_loop1i:
2821 return isUInt<10>(Offset);
2822
2823 case Hexagon::S4_storeirb_io:
2824 case Hexagon::S4_storeirbt_io:
2825 case Hexagon::S4_storeirbf_io:
2826 return isUInt<6>(Offset);
2827
2828 case Hexagon::S4_storeirh_io:
2829 case Hexagon::S4_storeirht_io:
2830 case Hexagon::S4_storeirhf_io:
2831 return isShiftedUInt<6,1>(Offset);
2832
2833 case Hexagon::S4_storeiri_io:
2834 case Hexagon::S4_storeirit_io:
2835 case Hexagon::S4_storeirif_io:
2836 return isShiftedUInt<6,2>(Offset);
2837
2838 case Hexagon::A4_cmpbeqi:
2839 return isUInt<8>(Offset);
2840 case Hexagon::A4_cmpbgti:
2841 return isInt<8>(Offset);
2842 }
2843
2844 if (Extend)
2845 return true;
2846
2847 switch (Opcode) {
2848 case Hexagon::L2_loadri_io:
2849 case Hexagon::S2_storeri_io:
2852
2853 case Hexagon::L2_loadrd_io:
2854 case Hexagon::S2_storerd_io:
2857
2858 case Hexagon::L2_loadrh_io:
2859 case Hexagon::L2_loadruh_io:
2860 case Hexagon::S2_storerh_io:
2861 case Hexagon::S2_storerf_io:
2864
2865 case Hexagon::L2_loadrb_io:
2866 case Hexagon::L2_loadrub_io:
2867 case Hexagon::S2_storerb_io:
2870
2871 case Hexagon::A2_addi:
2874
2875 case Hexagon::L4_iadd_memopw_io:
2876 case Hexagon::L4_isub_memopw_io:
2877 case Hexagon::L4_add_memopw_io:
2878 case Hexagon::L4_sub_memopw_io:
2879 case Hexagon::L4_iand_memopw_io:
2880 case Hexagon::L4_ior_memopw_io:
2881 case Hexagon::L4_and_memopw_io:
2882 case Hexagon::L4_or_memopw_io:
2884
2885 case Hexagon::L4_iadd_memoph_io:
2886 case Hexagon::L4_isub_memoph_io:
2887 case Hexagon::L4_add_memoph_io:
2888 case Hexagon::L4_sub_memoph_io:
2889 case Hexagon::L4_iand_memoph_io:
2890 case Hexagon::L4_ior_memoph_io:
2891 case Hexagon::L4_and_memoph_io:
2892 case Hexagon::L4_or_memoph_io:
2894
2895 case Hexagon::L4_iadd_memopb_io:
2896 case Hexagon::L4_isub_memopb_io:
2897 case Hexagon::L4_add_memopb_io:
2898 case Hexagon::L4_sub_memopb_io:
2899 case Hexagon::L4_iand_memopb_io:
2900 case Hexagon::L4_ior_memopb_io:
2901 case Hexagon::L4_and_memopb_io:
2902 case Hexagon::L4_or_memopb_io:
2904
2905
2906
2907 case Hexagon::STriw_pred:
2908 case Hexagon::LDriw_pred:
2909 case Hexagon::STriw_ctr:
2910 case Hexagon::LDriw_ctr:
2911 return true;
2912
2913 case Hexagon::PS_fi:
2914 case Hexagon::PS_fia:
2915 case Hexagon::INLINEASM:
2916 return true;
2917
2918 case Hexagon::L2_ploadrbt_io:
2919 case Hexagon::L2_ploadrbf_io:
2920 case Hexagon::L2_ploadrubt_io:
2921 case Hexagon::L2_ploadrubf_io:
2922 case Hexagon::S2_pstorerbt_io:
2923 case Hexagon::S2_pstorerbf_io:
2924 return isUInt<6>(Offset);
2925
2926 case Hexagon::L2_ploadrht_io:
2927 case Hexagon::L2_ploadrhf_io:
2928 case Hexagon::L2_ploadruht_io:
2929 case Hexagon::L2_ploadruhf_io:
2930 case Hexagon::S2_pstorerht_io:
2931 case Hexagon::S2_pstorerhf_io:
2932 return isShiftedUInt<6,1>(Offset);
2933
2934 case Hexagon::L2_ploadrit_io:
2935 case Hexagon::L2_ploadrif_io:
2936 case Hexagon::S2_pstorerit_io:
2937 case Hexagon::S2_pstorerif_io:
2938 return isShiftedUInt<6,2>(Offset);
2939
2940 case Hexagon::L2_ploadrdt_io:
2941 case Hexagon::L2_ploadrdf_io:
2942 case Hexagon::S2_pstorerdt_io:
2943 case Hexagon::S2_pstorerdf_io:
2944 return isShiftedUInt<6,3>(Offset);
2945
2946 case Hexagon::L2_loadbsw2_io:
2947 case Hexagon::L2_loadbzw2_io:
2948 return isShiftedInt<11,1>(Offset);
2949
2950 case Hexagon::L2_loadbsw4_io:
2951 case Hexagon::L2_loadbzw4_io:
2952 return isShiftedInt<11,2>(Offset);
2953 }
2954
2955 dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2956 << ")\n";
2957 llvm_unreachable("No offset range is defined for this opcode. "
2958 "Please define it in the above switch statement!");
2959}
2960
2963}
2964
2968 return
2971}
2972
2976 return true;
2977
2979 return true;
2980
2982 return true;
2983
2984 return false;
2985}
2986
2988 switch (MI.getOpcode()) {
2989
2990 case Hexagon::L2_loadrub_io:
2991 case Hexagon::L4_loadrub_ur:
2992 case Hexagon::L4_loadrub_ap:
2993 case Hexagon::L2_loadrub_pr:
2994 case Hexagon::L2_loadrub_pbr:
2995 case Hexagon::L2_loadrub_pi:
2996 case Hexagon::L2_loadrub_pci:
2997 case Hexagon::L2_loadrub_pcr:
2998 case Hexagon::L2_loadbzw2_io:
2999 case Hexagon::L4_loadbzw2_ur:
3000 case Hexagon::L4_loadbzw2_ap:
3001 case Hexagon::L2_loadbzw2_pr:
3002 case Hexagon::L2_loadbzw2_pbr:
3003 case Hexagon::L2_loadbzw2_pi:
3004 case Hexagon::L2_loadbzw2_pci:
3005 case Hexagon::L2_loadbzw2_pcr:
3006 case Hexagon::L2_loadbzw4_io:
3007 case Hexagon::L4_loadbzw4_ur:
3008 case Hexagon::L4_loadbzw4_ap:
3009 case Hexagon::L2_loadbzw4_pr:
3010 case Hexagon::L2_loadbzw4_pbr:
3011 case Hexagon::L2_loadbzw4_pi:
3012 case Hexagon::L2_loadbzw4_pci:
3013 case Hexagon::L2_loadbzw4_pcr:
3014 case Hexagon::L4_loadrub_rr:
3015 case Hexagon::L2_ploadrubt_io:
3016 case Hexagon::L2_ploadrubt_pi:
3017 case Hexagon::L2_ploadrubf_io:
3018 case Hexagon::L2_ploadrubf_pi:
3019 case Hexagon::L2_ploadrubtnew_io:
3020 case Hexagon::L2_ploadrubfnew_io:
3021 case Hexagon::L4_ploadrubt_rr:
3022 case Hexagon::L4_ploadrubf_rr:
3023 case Hexagon::L4_ploadrubtnew_rr:
3024 case Hexagon::L4_ploadrubfnew_rr:
3025 case Hexagon::L2_ploadrubtnew_pi:
3026 case Hexagon::L2_ploadrubfnew_pi:
3027 case Hexagon::L4_ploadrubt_abs:
3028 case Hexagon::L4_ploadrubf_abs:
3029 case Hexagon::L4_ploadrubtnew_abs:
3030 case Hexagon::L4_ploadrubfnew_abs:
3031 case Hexagon::L2_loadrubgp:
3032
3033 case Hexagon::L2_loadruh_io:
3034 case Hexagon::L4_loadruh_ur:
3035 case Hexagon::L4_loadruh_ap:
3036 case Hexagon::L2_loadruh_pr:
3037 case Hexagon::L2_loadruh_pbr:
3038 case Hexagon::L2_loadruh_pi:
3039 case Hexagon::L2_loadruh_pci:
3040 case Hexagon::L2_loadruh_pcr:
3041 case Hexagon::L4_loadruh_rr:
3042 case Hexagon::L2_ploadruht_io:
3043 case Hexagon::L2_ploadruht_pi:
3044 case Hexagon::L2_ploadruhf_io:
3045 case Hexagon::L2_ploadruhf_pi:
3046 case Hexagon::L2_ploadruhtnew_io:
3047 case Hexagon::L2_ploadruhfnew_io:
3048 case Hexagon::L4_ploadruht_rr:
3049 case Hexagon::L4_ploadruhf_rr:
3050 case Hexagon::L4_ploadruhtnew_rr:
3051 case Hexagon::L4_ploadruhfnew_rr:
3052 case Hexagon::L2_ploadruhtnew_pi:
3053 case Hexagon::L2_ploadruhfnew_pi:
3054 case Hexagon::L4_ploadruht_abs:
3055 case Hexagon::L4_ploadruhf_abs:
3056 case Hexagon::L4_ploadruhtnew_abs:
3057 case Hexagon::L4_ploadruhfnew_abs:
3058 case Hexagon::L2_loadruhgp:
3059 return true;
3060 default:
3061 return false;
3062 }
3063}
3064
3065
3070 return true;
3071 return false;
3072}
3073
3074
3079 OffsetIsScalable = false;
3081 if (!BaseOp || !BaseOp->isReg())
3082 return false;
3084 return true;
3085}
3086
3087
3090 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3092 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3093 return true;
3094 }
3096 return false;
3098
3099
3102 if (!Stored.isReg())
3103 return false;
3104 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3106 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3107 return true;
3108 }
3109 }
3110 return false;
3111}
3112
3114 unsigned Opc = CallMI.getOpcode();
3115 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3116}
3117
3120 if (I.isEHLabel())
3121 return true;
3122 return false;
3123}
3124
3125
3126
3128 short NonExtOpcode;
3129
3130
3131 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3132 return true;
3133
3134 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3135
3136
3139
3140
3141 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3142 break;
3144
3145
3146
3147 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3148 break;
3150 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3151 break;
3152 default:
3153 return false;
3154 }
3155 if (NonExtOpcode < 0)
3156 return false;
3157 return true;
3158 }
3159 return false;
3160}
3161
3163 return Hexagon::getRealHWInstr(MI.getOpcode(),
3164 Hexagon::InstrType_Pseudo) >= 0;
3165}
3166
3168 const {
3170 while (I != E) {
3171 if (I->isBarrier())
3172 return true;
3173 ++I;
3174 }
3175 return false;
3176}
3177
3178
3180 const uint64_t F = MI.getDesc().TSFlags;
3183}
3184
3185
3188 return false;
3189
3190 const uint64_t F = MI.getDesc().TSFlags;
3192}
3193
3196
3198 return false;
3199
3200
3202 return false;
3203
3204
3205
3207 return false;
3208
3209 return true;
3210}
3211
3214
3216 return false;
3217
3220
3221 if (!MII->isBundle())
3223
3224 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3227 return true;
3228 }
3229 return false;
3230}
3231
3235
3236 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3237 return false;
3238 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3239 return false;
3240 }
3241
3242
3243
3244 switch (MI.getOpcode()) {
3245 case Hexagon::A4_addp_c:
3246 case Hexagon::A4_subp_c:
3247 case Hexagon::A4_tlbmatch:
3248 case Hexagon::A5_ACS:
3249 case Hexagon::F2_sfinvsqrta:
3250 case Hexagon::F2_sfrecipa:
3251 case Hexagon::J2_endloop0:
3252 case Hexagon::J2_endloop01:
3253 case Hexagon::J2_ploop1si:
3254 case Hexagon::J2_ploop1sr:
3255 case Hexagon::J2_ploop2si:
3256 case Hexagon::J2_ploop2sr:
3257 case Hexagon::J2_ploop3si:
3258 case Hexagon::J2_ploop3sr:
3259 case Hexagon::S2_cabacdecbin:
3260 case Hexagon::S2_storew_locked:
3261 case Hexagon::S4_stored_locked:
3262 return false;
3263 }
3264 return true;
3265}
3266
3268 return Opcode == Hexagon::J2_jumpt ||
3269 Opcode == Hexagon::J2_jumptpt ||
3270 Opcode == Hexagon::J2_jumpf ||
3271 Opcode == Hexagon::J2_jumpfpt ||
3272 Opcode == Hexagon::J2_jumptnew ||
3273 Opcode == Hexagon::J2_jumpfnew ||
3274 Opcode == Hexagon::J2_jumptnewpt ||
3275 Opcode == Hexagon::J2_jumpfnewpt;
3276}
3277
3280 return false;
3282}
3283
3285 const uint64_t F = MI.getDesc().TSFlags;
3287}
3288
3289
3290
3291
3292
3296
3300 return nullptr;
3301
3303
3304 unsigned BasePos = 0, OffsetPos = 0;
3306 return nullptr;
3307
3308
3309
3312 } else {
3314 if (!OffsetOp.isImm())
3315 return nullptr;
3317 }
3318
3321 return nullptr;
3323}
3324
3325
3327 unsigned &BasePos, unsigned &OffsetPos) const {
3329 return false;
3330
3331
3333 BasePos = 0;
3334 OffsetPos = 1;
3335 } else if (MI.mayStore()) {
3336 BasePos = 0;
3337 OffsetPos = 1;
3338 } else if (MI.mayLoad()) {
3339 BasePos = 1;
3340 OffsetPos = 2;
3341 } else
3342 return false;
3343
3345 BasePos++;
3346 OffsetPos++;
3347 }
3349 BasePos++;
3350 OffsetPos++;
3351 }
3352
3353 if (.getOperand(BasePos).isReg() ||
.getOperand(OffsetPos).isImm())
3354 return false;
3355
3356 return true;
3357}
3358
3359
3360
3361
3362
3366
3369 return Jumpers;
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383 do {
3384 --I;
3385 if (I->isEHLabel())
3386 return Jumpers;
3388
3390 --I;
3391
3392 while (I->isDebugInstr()) {
3394 return Jumpers;
3395 --I;
3396 }
3397 if (!isUnpredicatedTerminator(*I))
3398 return Jumpers;
3399
3400
3404
3405 do {
3406 if (&*I != LastInst && ->isBundle() && isUnpredicatedTerminator(*I)) {
3407 if (!SecondLastInst) {
3408 SecondLastInst = &*I;
3409 Jumpers.push_back(SecondLastInst);
3410 } else
3411 return Jumpers;
3412 }
3414 break;
3415 --I;
3416 } while (true);
3417 return Jumpers;
3418}
3419
3420
3422 const uint64_t F = MI.getDesc().TSFlags;
3424}
3425
3426
3427
3430 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3431
3432 switch (MI.getOpcode()) {
3433 default:
3435
3436
3437
3438
3439
3440
3441 case Hexagon::C2_cmpeq:
3442 case Hexagon::C2_cmpgt:
3443 case Hexagon::C2_cmpgtu:
3444 DstReg = MI.getOperand(0).getReg();
3445 Src1Reg = MI.getOperand(1).getReg();
3446 Src2Reg = MI.getOperand(2).getReg();
3447 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3448 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3451 break;
3452 case Hexagon::C2_cmpeqi:
3453 case Hexagon::C2_cmpgti:
3454 case Hexagon::C2_cmpgtui:
3455
3456 DstReg = MI.getOperand(0).getReg();
3457 SrcReg = MI.getOperand(1).getReg();
3458 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3459 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3461 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3462 (MI.getOperand(2).getImm() == -1)))
3464 break;
3465 case Hexagon::A2_tfr:
3466
3467 DstReg = MI.getOperand(0).getReg();
3468 SrcReg = MI.getOperand(1).getReg();
3471 break;
3472 case Hexagon::A2_tfrsi:
3473
3474
3475
3476 DstReg = MI.getOperand(0).getReg();
3479 break;
3480 case Hexagon::S2_tstbit_i:
3481 DstReg = MI.getOperand(0).getReg();
3482 Src1Reg = MI.getOperand(1).getReg();
3483 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3484 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3485 MI.getOperand(2).isImm() &&
3488 break;
3489
3490
3491
3492
3493 case Hexagon::J2_jumptnew:
3494 case Hexagon::J2_jumpfnew:
3495 case Hexagon::J2_jumptnewpt:
3496 case Hexagon::J2_jumpfnewpt:
3497 Src1Reg = MI.getOperand(0).getReg();
3498 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3499 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3501 break;
3502
3503
3504
3505
3506 case Hexagon::J2_jump:
3507 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3508 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3510 }
3511
3513}
3514
3515
3520 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3521 (GB.getOpcode() != Hexagon::J2_jumptnew))
3522 return -1u;
3524 if (!GB.readsRegister(DestReg, nullptr))
3525 return -1u;
3526 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3527 return -1u;
3528
3530 if (!CmpOp.isImm())
3531 return -1u;
3532 int V = CmpOp.getImm();
3533 if (V == -1)
3534 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3535 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3536 if (!isUInt<5>(V))
3537 return -1u;
3538 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3539 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3540}
3541
3542
3544 bool ForBigCore) const {
3545
3546
3547
3548
3549
3550
3551
3552 static const std::map<unsigned, unsigned> DupMap = {
3553 {Hexagon::A2_add, Hexagon::dup_A2_add},
3554 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3555 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3556 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3557 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3558 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3559 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3560 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3561 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3562 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3563 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3564 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3565 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3566 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3567 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3568 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3569 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3570 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3571 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3572 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3573 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3574 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3575 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3576 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3577 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3578 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3579 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3580 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3581 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3582 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3583 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3584 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3585 };
3586 unsigned OpNum = MI.getOpcode();
3587
3588 if (ForBigCore) {
3589 auto Iter = DupMap.find(OpNum);
3590 if (Iter != DupMap.end())
3591 return Iter->second;
3592 } else {
3593 for (const auto &Iter : DupMap)
3594 if (Iter.second == OpNum)
3595 return Iter.first;
3596 }
3597 return -1;
3598}
3599
3601 enum Hexagon::PredSense inPredSense;
3602 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3603 Hexagon::PredSense_true;
3604 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3605 if (CondOpcode >= 0)
3606 return CondOpcode;
3607
3609}
3610
3611
3613 switch (MI.getOpcode()) {
3615 case Hexagon::V6_vL32b_pi:
3616 return Hexagon::V6_vL32b_cur_pi;
3617 case Hexagon::V6_vL32b_ai:
3618 return Hexagon::V6_vL32b_cur_ai;
3619 case Hexagon::V6_vL32b_nt_pi:
3620 return Hexagon::V6_vL32b_nt_cur_pi;
3621 case Hexagon::V6_vL32b_nt_ai:
3622 return Hexagon::V6_vL32b_nt_cur_ai;
3623 case Hexagon::V6_vL32b_ppu:
3624 return Hexagon::V6_vL32b_cur_ppu;
3625 case Hexagon::V6_vL32b_nt_ppu:
3626 return Hexagon::V6_vL32b_nt_cur_ppu;
3627 }
3628 return 0;
3629}
3630
3631
3633 switch (MI.getOpcode()) {
3635 case Hexagon::V6_vL32b_cur_pi:
3636 return Hexagon::V6_vL32b_pi;
3637 case Hexagon::V6_vL32b_cur_ai:
3638 return Hexagon::V6_vL32b_ai;
3639 case Hexagon::V6_vL32b_nt_cur_pi:
3640 return Hexagon::V6_vL32b_nt_pi;
3641 case Hexagon::V6_vL32b_nt_cur_ai:
3642 return Hexagon::V6_vL32b_nt_ai;
3643 case Hexagon::V6_vL32b_cur_ppu:
3644 return Hexagon::V6_vL32b_ppu;
3645 case Hexagon::V6_vL32b_nt_cur_ppu:
3646 return Hexagon::V6_vL32b_nt_ppu;
3647 }
3648 return 0;
3649}
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3734 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3735 if (NVOpcode >= 0)
3736 return NVOpcode;
3737
3738 switch (MI.getOpcode()) {
3739 default:
3741 std::to_string(MI.getOpcode()));
3742 case Hexagon::S4_storerb_ur:
3743 return Hexagon::S4_storerbnew_ur;
3744
3745 case Hexagon::S2_storerb_pci:
3746 return Hexagon::S2_storerb_pci;
3747
3748 case Hexagon::S2_storeri_pci:
3749 return Hexagon::S2_storeri_pci;
3750
3751 case Hexagon::S2_storerh_pci:
3752 return Hexagon::S2_storerh_pci;
3753
3754 case Hexagon::S2_storerd_pci:
3755 return Hexagon::S2_storerd_pci;
3756
3757 case Hexagon::S2_storerf_pci:
3758 return Hexagon::S2_storerf_pci;
3759
3760 case Hexagon::V6_vS32b_ai:
3761 return Hexagon::V6_vS32b_new_ai;
3762
3763 case Hexagon::V6_vS32b_pi:
3764 return Hexagon::V6_vS32b_new_pi;
3765 }
3766 return 0;
3767}
3768
3769
3770
3771
3772
3773
3776
3779 bool Taken = false;
3781
3784 if (MBPI)
3787 };
3788
3789 if (BrTarget.isMBB()) {
3791 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3792 } else {
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802 assert(MI.isConditionalBranch());
3804 bool SawCond = false, Bad = false;
3806 if (.isBranch())
3807 continue;
3808 if (I.isConditionalBranch()) {
3809 SawCond = true;
3811 Bad = true;
3812 break;
3813 }
3814 }
3815 if (I.isUnconditionalBranch() && !SawCond) {
3816 Bad = true;
3817 break;
3818 }
3819 }
3820 if (!Bad) {
3823 if (NextIt == B.instr_end()) {
3824
3826 if (.isLayoutSuccessor(SB))
3827 continue;
3828 Taken = getEdgeProbability(Src, SB) < OneHalf;
3829 break;
3830 }
3831 } else {
3832 assert(NextIt->isUnconditionalBranch());
3833
3836 if (.isMBB())
3837 continue;
3839 break;
3840 }
3841 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3842 }
3843 }
3844 }
3845
3846
3847
3848 switch (MI.getOpcode()) {
3849 case Hexagon::J2_jumpt:
3850 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3851 case Hexagon::J2_jumpf:
3852 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3853
3854 default:
3856 }
3857}
3858
3859
3862 switch (MI.getOpcode()) {
3863
3864 case Hexagon::J2_jumpt:
3865 case Hexagon::J2_jumpf:
3867 }
3868
3869 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3870 if (NewOpcode >= 0)
3871 return NewOpcode;
3872 return 0;
3873}
3874
3876 int NewOp = MI.getOpcode();
3878 NewOp = Hexagon::getPredOldOpcode(NewOp);
3879
3880
3881
3882 if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
3883 switch (NewOp) {
3884 case Hexagon::J2_jumptpt:
3885 NewOp = Hexagon::J2_jumpt;
3886 break;
3887 case Hexagon::J2_jumpfpt:
3888 NewOp = Hexagon::J2_jumpf;
3889 break;
3890 case Hexagon::J2_jumprtpt:
3891 NewOp = Hexagon::J2_jumprt;
3892 break;
3893 case Hexagon::J2_jumprfpt:
3894 NewOp = Hexagon::J2_jumprf;
3895 break;
3896 }
3897 }
3898 assert(NewOp >= 0 &&
3899 "Couldn't change predicate new instruction to its old form.");
3900 }
3901
3902 if (isNewValueStore(NewOp)) {
3903 NewOp = Hexagon::getNonNVStore(NewOp);
3904 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3905 }
3906
3908 return NewOp;
3909
3910
3911 switch (NewOp) {
3912 case Hexagon::J2_jumpfpt:
3913 return Hexagon::J2_jumpf;
3914 case Hexagon::J2_jumptpt:
3915 return Hexagon::J2_jumpt;
3916 case Hexagon::J2_jumprfpt:
3917 return Hexagon::J2_jumprf;
3918 case Hexagon::J2_jumprtpt:
3919 return Hexagon::J2_jumprt;
3920 }
3921 return NewOp;
3922}
3923
3924
3925
3928 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3930
3931 switch (MI.getOpcode()) {
3932 default:
3934
3935
3936
3937
3938
3939 case Hexagon::L2_loadri_io:
3940 case Hexagon::dup_L2_loadri_io:
3941 DstReg = MI.getOperand(0).getReg();
3942 SrcReg = MI.getOperand(1).getReg();
3943
3944
3946 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3948 MI.getOperand(2).isImm() &&
3949 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3951
3953 (MI.getOperand(2).isImm() &&
3954 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3956 }
3957 break;
3958 case Hexagon::L2_loadrub_io:
3959 case Hexagon::dup_L2_loadrub_io:
3960
3961 DstReg = MI.getOperand(0).getReg();
3962 SrcReg = MI.getOperand(1).getReg();
3964 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3966 break;
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977 case Hexagon::L2_loadrh_io:
3978 case Hexagon::L2_loadruh_io:
3979 case Hexagon::dup_L2_loadrh_io:
3980 case Hexagon::dup_L2_loadruh_io:
3981
3982 DstReg = MI.getOperand(0).getReg();
3983 SrcReg = MI.getOperand(1).getReg();
3985 MI.getOperand(2).isImm() &&
3986 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3988 break;
3989 case Hexagon::L2_loadrb_io:
3990 case Hexagon::dup_L2_loadrb_io:
3991
3992 DstReg = MI.getOperand(0).getReg();
3993 SrcReg = MI.getOperand(1).getReg();
3995 MI.getOperand(2).isImm() &&
3996 isUInt<3>(MI.getOperand(2).getImm()))
3998 break;
3999 case Hexagon::L2_loadrd_io:
4000 case Hexagon::dup_L2_loadrd_io:
4001
4002 DstReg = MI.getOperand(0).getReg();
4003 SrcReg = MI.getOperand(1).getReg();
4005 Hexagon::IntRegsRegClass.contains(SrcReg) &&
4007 MI.getOperand(2).isImm() &&
4008 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4010 break;
4011
4012
4013 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4014 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4015 case Hexagon::L4_return:
4016 case Hexagon::L2_deallocframe:
4017 case Hexagon::dup_L2_deallocframe:
4019 case Hexagon::EH_RETURN_JMPR:
4020 case Hexagon::PS_jmpret:
4021 case Hexagon::SL2_jumpr31:
4022
4023
4024 DstReg = MI.getOperand(0).getReg();
4025 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
4027 break;
4028 case Hexagon::PS_jmprett:
4029 case Hexagon::PS_jmpretf:
4030 case Hexagon::PS_jmprettnewpt:
4031 case Hexagon::PS_jmpretfnewpt:
4032 case Hexagon::PS_jmprettnew:
4033 case Hexagon::PS_jmpretfnew:
4034 case Hexagon::SL2_jumpr31_t:
4035 case Hexagon::SL2_jumpr31_f:
4036 case Hexagon::SL2_jumpr31_tnew:
4037 case Hexagon::SL2_jumpr31_fnew:
4038 DstReg = MI.getOperand(1).getReg();
4039 SrcReg = MI.getOperand(0).getReg();
4040
4041 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4042 (Hexagon::P0 == SrcReg)) &&
4043 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4045 break;
4046 case Hexagon::L4_return_t:
4047 case Hexagon::L4_return_f:
4048 case Hexagon::L4_return_tnew_pnt:
4049 case Hexagon::L4_return_fnew_pnt:
4050 case Hexagon::L4_return_tnew_pt:
4051 case Hexagon::L4_return_fnew_pt:
4052
4053 SrcReg = MI.getOperand(0).getReg();
4054 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4056 break;
4057
4058
4059
4060
4061
4062 case Hexagon::S2_storeri_io:
4063 case Hexagon::dup_S2_storeri_io:
4064
4065
4066 Src1Reg = MI.getOperand(0).getReg();
4067 Src2Reg = MI.getOperand(2).getReg();
4068 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4071 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
4073
4075 MI.getOperand(1).isImm() &&
4076 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
4078 break;
4079 case Hexagon::S2_storerb_io:
4080 case Hexagon::dup_S2_storerb_io:
4081
4082 Src1Reg = MI.getOperand(0).getReg();
4083 Src2Reg = MI.getOperand(2).getReg();
4085 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4087 break;
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097 case Hexagon::S2_storerh_io:
4098 case Hexagon::dup_S2_storerh_io:
4099
4100 Src1Reg = MI.getOperand(0).getReg();
4101 Src2Reg = MI.getOperand(2).getReg();
4103 MI.getOperand(1).isImm() &&
4104 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
4106 break;
4107 case Hexagon::S2_storerd_io:
4108 case Hexagon::dup_S2_storerd_io:
4109
4110 Src1Reg = MI.getOperand(0).getReg();
4111 Src2Reg = MI.getOperand(2).getReg();
4113 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4115 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4117 break;
4118 case Hexagon::S4_storeiri_io:
4119 case Hexagon::dup_S4_storeiri_io:
4120
4121 Src1Reg = MI.getOperand(0).getReg();
4123 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4124 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4126 break;
4127 case Hexagon::S4_storeirb_io:
4128 case Hexagon::dup_S4_storeirb_io:
4129
4130 Src1Reg = MI.getOperand(0).getReg();
4132 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4133 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4135 break;
4136 case Hexagon::S2_allocframe:
4137 case Hexagon::dup_S2_allocframe:
4138 if (MI.getOperand(2).isImm() &&
4139 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4141 break;
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160 case Hexagon::A2_addi:
4161 case Hexagon::dup_A2_addi:
4162 DstReg = MI.getOperand(0).getReg();
4163 SrcReg = MI.getOperand(1).getReg();
4165
4166 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4168 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4170
4171 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4172 isInt<7>(MI.getOperand(2).getImm()))
4174
4175
4177 ((MI.getOperand(2).getImm() == 1) ||
4178 (MI.getOperand(2).getImm() == -1)))
4180 }
4181 break;
4182 case Hexagon::A2_add:
4183 case Hexagon::dup_A2_add:
4184
4185 DstReg = MI.getOperand(0).getReg();
4186 Src1Reg = MI.getOperand(1).getReg();
4187 Src2Reg = MI.getOperand(2).getReg();
4191 break;
4192 case Hexagon::A2_andir:
4193 case Hexagon::dup_A2_andir:
4194
4195
4196
4197 DstReg = MI.getOperand(0).getReg();
4198 SrcReg = MI.getOperand(1).getReg();
4200 MI.getOperand(2).isImm() &&
4201 ((MI.getOperand(2).getImm() == 1) ||
4202 (MI.getOperand(2).getImm() == 255)))
4204 break;
4205 case Hexagon::A2_tfr:
4206 case Hexagon::dup_A2_tfr:
4207
4208 DstReg = MI.getOperand(0).getReg();
4209 SrcReg = MI.getOperand(1).getReg();
4212 break;
4213 case Hexagon::A2_tfrsi:
4214 case Hexagon::dup_A2_tfrsi:
4215
4216
4217
4218
4219 DstReg = MI.getOperand(0).getReg();
4222 break;
4223 case Hexagon::C2_cmoveit:
4224 case Hexagon::C2_cmovenewit:
4225 case Hexagon::C2_cmoveif:
4226 case Hexagon::C2_cmovenewif:
4227 case Hexagon::dup_C2_cmoveit:
4228 case Hexagon::dup_C2_cmovenewit:
4229 case Hexagon::dup_C2_cmoveif:
4230 case Hexagon::dup_C2_cmovenewif:
4231
4232
4233
4234 DstReg = MI.getOperand(0).getReg();
4235 SrcReg = MI.getOperand(1).getReg();
4237 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4238 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4240 break;
4241 case Hexagon::C2_cmpeqi:
4242 case Hexagon::dup_C2_cmpeqi:
4243
4244 DstReg = MI.getOperand(0).getReg();
4245 SrcReg = MI.getOperand(1).getReg();
4246 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4248 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4250 break;
4251 case Hexagon::A2_combineii:
4252 case Hexagon::A4_combineii:
4253 case Hexagon::dup_A2_combineii:
4254 case Hexagon::dup_A4_combineii:
4255
4256 DstReg = MI.getOperand(0).getReg();
4258 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4259 (MI.getOperand(1).isGlobal() &&
4260 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4261 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4262 (MI.getOperand(2).isGlobal() &&
4263 isUInt<2>(MI.getOperand(2).getOffset()))))
4265 break;
4266 case Hexagon::A4_combineri:
4267 case Hexagon::dup_A4_combineri:
4268
4269
4270 DstReg = MI.getOperand(0).getReg();
4271 SrcReg = MI.getOperand(1).getReg();
4273 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4274 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4276 break;
4277 case Hexagon::A4_combineir:
4278 case Hexagon::dup_A4_combineir:
4279
4280 DstReg = MI.getOperand(0).getReg();
4281 SrcReg = MI.getOperand(2).getReg();
4283 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4284 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4286 break;
4287 case Hexagon::A2_sxtb:
4288 case Hexagon::A2_sxth:
4289 case Hexagon::A2_zxtb:
4290 case Hexagon::A2_zxth:
4291 case Hexagon::dup_A2_sxtb:
4292 case Hexagon::dup_A2_sxth:
4293 case Hexagon::dup_A2_zxtb:
4294 case Hexagon::dup_A2_zxth:
4295
4296 DstReg = MI.getOperand(0).getReg();
4297 SrcReg = MI.getOperand(1).getReg();
4300 break;
4301 }
4302
4304}
4305
4307 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4308}
4309
4312
4313
4314 if (!ItinData)
4316
4317 if (MI.isTransient())
4318 return 0;
4320}
4321
4322
4323
4324
4325
4326
4327
4328
4329
4332 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4334
4335
4337
4341 int Idx = DefMI.findRegisterDefOperandIdx(SR, &HRI, false, false);
4342 if (Idx != -1) {
4343 DefIdx = Idx;
4344 break;
4345 }
4346 }
4347 }
4348
4352 int Idx = UseMI.findRegisterUseOperandIdx(SR, &HRI, false);
4353 if (Idx != -1) {
4354 UseIdx = Idx;
4355 break;
4356 }
4357 }
4358 }
4359 }
4360
4362 ItinData, DefMI, DefIdx, UseMI, UseIdx);
4364
4365
4366
4369}
4370
4371
4372
4373
4376 if (Cond.empty())
4377 return false;
4379 Cond[0].setImm(Opc);
4380 return true;
4381}
4382
4384 int InvPredOpcode;
4385 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4386 : Hexagon::getTruePredOpcode(Opc);
4387 if (InvPredOpcode >= 0)
4388 return InvPredOpcode;
4389
4391}
4392
4393
4395 const uint64_t F = MI.getDesc().TSFlags;
4400
4401 if (isSigned)
4402 return ~(-1U << (bits - 1));
4403 else
4404 return ~(-1U << bits);
4405}
4406
4407
4409 switch (MI.getOpcode()) {
4410 case Hexagon::L2_loadrbgp:
4411 case Hexagon::L2_loadrdgp:
4412 case Hexagon::L2_loadrhgp:
4413 case Hexagon::L2_loadrigp:
4414 case Hexagon::L2_loadrubgp:
4415 case Hexagon::L2_loadruhgp:
4416 case Hexagon::S2_storerbgp:
4417 case Hexagon::S2_storerbnewgp:
4418 case Hexagon::S2_storerhgp:
4419 case Hexagon::S2_storerhnewgp:
4420 case Hexagon::S2_storerigp:
4421 case Hexagon::S2_storerinewgp:
4422 case Hexagon::S2_storerdgp:
4423 case Hexagon::S2_storerfgp:
4424 return true;
4425 }
4426 const uint64_t F = MI.getDesc().TSFlags;
4427 unsigned addrMode =
4429
4430
4434}
4435
4437
4438
4439
4440
4441 if (MI.getOpcode() == Hexagon::A4_ext)
4442 return false;
4443
4446}
4447
4449 const uint64_t F = MI.getDesc().TSFlags;
4452}
4453
4455 bool ToBigInstrs) const {
4456 int Opcode = -1;
4457 if (ToBigInstrs) {
4458
4460
4462 } else
4464
4465
4466 if (Opcode >= 0)
4467 MII->setDesc(get(Opcode));
4468}
4469
4470
4471
4473 bool ToBigInstrs) const {
4474 for (auto &MB : MF)
4476 End = MB.instr_end();
4477 Instr != End; ++Instr)
4479}
4480
4481
4485 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4487 ++MII;
4488 }
4489}
4490
4492 using namespace HexagonII;
4493
4494 const uint64_t F = MI.getDesc().TSFlags;
4495 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4496 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4497 if (Size != 0)
4498 return Size;
4499
4500 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4502
4503
4505 switch (S) {
4507 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4508 default:
4510 }
4511}
4512
4513
4515 const uint64_t F = MI.getDesc().TSFlags;
4520
4521 if (isSigned)
4522 return -1U << (bits - 1);
4523 else
4524 return 0;
4525}
4526
4527
4529
4530
4531 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4532 if (NonExtOpcode >= 0)
4533 return NonExtOpcode;
4534
4535 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4536
4539 return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4541 return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4543 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4544
4545 default:
4546 return -1;
4547 }
4548 }
4549 return -1;
4550}
4551
4553 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4554 if (Cond.empty())
4555 return false;
4558 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4559 return false;
4560 }
4561 PredReg = Cond[1].getReg();
4562 PredRegPos = 1;
4563
4564 PredRegFlags = 0;
4565 if (Cond[1].isImplicit())
4569 return true;
4570}
4571
4573 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4574}
4575
4577 return Hexagon::getRegForm(MI.getOpcode());
4578}
4579
4580
4581
4582
4583
4585 if (MI.isDebugInstr() || MI.isPosition())
4586 return 0;
4587
4588 unsigned Size = MI.getDesc().getSize();
4590
4591
4593
4596
4597
4602
4603
4604 unsigned NumDefs = 0;
4605 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4606 ++NumDefs)
4607 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4608
4609 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4610
4611 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4613 }
4614
4615 return Size;
4616}
4617
4619 const uint64_t F = MI.getDesc().TSFlags;
4621}
4622
4625 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4626
4628}
4629
4630
4633}
4634
4637 assert(BundleHead->isBundle() && "Not a bundle header");
4639
4641}
4642
4643
4644
4647 "Instruction must be extendable");
4648
4651
4653 "Branch with unknown extendable field type");
4654
4656}
4657
4660 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4665 int TargetPos = MI.getNumOperands() - 1;
4666
4667
4668 while ((TargetPos > -1) && .getOperand(TargetPos).isMBB())
4669 --TargetPos;
4670 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4671 MI.getOperand(TargetPos).setMBB(NewTarget);
4674 }
4675 MI.setDesc(get(NewOpcode));
4676 return true;
4677}
4678
4680
4686
4687 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4688 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4694 }
4695
4696}
4697
4698
4699
4700
4704 return true;
4705}
4706
4707
4709 int PredRevOpcode = -1;
4711 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4712 else
4713 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4714 assert(PredRevOpcode > 0);
4715 return PredRevOpcode;
4716}
4717
4718
4720 const {
4721 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4722}
4723
4726 assert(MIB->isBundle());
4728 if (Operand.isImm())
4729 Operand.setImm(Operand.getImm() | memShufDisabledMask);
4730 else
4732}
4733
4737 return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4738}
4739
4740
4742 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4743}
4744
4746 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4747}
4748
4750 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4751}
4752
4754 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4755}
4756
4758 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4759}
4760
4762 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4763}
4764
4766 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4767}
4768
4770 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4771}
4772
4775
4779}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool mayAlias(MachineInstr &MIa, SmallVectorImpl< MachineInstr * > &MemInsns, AliasAnalysis *AA)
static bool isConstant(const MachineInstr &MI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static const Function * getParent(const Value *V)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static bool isSigned(unsigned int Opcode)
const HexagonInstrInfo * TII
static bool isUndef(ArrayRef< int > Mask)
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::desc("Disable schedule adjustment for new value stores."))
const int Hexagon_MEMH_OFFSET_MAX
const int Hexagon_MEMB_OFFSET_MAX
const int Hexagon_MEMH_OFFSET_MIN
const int Hexagon_MEMD_OFFSET_MAX
static cl::opt< bool > EnableTimingClassLatency("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
const int Hexagon_MEMD_OFFSET_MIN
const int Hexagon_ADDI_OFFSET_MAX
static cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
const int Hexagon_MEMW_OFFSET_MIN
cl::opt< bool > ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))
const int Hexagon_ADDI_OFFSET_MIN
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::desc("branch relax asm"))
static void parseOperands(const MachineInstr &MI, SmallVectorImpl< Register > &Defs, SmallVectorImpl< Register > &Uses)
Gather register def/uses from MI.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
const int Hexagon_MEMB_OFFSET_MIN
static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE)
Calculate number of instructions excluding the debug instructions.
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI)
static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::desc("Use the DFA based hazard recognizer."))
static bool isIntRegForSubInst(Register Reg)
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
#define HEXAGON_INSTR_SIZE
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
uint64_t IntrinsicInst * II
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
static StringRef getName(Value *V)
static bool isBranch(unsigned Opcode)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
Remove Loads Into Fake Uses
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
const Constant * getInitializer() const
getInitializer - Return the initializer for this global variable.
short getEquivalentHWInstr(const MachineInstr &MI) const
int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore=true) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
short changeAddrMode_abs_io(short Opc) const
bool isRestrictNoSlot1Store(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
bool isVecALU(const MachineInstr &MI) const
bool isCompoundBranchInstr(const MachineInstr &MI) const
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool isJumpR(const MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
bool isPredictedTaken(unsigned Opcode) const
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
unsigned getInvertedPredicatedOpcode(const int Opc) const
bool isPureSlot0(const MachineInstr &MI) const
bool doesNotReturn(const MachineInstr &CallMI) const
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool getPredReg(ArrayRef< MachineOperand > Cond, Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
bool isPredicatedNew(const MachineInstr &MI) const
bool isSignExtendingLoad(const MachineInstr &MI) const
bool isVecAcc(const MachineInstr &MI) const
bool reversePredSense(MachineInstr &MI) const
unsigned getAddrMode(const MachineInstr &MI) const
MCInst getNop() const override
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
bool mayBeNewStore(const MachineInstr &MI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
bool isAddrModeWithOffset(const MachineInstr &MI) const
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
bool isBaseImmOffset(const MachineInstr &MI) const
bool isAbsoluteSet(const MachineInstr &MI) const
short changeAddrMode_io_pi(short Opc) const
short changeAddrMode_pi_io(short Opc) const
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
bool isLoopN(const MachineInstr &MI) const
bool isSpillPredRegOp(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isIndirectCall(const MachineInstr &MI) const
short changeAddrMode_ur_rr(short Opc) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
bool hasNonExtEquivalent(const MachineInstr &MI) const
bool isConstExtended(const MachineInstr &MI) const
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
int getCondOpcode(int Opc, bool sense) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
bool isAccumulator(const MachineInstr &MI) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
bool PredOpcodeHasJMP_c(unsigned Opcode) const
bool isNewValue(const MachineInstr &MI) const
Register createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
bool isDotCurInst(const MachineInstr &MI) const
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
bool isExtended(const MachineInstr &MI) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
bool isAsCheapAsAMove(const MachineInstr &MI) const override
int getMaxValue(const MachineInstr &MI) const
bool isPredicateLate(unsigned Opcode) const
short changeAddrMode_rr_ur(short Opc) const
bool hasPseudoInstrPair(const MachineInstr &MI) const
bool isNewValueInst(const MachineInstr &MI) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override
Measure the specified inline asm to determine an approximation of its length.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
int getNonDotCurOp(const MachineInstr &MI) const
bool isIndirectL4Return(const MachineInstr &MI) const
unsigned reversePrediction(unsigned Opcode) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
InstrStage::FuncUnits getUnits(const MachineInstr &MI) const
unsigned getMemAccessSize(const MachineInstr &MI) const
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Store the specified register of the given register class to the specified stack frame index.
bool isComplex(const MachineInstr &MI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
int getDotNewOp(const MachineInstr &MI) const
void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const
bool isMemOp(const MachineInstr &MI) const
int getDotOldOp(const MachineInstr &MI) const
short getPseudoInstrPair(const MachineInstr &MI) const
bool hasUncondBranch(const MachineBasicBlock *B) const
short getNonExtOpcode(const MachineInstr &MI) const
bool isTailCall(const MachineInstr &MI) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool isDeallocRet(const MachineInstr &MI) const
unsigned getCExtOpNum(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isLateSourceInstr(const MachineInstr &MI) const
bool isDotNewInst(const MachineInstr &MI) const
void translateInstrsForDup(MachineFunction &MF, bool ToBigInstrs=true) const
bool isTC1(const MachineInstr &MI) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const
unsigned getSize(const MachineInstr &MI) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
short changeAddrMode_io_abs(short Opc) const
int getDotCurOp(const MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool isExpr(unsigned OpType) const
void genAllInsnTimingClasses(MachineFunction &MF) const
bool isTC2Early(const MachineInstr &MI) const
bool hasEHLabel(const MachineBasicBlock *B) const
bool shouldSink(const MachineInstr &MI) const override
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_rr_io(short Opc) const
bool isHVXVec(const MachineInstr &MI) const
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
short changeAddrMode_io_rr(short Opc) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Emit instructions to copy a pair of physical registers.
bool mayBeCurLoad(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
bool isNewValueJump(const MachineInstr &MI) const
bool isTC4x(const MachineInstr &MI) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool isFloat(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Load the specified register of the given register class from the specified stack frame index.
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, LocationSize &AccessSize) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
uint64_t getType(const MachineInstr &MI) const
bool isEndLoopN(unsigned Opcode) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
bool isExtendable(const MachineInstr &MI) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
HexagonInstrInfo(HexagonSubtarget &ST)
bool isPredicatedTrue(const MachineInstr &MI) const
bool isNewValueStore(const MachineInstr &MI) const
int getMinValue(const MachineInstr &MI) const
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTC2(const MachineInstr &MI) const
Register getStackRegister() const
Register getFrameRegister(const MachineFunction &MF) const override
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
bool usePredicatedCalls() const
const HexagonRegisterInfo * getRegisterInfo() const override
bool useNewValueStores() const
Itinerary data supplied by a subtarget to be used by a target.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< MCPhysReg, const MachineOperand * > > &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle).
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
Represents a single loop in the control flow graph.
This class is intended to be used as a base class for asm properties and features specific to the tar...
virtual unsigned getMaxInstLength(const MCSubtargetInfo *STI=nullptr) const
Returns the maximum possible encoded instruction size in bytes.
StringRef getCommentString() const
const char * getSeparatorString() const
MCInstBuilder & addInst(const MCInst *Val)
Add a new MCInst operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Wrapper class representing physical registers. Should be passed by value.
instr_iterator instr_begin()
MachineInstrBundleIterator< const MachineInstr > const_iterator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
Instructions::iterator instr_iterator
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
instr_iterator instr_end()
Instructions::const_iterator const_instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
iterator_range< succ_iterator > successors()
iterator_range< pred_iterator > predecessors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
instr_iterator getInstrIterator() const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
unsigned getNumOperands() const
Retuns the total number of operands.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
A description of a memory reference used in the backend.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
unsigned getTargetFlags() const
static MachineOperand CreateImm(int64_t Val)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
void addTargetFlag(unsigned F)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
size_t count(char C) const
Return the number of occurrences of C in the string.
Object returned by analyzeLoopForPipelining.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Primary interface to the complete machine description for the target machine.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSlot0Only(unsigned units)
unsigned const TypeCVI_LAST
unsigned const TypeCVI_FIRST
@ RestrictNoSlot1StoreMask
@ RestrictNoSlot1StorePos
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool is_TC1(unsigned SchedClass)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
auto reverse(ContainerTy &&C)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
bool is_TC2(unsigned SchedClass)
unsigned getUndefRegState(bool B)
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
bool is_TC2early(unsigned SchedClass)
unsigned getKillRegState(bool B)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
bool is_TC4x(unsigned SchedClass)
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
These values represent a non-pipelined step in the execution of an instruction.
FuncUnits getUnits() const
Returns the choice of FUs.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.