LLVM: lib/Target/AMDGPU/R600InstrInfo.cpp File Reference (original) (raw)
R600 Implementation of TargetInstrInfo. More...
#include "[R600InstrInfo.h](R600InstrInfo%5F8h%5Fsource.html)"#include "[MCTargetDesc/R600MCTargetDesc.h](R600MCTargetDesc%5F8h%5Fsource.html)"#include "[R600Defines.h](R600Defines%5F8h%5Fsource.html)"#include "[R600Subtarget.h](R600Subtarget%5F8h%5Fsource.html)"#include "[llvm/ADT/SmallSet.h](SmallSet%5F8h%5Fsource.html)"#include "[llvm/CodeGen/MachineFrameInfo.h](MachineFrameInfo%5F8h%5Fsource.html)"#include "R600GenDFAPacketizer.inc"#include "R600GenInstrInfo.inc"
Go to the source code of this file.
| Macros | |
|---|---|
| #define | GET_INSTRINFO_CTOR_DTOR |
| #define | GET_INSTRINFO_CTOR_DTOR |
| #define | GET_INSTRMAP_INFO |
| #define | GET_INSTRINFO_NAMED_OPS |
| #define | OPERAND_CASE(Label) |
| Functions | |
|---|---|
| static std::vector< std::pair< int, unsigned > > | Swizzle (std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz) |
| static unsigned | getTransSwizzle (R600InstrInfo::BankSwizzle Swz, unsigned Op) |
| static bool | NextPossibleSolution (std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, unsigned Idx) |
| Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swizzle sequence assuming that all swizzles after Idx can be skipped. | |
| static bool | isConstCompatible (R600InstrInfo::BankSwizzle TransSwz, const std::vector< std::pair< int, unsigned > > &TransOps, unsigned ConstCount) |
| Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr at cycle 1 if they read 2 const. | |
| static bool | isPredicateSetter (unsigned Opcode) |
| static MachineInstr * | findFirstPredicateSetterFrom (MachineBasicBlock &MBB, MachineBasicBlock::iterator I) |
| static bool | isJump (unsigned Opcode) |
| static bool | isBranch (unsigned Opcode) |
| static MachineBasicBlock::iterator | FindLastAluClause (MachineBasicBlock &MBB) |
| static R600::OpName | getSlotedOps (R600::OpName Op, unsigned Slot) |
R600 Implementation of TargetInstrInfo.
Definition in file R600InstrInfo.cpp.
◆ GET_INSTRINFO_CTOR_DTOR [1/2]
#define GET_INSTRINFO_CTOR_DTOR
◆ GET_INSTRINFO_CTOR_DTOR [2/2]
#define GET_INSTRINFO_CTOR_DTOR
◆ GET_INSTRINFO_NAMED_OPS
#define GET_INSTRINFO_NAMED_OPS
◆ GET_INSTRMAP_INFO
#define GET_INSTRMAP_INFO
◆ OPERAND_CASE
| #define OPERAND_CASE | ( | Label | ) |
|---|
Value:
case Label: { \
static const R600::OpName Ops[] = {Label##_X, Label##_Y, Label##_Z, \
Label##_W}; \
return Ops[Slot]; \
}
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Definition at line 1241 of file R600InstrInfo.cpp.
Referenced by getSlotedOps().
◆ findFirstPredicateSetterFrom()
◆ FindLastAluClause()
◆ getSlotedOps()
| R600::OpName getSlotedOps ( R600::OpName Op, unsigned Slot ) | static |
|---|
◆ getTransSwizzle()
◆ isBranch()
Definition at line 632 of file R600InstrInfo.cpp.
Referenced by llvm::R600InstrInfo::analyzeBranch(), decodePCDBLOperand(), llvm::HexagonShuffler::GetPacketSummary(), llvm::HexagonMCInstrInfo::isConstExtended(), llvm::HexagonInstrInfo::isPredictedTaken(), llvm::MCInstrAnalysis::mayAffectControlFlow(), llvm::HexagonInstrInfo::reverseBranchCondition(), translateImmediate(), tryAddingSymbolicOperand(), tryAddingSymbolicOperand(), and tryAddingSymbolicOperand().