Upsample - Resample input at higher rate by inserting zeros - Simulink (original) (raw)

Resample input at higher rate by inserting zeros

Libraries:
DSP System Toolbox / Signal Operations
DSP System Toolbox HDL Support / Signal Operations

Description

The Upsample block resamples each channel of the_M_i-by-N input at a rate_L_ times higher than the input sample rate by inserting_L_−1 zeros between consecutive samples. Specify the integer_L_ in the Upsample factor, L parameter or through the input port L.

You can use this block inside triggered subsystems when you set the Rate options parameter to Enforce single-rate processing.

Examples

Ports

Input

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Specify the input signal as a real or a complex-valued scalar, vector, or a matrix signal.

When you set Input processing toColumns as channels (frame based) andRate options to Enforce single-rate processing, the input can be a variable-size signal. When the input is a variable-size signal, the frame size (number of rows) and the number of channels (columns) of the signal can change during simulation.

This port is unnamed until you set Upsample factor source to Input port. (since R2023a)

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point
Complex Number Support: Yes

Since R2023a

Specify the upsample factor L as a positive integer less than or equal to the value you specify in the Maximum upsample factor, Lmax parameter.

Dependency

To enable this port, set the Upsample factor source parameter to Input port.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

Output

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The Upsample block outputs a signal that has the same data type and complexity as the input signal. The size of the output depends on the value of the upsample factor and the option you select in theRate options parameter.

If you set Upsample factor, L to L andRate options to:

When you input the upsample factor through the input port L, the Rate options parameter is automatically set toEnforce single-rate processing. In this case, the block maintains the input sample rate at the output by increasing the output frame size by a factor of_L_. (since R2023a)

The output is a variable-size signal when one or both of these conditions are met:

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point
Complex Number Support: Yes

Parameters

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Since R2023a

Specify the upsample factor through one of these options:

Specify the upsample factor L by which to increase the input sample rate as a positive integer.

Dependency

To enable this parameter, setUpsample factor source to Dialog parameter. (since R2023a)

Specify the sample offset D as an integer in the range [0, _L_−1].

Use the Sample offset (0 to L−1) parameter to delay the output samples by a specific number of sample periods. Doing so enables you to select any of the L possible output phases. The value you specify in the Sample offset (0 to L−1) parameter must be an integer in the range 0≤D<(L−1).

When you input the upsample factor through the input port L, the Sample offset (0 to L−1) parameter is not enabled in the block dialog box. In this case, the sample offset D is automatically set to 0. (since R2023a)

Dependency

To enable this parameter, setUpsample factor source to Dialog parameter. (since R2023a)

Since R2023a

Specify the maximum upsample factor Lmax as a positive integer greater than or equal to 1. The upsample factor you specify through the input port L must be less than or equal to Lmax.

Dependency

To enable this parameter, set Upsample factor source to Input port.

Specify how the block should process the input. You can set this parameter to one of these options:

Dependency

To enable this parameter, setUpsample factor source to Dialog parameter. (since R2023a)

When you set Upsample factor source to Input port, the Input processing parameter is automatically set to Columns as channels (frame based). (since R2023a)

Specify the method that the block uses to upsample the input. You can select one of the following options:

Dependency

To enable this parameter, setUpsample factor source to Dialog parameter. (since R2023a)

When you set Upsample factor source to Input port, the Rate options parameter is automatically set toEnforce single-rate processing. (since R2023a)

Specify the value with which the block is initialized for cases of nonzero latency as a scalar, vector, or a matrix. The scalar value appears in the output as the sample D+1. If this parameter is set to a vector or a matrix, the size of this parameter should be the same as that of the input. This parameter appears only when you configure the block to perform multirate processing.

Dependencies

To enable this parameter, set Rate options to Allow multirate processing.

Block Characteristics

Data Types Boolean | double fixed point integer single
Direct Feedthrough no
Multidimensional Signals no
Variable-Size Signals yes
Zero-Crossing Detection no

More About

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When you set the Input processing parameter to Columns as channels (frame based), the block upsamples each column of the input over time. In this mode, the block can perform either single-rate or multirate processing. You can use the Rate options parameter to specify how the block upsamples the input.

When you set the Input processing parameter toElements as channels (sample based), the block treats an M_-by-N matrix input as_M*N independent channels, and upsamples each channel over time. In this mode, the block always performs multirate processing. The output sample rate is L times higher than the input sample rate (Tso = Tsi/L), and the input and output sizes are identical.

The Upsample block has zero-tasking latency for all single-rate operations. The block is in a single-rate mode if you specify an upsample factor of 1 or if you set the Input processing parameter to Columns as channels (frame based) and the Rate options parameter toEnforce single-rate processing.

The Upsample block also has zero-tasking latency for multirate operations if you run your model in Simulink® single-tasking mode.

Zero-tasking latency means that the block propagates the first input (received at_t_ = 0) immediately after the consecutive zeros_D_, which you specify in the Sample offset (0 to L−1) parameter. When you input the upsample factor through the input port L, D = 0. This output (D+1) is followed in turn by the _L_−1 inserted zeros and the next input sample.

The Upsample block has tasking latency for a multirate multitasking operation:

Extended Capabilities

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Generated code relies on the memcpy ormemset function (string.h) under certain conditions.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

Best Practices

Consider whether your model can use the Repeat block instead of theUpsample block. The Repeat block uses fewer hardware resources, so as a best practice use the Upsample block only when your algorithm requires zero-padding upsampling.

See also Multirate Model Requirements for HDL Code Generation (HDL Coder).

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline (HDL Coder).
OutputPipeline Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline (HDL Coder).

Restrictions

Complex Data Support

This block supports code generation for complex signals.

Version History

Introduced before R2006a

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Starting in R2025a, when you use the clock-rate pipelining optimization, the Upsample block does not act as a barrier to the optimization. As a result, clock-rate pipelining optimizes multirate designs more effectively by reducing the large amount of latency and unbalanced delays that could have previously occurred. For example, in previous releases, a multirate design with feedback loops might generate delay balancing errors when you enabled clock-rate pipelining. In R2025a, these designs do not generate delay balancing errors.

You can now specify the upsample factor through an input port when theUpsample block operates in the single-rate frame-based processing mode. When you specify the upsample factor through the input port, you can change the factor during simulation.

Starting in R2022b, when you set Input processing toColumns as channels (frame based) and Rate options to Enforce single-rate processing, the input can be a variable-size signal. That is, the frame size (number of rows) and the number of channels (columns) of the signal can change during simulation.

When the input is a variable-size signal, the output is also a variable-size signal.