Multi-file test bench - Divide generated test bench into helper functions, data, and HDL test bench code files - MATLAB (original) (raw)

Divide generated test bench into helper functions, data, and HDL test bench code files

Model Configuration Pane: Test Bench

Description

You can use this setting to specify how you want to divide files that contain the test bench code, data, and helper functions.

The file names are derived from the name of the DUT, the Test bench name postfix property, and the Test bench data file name postfix property as:

DUTname_ TestBenchPostfix_ TestBenchDataPostfix

For example, if the DUT name is symmetric_fir, and the target language is VHDL®, the default test bench file names are:

If the DUT name is symmetric_fir and the target language is Verilog®, the default test bench file names are:

If the DUT name is symmetric_fir and the target language is SystemVerilog, the default test bench file names are:

Dependencies

When this property is selected, Test bench data file name postfix is enabled.

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Settings

Off (default) | On

On

Write three separate HDL files. There is a separate file for test bench code, helper functions, and test bench data.

Off

Write two separate HDL files. One file contains the HDL test bench code. The other file contains the helper functions package and test bench data.

Tips

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

No recommendations.

Programmatic Use

Parameter: MultifileTestBench
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Version History

Introduced in R2012a