makehdltb - Generate HDL test bench from model or subsystem - MATLAB (original) (raw)

Generate HDL test bench from model or subsystem

Syntax

Description

makehdltb([dut](#btke2q9%5Fsep%5Fshared-dut)) generates an HDL test bench from the specified subsystem or model reference.

example

makehdltb([dut](#btke2q9%5Fsep%5Fshared-dut),[Name,Value](#namevaluepairarguments)) generates an HDL test bench from the specified subsystem or model reference with options specified by one or more name-value pair arguments.

Note

If you have not previously executedmakehdl within the current MATLAB® session, makehdltb callsmakehdl to generate model code before generating the test bench code. Properties passed in tomakehdl persist aftermakehdl executes, and (unless explicitly overridden) are passed to subsequentmakehdltb calls during the same MATLAB session.
Test bench code and model code must both be generated in the same target language. If the target language specified formakehdltb differs from the target language specified for the previous makehdl execution, makehdltb regenerates model code in the same language specified for the test bench.

example

Examples

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Generate VHDL® DUT and test bench for a subsystem.

Use makehdl to generate VHDL code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir')

Generating HDL for 'sfir_fixed/symmetric_fir'.

Starting HDL check.

HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings,

and 0 messages.

Begin VHDL Code Generation for 'sfir_fixed'.

Working on sfir_fixed/symmetric_fir as

hdlsrc\sfir_fixed\symmetric_fir.vhd

HDL code generation complete.

After makehdl is complete, use makehdltb to generate a VHDL test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir')

Begin TestBench generation.

Generating HDL TestBench for 'sfir_fixed/symmetric_fir'.

Begin simulation of the model 'gm_sfir_fixed'...

Collecting data...

Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.vhd

Creating stimulus vectors...

HDL TestBench generation complete.

The generated VHDL test bench code is saved in the hdlsrc folder.

Generate Verilog® DUT and test bench for a subsystem.

Use makehdl to generate Verilog code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

Generating HDL for 'sfir_fixed/symmetric_fir'.

Starting HDL check.

HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings,

and 0 messages.

Begin Verilog Code Generation for 'sfir_fixed'.

Working on sfir_fixed/symmetric_fir as

hdlsrc\sfir_fixed\symmetric_fir.v

HDL code generation complete.

After makehdl is complete, use makehdltb to generate a Verilog test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

Begin TestBench generation.

Generating HDL TestBench for 'sfir_fixed/symmetric_fir'.

Begin simulation of the model 'gm_sfir_fixed'...

Collecting data...

Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.v

Creating stimulus vectors...

HDL TestBench generation complete.

The generated Verilog test bench code is saved in the hdlsrc\sfir_fixed folder.

Generate SystemVerilog DUT and test bench for a subsystem.

Use makehdl to generate SystemVerilog code for the subsystemsymmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','SystemVerilog')

After makehdl is complete, usemakehdltb to generate a SystemVerilog test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','SystemVerilog')

The generated SystemVerilog test bench code for thesymmetric_fir subsystem is saved in thehdlsrc\sfir_fixed\symmetric_fir_tb.sv.

Generate SystemVerilog DPI test bench for a subsystem.

Consider this option if generation or simulation of the default HDL test bench takes a long time. Generation of a DPI test bench can be faster than the default version because it does not run a Simulink® simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file. For requirements to use this feature, see the GenerateSVDPITestBench property.

Use makehdl to generate Verilog code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

Generating HDL for 'sfir_fixed/symmetric_fir'.

Starting HDL check.

HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings,

and 0 messages.

Begin Verilog Code Generation for 'sfir_fixed'.

Working on sfir_fixed/symmetric_fir as

hdlsrc\sfir_fixed\symmetric_fir.v

HDL code generation complete.

After the code is generated, use makehdltb to generate a test bench for the same subsystem. Specify your HDL simulator so that the code generator can generate scripts to build and run the generated SystemVerilog and C code. Disable generation of the default test bench.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog',... 'GenerateSVDPITestBench','ModelSim','GenerateHDLTestBench','off')

Start checking model compatibility with SystemVerilog DPI testbench

Finished checking model compatibility with SystemVerilog DPI testbench

Preparing generated model for SystemVerilog DPI component generation

Generating SystemVerilog DPI component

Starting build procedure for model: gm_sfir_fixed_ref

Starting SystemVerilog DPI Component Generation

Generating DPI H Wrapper gm_sfir_fixed_ref_dpi.h

Generating DPI C Wrapper gm_sfir_fixed_ref_dpi.c

Generating SystemVerilog module gm_sfir_fixed_ref_dpi.sv using template C:\matlab\toolbox\hdlverifier\dpigenerator\rtw\hdlverifier_dpitb_template.vgt

Generating makefiles for: gm_sfir_fixed_ref_dpi

Invoking make to build the DPI Shared Library

Successful completion of build procedure for model: gm_sfir_fixed_ref

Working on symmetric_fir_dpi_tb as hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.sv.

Generating SystemVerilog DPI testbench simulation script for ModelSim/QuestaSim hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.do

HDL TestBench generation complete.

The generated SystemVerilog and C test bench files, and the build scripts, are saved in the hdlsrc\sfir_fixed folder.

Input Arguments

Name-Value Arguments

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Specify optional pairs of arguments asName1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: 'TargetLanguage','Verilog'

Target Language and Folder Selection Options

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Specify the Subsystem in your model to generate the test bench for. For more information, see Generate HDL for.

Specify whether to generate VHDL or Verilog code. For more information, see Language.

Specify a path to write the generated files and HDL code into. For more information, see Code Generation Folder.

Test Bench Generation Output Options

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The code generator produces an HDL test bench by running a Simulink simulation to capture input vectors and expected output data for your DUT. For more information, see HDL test bench.

Clock and Reset Input Options

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Specify that the generated test bench drives the clock enable input based on ClockLowTime andClockHighTime.

For more information, see Force clock.

Clock high time during a clock period, specified in nanoseconds.

For more information, see Clock high time (ns).

Clock low time during a clock period, specified in nanoseconds.

For more information, see Clock low time (ns).

Specify that the generated test bench drives the clock enable input.

For more information, see Force clock enable.

Specify that the generated test bench drives the reset input.

For more information, see Force reset.

Testbench Stimulus and Response Parameters

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Hold time for inputs and forced reset, specified in nanoseconds.

For more information, see Hold time (ns).

Testbench Configuration Parameters

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Divide generated test bench into helper functions, data, and HDL test bench files.

For more information, see Multi-file test bench.

Floating Point Tolerance Options

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Floating-point tolerance value depending on theFPToleranceStrategy specified. For more information, see Tolerance Value.

Port Names and Types

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Specify whether to generate single or multiple clock inputs in the HDL code. For more information, see Clock inputs.

Specify whether to use an active-high or active-low asserted level for the reset input signal. For more information, see Reset asserted level.

Specify the clock input port name as a character vector. For more information, see Clock input port.

File and Variable Names

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Specify the file name extension for generated Verilog files. For more information, see Verilog file extension.

Specify the file name extension for generated VHDL files. For more information, see VHDL file extension.

Specify the postfix for the package file name as a character vector. For more information, seePackage postfix.

Coding Style

Script Generation

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The HDL simulation command, specified as a character vector.

For more information, see Simulation command.

Initialization for the HDL simulation script, specified as a character vector.

For more information, see Simulation initialization.

The termination name for the HDL simulation command, specified as a character vector.

For more information, see Simulation termination.

Waveform viewing command, specified as a character vector. The implicit argument adds the signal paths for the DUT top-level input, output, and output reference signals.

For more information, see Simulation waveform viewing command.

Version History

Introduced in R2006b