Reciprocal - Compute reciprocal operation and simulate with latency - Simulink (original) (raw)
Compute reciprocal operation and simulate with latency
Since R2020b
Description
The Reciprocal block performs the reciprocal operation on the input data signal. The block has control signals that indicate whether the input and output data are valid. You can also specify the number of iterations of the algorithm and the latency strategy.
To use this block in your Simulink® model, open the HDLMathLib library by entering this command in the MATLAB® Command Window:
open_system("HDLMathLib")
You can simulate the block with latency. For more information, see Latency Considerations.
Examples
Ports
Input
Data input to calculate the reciprocal, specified as a scalar.
Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Input control signal that indicates whether the input signal is valid, specified as a scalar.
Data Types: Boolean
Output
Output signal that is the reciprocal of the input signal, returned as a scalar.
Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Output control signal that indicates whether output signal is valid, returned as a scalar.
Data Types: Boolean
Parameters
Specify whether to use minimum, maximum, custom, or zero latency. For more information, see Latency Strategy.
To use custom latency for the block, set the Latency strategy toCustom and enter the latency value in the Custom latency field.
You can also control the number of pipeline stages for the iterative algorithm. To customize the latency for iterative algorithm, set theLatency strategy to Custom(PerIteration) and enter the iterations per pipeline value in the IterationsPerPipeline field. (since R2025a)
Programmatic Use
| Block Parameter:latencyMode | |||
|---|---|---|---|
| Type: character vector | |||
| Values: 'Max' |'Min' | 'Custom' | 'Custom(PerIteration)' | 'Zero' |
| Default: 'Max' |
Specify the custom latency value. The latency must be a nonnegative integer in the range [0, _L_], where L is the maximum latency value of Reciprocal block. For more information, see CustomLatency.
Dependency
To use this parameter, set Latency strategy toCustom.
Programmatic Use
| Block Parameter:customLatencyValue |
|---|
| Type: Integer |
| Values: 0 to Max latency |
| Default: 0 |
Since R2025a
Specify the iterations to use per each pipeline stage in the algorithm.
Dependency
To enable this parameter, set Latency strategy toCustom(PerIteration).
Programmatic Use
| Block Parameter:iterationsPerPipelineValue |
|---|
| Type: Integer |
| Values: Positive integer |
| Default: 1 |
Specify the output data type. The data type can be inherited or specified directly.
Programmatic Use
| Block Parameter:OutDataTypeStr | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Type: character vector | |||||||||||
| Values: 'Inherit: Inherit via internal rule' | 'Inherit: Inherit via back propagation' | 'Inherit: Same as first input' | 'int8' | 'uint8' | int16 | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | fixdt(1,16,0) | '' |
| Default: 'Inherit: Inherit via internal rule' |
Specify the rounding mode for fixed-point operations. For more information, see Rounding Modes.
Programmatic Use
| Block Parameter: RndMeth | |||||
|---|---|---|---|---|---|
| Type: character vector | |||||
| Values: 'Zero' | 'Ceiling' | 'Convergent' | 'Floor' | 'Nearest' | 'ROund' | 'Simplest' |
| Default: 'Zero' |
Algorithms
You can simulate the Reciprocal block with latency. This block is a masked subsystem that contains the LumpLatency MATLAB Function block. The subsystem uses this MATLAB Function block to compute the latency based on output data type. The latency of the block is calculated from word-length and fractional-length of fixed-point output.
To view the function that computes the latency of the block, open theLumpLatency block in the masked subsystem. To view inside the mask, click the ⇩ icon on the block.
This table shows how the block calculates the latency based on the setting of theLatency strategy parameter:
| Latency Strategy | Latency Value (L) |
|---|---|
| Max | Uses maximum latency by using the equation L =N + 4, where N is the number of iterations. The software determines the value of N by using the fixed-point input and output data type, as described below. |
| Min | When the output data type is not a custom type, the software calculates the value of L using this equation:L = 2 + ceil( N / 3).When the output data type is a custom type, the software calculates the value of L using this equation:L = 3 + ceil( (N - 1) / 3), |
| Custom | Specifies a custom latency value. To specify the latency, enter a value between zero and the maximum latency in the Custom latency parameter. For more information, see Custom latency. |
| Custom(PerIteration) | Use this setting to control the pipeline stages for the iterative algorithm.Specify the number of pipeline stages per iteration using the IterationsPerPipeline parameter. The block uses the equation L = 2 + floor(N /K), where K is the value of theIterationsPerPipeline parameter. |
| Zero | The latency of the block is 0. |
The software calculates the value of N using the signedness, word length, and fractional length of the fixed-point input and output. The calculation depends on the conditions in this table.
| Conditions | Number of Iterations (N) | ||
|---|---|---|---|
| OutputWL is greater than or equal to_InputWL_ | abs(FractionSum) is less than OutputWL | abs(FractionSum) + 1 is equal to OutputWL | OutputWL + 1 |
| abs(FractionSum) + 1 is not equal to OutputWL | OutputWL | ||
| abs(FractionSum) is greater than or equal to OutputWL | Output is signed | abs(FractionSum) + 2 | |
| Output is unsigned | abs(FractionSum) + 1 | ||
| OutputWL is less than_InputWL_ | abs(FractionSum) is less than InputWL | abs(FractionSum) + 1 is equal to InputWL | InputWL + 1 |
| abs(FractionSum) + 1 is not equal to InputWL | InputWL | ||
| abs(FractionSum) is greater than or equal to InputWL | Output is signed | abs(FractionSum) + 2 | |
| Output is unsigned | abs(FractionSum) + 1 |
Where OutputWL is an output word length and_InputWL_ is an input word length. Fractional length sum_FractionSum_ is the sum of the input fractional length_InputFL_ and output fractional length OutputFL.
When the output data type is a custom type, the software adds one more iteration to the number of iterations it calculates in accordance with the latency table. To determine whether the output data type is a custom type, these conditions must be true:
- InputWL is not equal to OutputWL.
- Input signedness is not equal to output signedness.
- OutputFL is not equal to (InputWL -InputFL - 2) for signed input. OutputFL is not equal to (InputWL - InputFL - 1) for unsigned input.
The Reciprocal block uses pipelined architectures to implement the iteration-based reciprocal algorithm. The number of iterations depends on the word length and fractional length of fixed-point input and output. The block performs a single iteration per pipeline stage and uses multiple pipeline stages for computation. A larger word length can provide higher resolution, but requires more iterations to process. By default, the block uses the maximum latency. For example, if your block requires the 20 iterations, the latency of the block is 24, based on the latency equation in Latency Considerations. When you require more iterations for processing the larger word length, the latency of the block also increases.
You can customize the latency for the iterative algorithm by setting Latency strategy to Custom(PerIteration), which allows you to control the number of iterations per pipeline stages. For example, if your block requires the 20 iterations and you want the block to perform the iterations in four pipeline stages, then set the IterationsPerPipeline to 20/4 = 5. By using the Custom(PerIteration) latency strategy, the latency of the block reduces to 6.
Extended Capabilities
The block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.
HDL Architecture
| Architecture | Description |
|---|---|
| Module (default) | Generate code for the subsystem and the blocks within the subsystem. |
| BlackBox | Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals. |
| No HDL | Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code. |
HDL Block Properties
| General | |
|---|---|
| AdaptivePipelining | Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is inherit. See alsoAdaptivePipelining. |
| BalanceDelays | Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is inherit. See also BalanceDelays. |
| ClockRatePipelining | Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is inherit. See also ClockRatePipelining. |
| ConstrainedOutputPipeline | Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, see ConstrainedOutputPipeline. |
| DistributedPipelining | Pipeline register distribution, or register retiming. The default is inherit. See also DistributedPipelining. |
| DSPStyle | Synthesis attributes for multiplier mapping. The default is none. See also DSPStyle. |
| FlattenHierarchy | Remove subsystem hierarchy from generated HDL code. The default is inherit. See also FlattenHierarchy. |
| InputPipeline | Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline. |
| OutputPipeline | Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline. |
| SharingFactor | Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing. |
| StreamingFactor | Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming. |
Target Specification
This block cannot be the DUT, so the block property settings in the Target Specification tab are ignored.
Limitations
- You cannot use this block in the Synchronous Subsystem.
- The block does not support resource sharing optimization.
Version History
Introduced in R2020b
You can control the pipeline stages for iterative algorithms by setting theLatencyStrategy parameter HDL toCustom(PerIterations), then specifying the number of pipeline stages per iteration by using the IterationsPerPipeline parameter. Use this setting to control the pipeline stages in the generated code and optimize the design for speed and resource utilization.