Unit Delay Enabled Synchronous - Delay input signal by one sample period when external Enable signal is

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Main Content

Delay input signal by one sample period when external Enable signal is true

Libraries:
HDL Coder / Discrete

Description

The Unit Delay Enabled Synchronous block delays the input signal u by one sample period when the external Enable signal is true. When the Enable signal is false, the state and output signal hold the previous value. The Enable signal is true when E is not zero and false when E is zero.

The Unit Delay Enabled Synchronous block implementation consists of aSynchronous Subsystem that contains an Enabled Delay block with a Delay length of one and a State Control block in Synchronous mode. When you use this block in your model and have HDL Coder™ installed, your model generates cleaner HDL code and uses fewer hardware resources due to the Synchronous behavior of the State Control block.

Examples

Limitations

The block does not support vector inputs on the Enable port.
You cannot use the block inside Enabled Subsystem,Triggered Subsystem, or Resettable Subsystem blocks that use Classic semantics. The Subsystem must useSynchronous semantics.

Ports

Input

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The Unit Delay Enabled Synchronous block accepts the input signal of the data types listed below. For more information, seeData Types Supported by Simulink.

The Unit Delay Enabled Synchronous block accepts the Enable signal of the data types listed below. For more information, seeData Types Supported by Simulink.

When the Enable signal is false, the state and output signal hold the previous value. The Enable signal is true when E input is not zero and false when E input is zero.

Output

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Output data type matches input.

Parameters

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The Initial condition can take a scalar input or use the same data type as the input signal. You cannot run the simulation withNaN or Inf as theInitial condition.

Programmatic Use

Block parameter: InitialCondition
Type: character vector
Value: '0' \| '[n]'	'[m n]'
Default: '0'

The Sample time must be a real double scalar that specifies the period or a real double vector of length two that specifies the period and offset. The period and offset must be finite and non-negative with offset less than the period.

Programmatic Use

Block parameter: SampleTime
Type: character vector
Value: '-1' \| '[n]'	'[m n]'
Default: '-1'

Extended Capabilities

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HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline.
ResetType	Suppress reset logic generation. The default is default, which generates reset logic. See also ResetType.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

HDL code generation supports only boolean data type at the Enable port.

Version History

Introduced in R2017b