State Control - Specify synchronous reset and enable behavior for blocks with state - Simulink (original) (raw)

Main Content

Specify synchronous reset and enable behavior for blocks with state

Libraries:
HDL Coder / HDL Subsystems

Description

Use the State Control block to toggle subsystem behavior between the default Simulink® simulation behavior and the synchronous hardware simulation behavior.

See Synchronous Subsystem Behavior with the State Control Block.

Limitations

Subsystem-level Limitations

Model-Level Limitations

Supported Block Modes

The following restrictions apply to blocks in synchronous mode:

Unsupported Blocks

The following blocks are not allowed in synchronous mode:

Parameters

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Specify whether to use synchronous or classic semantics. The default isSynchronous.

Extended Capabilities

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HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture. HDL Coder does not generate HDL code specific to the State Control block. How you set the State Control block affects other blocks inside the subsystem that have state.

Version History

Introduced in R2016a

See Also

Blocks

Topics