SystemVerilog DPI Test Bench - MATLAB & Simulink (original) (raw)

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Generate DPI test bench code from entire Simulink model (requires HDL Verifier™)

When you generate HDL code from a subsystem, you can optionally generate a SystemVerilog test bench. This test bench verifies the generated HDL code by using a C component generated from the entire Simulink® model.

You can access this feature in HDL Workflow Advisor under > , or in the Model Configuration Parameters dialog box, under > . Or, for command-line access, set theGenerateSVDPITestBench property ofmakehdltb.

Functions

Topics

• Verify HDL Design Using SystemVerilog DPI Test Bench
  This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
• Choose a Test Bench for Generated HDL Code
  Select a generated test bench.