Using Triggered Subsystems for HDL Code Generation - MATLAB & Simulink (original) (raw)

The Triggered Subsystem block is a Subsystem block that executes each time the control signal has a trigger value. To learn more about the block, see Triggered Subsystem.

Best Practices

When using triggered subsystems in models targeted for HDL code generation, consider the following:

Using the Signal Editor Block

When you connect outputs from a Signal Editor block to a triggered subsystem, you might need to use a Rate Transition block. To run all triggered subsystem ports at the same rate:

Using Trigger as Clock

Using the trigger as clock in triggered subsystems enables you to partition your design into different clock regions in the generated code. Make sure that theClock edge setting in the Configuration Parameters dialog box matches the Trigger type of the Trigger block inside the triggered subsystem.

For example, you can model:

Note

Using the trigger as clock for triggered subsystems can result in timing mismatches of one cycle during testbench simulation.

Specify Trigger as Clock

Trigger as Clock Without Synchronous Registers

When you use the trigger as clock in triggered subsystem, each triggered subsystem input or output requires synchronization delays immediately outside and immediately inside the subsystem. These delays act as a synchronization interface between the regions running at different rates. HDL Coder™ can allows you to generate HDL code without adding the synchronization delays by enabling the "trigger as clock without synchronous register" option. By default, this option is on.

You can enable or disable this option by using makehdl or hdlset_param function. For example, to generate an HDL code for a DUT subsystem, myDUT in a model, myModel, that uses trigger as a clock for triggered subsystem without having synchronization delays, enter:

makehdl("myModel/myDUT",TriggerAsClockWithoutSyncRegisters="on")

Model Trigger Signal As Clock in Triggered Subsystem

This example shows how to model trigger port of the Triggered Subsystem as a clock signal. Using trigger as clock functionality in the Triggered Subsystem enables you to use trigger signal as a clock in your generated HDL code.

The model TriggerAsClockSingle has a DUT subsystem which contains a Triggered Subsystem. Load and open the TriggerAsClockSingle model by running these commands:

load_system("TriggerAsClockSingle"); set_param("TriggerAsClockSingle",'SimulationCommand','Update') open_system("TriggerAsClockSingle/DUT");

To use trigger signal as clock in your generated HDL code, enable Use trigger signal as clock option in the HDL Code Generation > Global Settings > Ports tab of the configuration settings. Then, generate the HDL code for a DUT subsystem using makehdl command or HDL Coder™ app:

makehdl("TriggerAsClockSingle/DUT")

In the generated HDL code, HDL Coder maps the trigger port of the Triggered Subsystem to the clock. This code snippet shows the HDL code of Triggered Subsystem which uses Trigger signal as a clock.

 Delay1_process : PROCESS (Trigger, reset)
 BEGIN
     IF reset = '1' THEN
         Delay1_out1 <= to_unsigned(16#0000#, 16);
     ELSIF Trigger'EVENT AND Trigger = '1' THEN
         Delay1_out1 <= Gain_out1;
     END IF;
 END PROCESS Delay1_process;

Use Triggered and Resettable Subsystem to Model Clock and Reset Signals

You can model control signals, such as clock and reset, by using the triggered and resettable subsystem. You can use trigger as clock functionality to model trigger port from triggered subsystem as a clock and use resettable subsystem to model reset port from Simulink.

When you use triggered or resettable subsystem in your model targeted for HDL code generation, you can:

Model Single Clock and Reset Signal Using Triggered and Resettable Subsystems

This example shows how to model clock and reset signal using Triggered and Resettable subsystems. You can use trigger as clock functionality to model trigger port from triggered subsystem as a clock and use resettable subsystem to model reset port.

The model ClockAndResetModellingUsingTriggerAsClock has a DUT subsystem which contains a Triggered Subsystem. Load and open the ClockAndResetModellingUsingTriggerAsClock model by running these commands:

load_system("ClockAndResetModellingUsingTriggerAsClock"); set_param("ClockAndResetModellingUsingTriggerAsClock",'SimulationCommand','Update') open_system("ClockAndResetModellingUsingTriggerAsClock/DUT");

A resettable subsystem is placed within the triggered subsystem. Using resettable subsystem, you can model a reset port for your model. Minimize the global reset option so that model has single reset signal from resettable subsystem. To minimize global reset option, enable Minimize global resets in the HDL Code Generation > Global Settings > Ports tab of the configuration settings.

To use trigger signal as clock in your generated HDL code, enable Use trigger signal as clock option in the HDL Code Generation > Global Settings > Ports tab. Then, generate the HDL code for a DUT subsystem using makehdl command or HDL Coder™ app:

makehdl("ClockAndResetModellingUsingTriggerAsClock/DUT")

In the generated HDL code, HDL Coder maps the trigger port of the Triggered Subsystem to the clock. Also, the reset signal is generated from the Resettable subsystem. The HDL code of triggered subsystem shows mapping of trigger port to clock signal in the resettable subsystem.

 module Triggered_Subsystem
             (Trigger,
             Reset_1,
             Input_Data,
             Output_rsvd);

     input   Trigger;
     input   Reset_1;
     input   [1:0] Input_Data;  // ufix2
     output  [3:0] Output_rsvd;  // ufix4

     wire [3:0] Resettable_Subsystem_out1;  // ufix4

     Resettable_Subsystem u_Resettable_Subsystem (.clk(Trigger),
                                                 .Input_Data(Input_Data),  // ufix2
                                                 .Reset_1(Reset_1),
                                                 .Output_rsvd(Resettable_Subsystem_out1)  // ufix4
                                                 );
     assign Output_rsvd = Resettable_Subsystem_out1;

 endmodule  // Triggered_Subsystem

Limitations

HDL Coder supports HDL code generation for triggered subsystems that meet the following conditions:

See Also

Use Triggered Subsystem for Asynchronous Clock Domain

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