Verification - MATLAB & Simulink (original) (raw)

Main Content

Simulation and verification of generated HDL code against original model, and FPGA-in-the-loop

Categories

• Verification Basics
  View differences between original model and HDL implementation
• HDL Test Bench
  Generate a test bench that verifies generated HDL code against test vectors from Simulink®
• Cosimulation
  HDL cosimulation with Simulink (requires HDL Verifier™)
• SystemVerilog DPI Test Bench
  Generate DPI test bench code from entire Simulink model (requires HDL Verifier)
• FPGA-in-the-Loop
  Test design in hardware (requires HDL Verifier)
• FPGA Data Capture
  Capture signal data from live FPGA (requires HDL Verifier)