DVB-S2 LDPC Decoder - Decode LDPC code according to DVB-S2 standard - Simulink (original) (raw)

Decode LDPC code according to DVB-S2 standard

Since R2022a

Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The DVB-S2 LDPC Decoder block implements a low-density parity-check (LDPC) decoder using layered belief propagation with min-sum approximation and normalized min-sum approximation algorithms for decoding LDPC codes according to the Digital Video Broadcast Satellite Second Generation (DVB-S2) standard. The block accepts log-likelihood ratio (LLR) values, a stream of control signals, a frame type, and a code rate as inputs and outputs decoded bits, a stream of control signals, and a signal that indicates when the block is ready to accept new inputs.

The DVB-S2 LDPC Decoder block supports early termination to help improve decoding performance and convergence speeds at high signal-to-noise-ratio (SNR) conditions. The block supports parallelism at two levels 45 and 180. The block supports scalar and vector values through the input/output (I/O) interface. It also supports forward error correction (FEC) frames of type normal and short with all the code rates supported by the DVB-S2 standard. For more information about the DVB-S2 standard, see [1].

The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in DVB-S2 modem development.

Examples

Ports

Input

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LLR values, specified as a scalar or an eight-element column vector.

For HDL code generation, specify this value in signed fixed-point format. The input word length must be in the range from 4 to 16.

Data Types: int8 | int16 | signed fixed point

Control signals accompanying the sample stream, specified as asamplecontrol bus. The bus includes the start,end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

For more details, see Sample Control Bus.

Data Types: bus

Type of FEC frame, specified as a Boolean scalar.

Dependencies

To enable this port, set the FEC frame source parameter toInput port.

Data Types: Boolean

Code rate index, specified as an integer. Code rate index values range from 0 to 10. Each code rate index value represents a specific code rate, as shown in this table.

codeRateIdx Value Code Rate
0 1/4
1 1/3
2 2/5
3 1/2
4 3/5
5 2/3
6 3/4
7 4/5
8 5/6
9 8/9
10 9/10 (not supported for short frame)

You must specify this value in the fixdt(0,4,0) format.

Dependencies

To enable this port, do one of the following:

Data Types: fixdt(0,4,0)

Number of iterations, specified as an unsigned integer in the range from 1 to 63.

If you specify an iter value greater than 63 or less than 1, the block overrides your specification and sets the iter value to8 before decoding.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Max or Early and the Source for number of iterations parameter toInput port.

Data Types: uint8

Since R2024b

Scaling factor index, specified as a scalar. Each scaling factor index value represents a specific scaling factor, as shown in this table.

scalingFactorIdx Value Scaling Factor
0 0.5
1 0.5625
2 0.6250
3 0.6875
4 0.7500
5 0.8125
6 0.8750
7 0.9375
8 1

You must specify this value in the fixdt(0,4,0) format. If you specify a value other than one listed in this table, the block displays a warning message and applies the scaling factor index as 4 and continues its operation.

Dependencies

To enable this port, set the Algorithm parameter toNormalized min-sum and then set the Source for scaling factor parameter to Input port.

Data Types: uint8

Output

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Decoded bits, returned as a scalar or a column vector of size 8.

Data Types: Boolean

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, andvalid control signals, which indicate the boundaries of the frame and the validity of the samples.

For more details, see Sample Control Bus.

Data Types: bus

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 (true) when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is0 (false), the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

Parity check status indicator, returned as a Boolean scalar. The port indicates the status of the parity check after the decoding operation.

Dependencies

To enable this port, select the Enable parity check output port parameter.

Data Types: Boolean

Actual number of iterations the block takes to decode the output, returned as a scalar.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Early.

Data Types: uint8

Parameters

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Select the FEC frame source as Input port orProperty.

Select the FEC frame type as Normal orShort.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property.

Since R2024b

Select the parallelism level as 45 or180.

Select the code rate source as Property orInput port.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property.

Select the code rate.

Note

Code rate of 9/10 is not supported for short frame.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property and set the Code rate source parameter to Property.

Select the type of LDPC decoding algorithm. For more information, see Algorithm.

Since R2024b

Specify the scaling factor.

Dependencies

To enable this parameter, set the Algorithm parameter toNormalized min-sum.

Specify the scaling factor as a scalar in the range 0.5 to 1, incremented by 0.0625. For better performance, it is recommended to use scaling factors 0.75 and 1.

Dependencies

To enable this parameter, set the Algorithm parameter toNormalized min-sum and the Source for scaling factor parameter to Property.

Select the decoding termination criteria.

Select the source for specifying the number of iterations.

You can set the number of iterations by using either an input port or a parameter.

Specify the number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Max and theSource for number of iterations parameter toProperty.

Specify the maximum number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Early and set theSource for number of iterations parameter toProperty.

Select this parameter to enable the parityCheck output port to view the status of the parity check.

Algorithms

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This figure shows the architecture block diagram of the DVB-S2 LDPC Decoder block. The Controller block controls the layer and iteration count of the decoding process. The Variable node RAM block stores the variable node (VN) messages, and the Check node RAM block stores the check node (CN) messages. The Functional Unit block calculates the VN messages and CN messages based on layered belief propagation and either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. The Termination/Parity check status block calculates the parity checks and provides the parity check status after each iteration. For more information about decoding algorithms, see the following sections.

DVB-S2 LDPC decoder block architecture

The implementation of the belief propagation algorithm is based on the decoding algorithm presented in [2]. For a transmitted LDPC-encoded codeword, c, where c=(c0,c1,...,cn−1), the input to the LDPC decoder is the log-likelihood ratio (LLR) value L(ci)=log(Pr(ci=0|channel output for ci)Pr(ci=1|channel output for ci)).

In each iteration, the key components of the algorithm are updated based on these equations:

L(rji)=2 atanh (∏i′∈Vj\itanh(12L(qi′j))),

L(qij)=L(ci)+∑j′∈Ci\jL(rj′i), initialized as L(qij)=L(ci) before the first iteration, and

L(Qi)=L(ci)+∑j′∈CiL(rj′i).

At the end of each iteration, L(Qi) is an updated estimate of the LLR value for the transmitted bit ci. The value L(Qi) is the soft-decision output for ci. If L(Qi)<0, the hard-decision output for ci is 1. Otherwise, the output is 0.

The implementation of the layered belief propagation algorithm is based on the decoding algorithm presented in [3], Section II.A. The decoding loop iterates over subsets of rows (layers) of the PCM. For each row, m, in a layer and each bit index, j, the implementation updates the key components of the algorithm based on these equations:

(1) L(qmj)=L(qj)−Rmj,

(2) Amj=∑n ∈ N(m)n≠jψ(L(qmn)),

(3) smj=∏n ∈ N(m)n≠jsign(L(qmn)),

(4) Rmj=−smjψ(Amj), and

(5) L(qj)=L(qmj)+Rmj.

For each layer, the decoding equation (5) works on the combined input obtained from the current LLR inputs L(qmj) and the previous layer updates Rmj.

Because only a subset of the nodes is updated in a layer, the layered belief propagation algorithm is faster compared to the belief propagation algorithm. To achieve the same error rate as attained with belief propagation decoding, use half the number of decoding iterations when using the layered belief propagation algorithm.

The implementation of the min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

Amj=minn ∈ N(m)n≠j(|L(qmn) |⋅α),

where α is 1.

The implementation of the normalized min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

Amj=minn ∈ N(m)n≠j(|L(qmn) |⋅α),

where α is in the range [0, 1] and is the scaling factor specified by the Scaling factor parameter. This equation is an adaptation of equation (4) presented in [4].

The latency of the block varies based on the input type, frame type, code rate, parallelism level, and number of iterations.

Scalar Input

The latency of the block is equal to (r x _t_) +d + inputLen. In this calculation, r is the number of iterations,t is the number of clocks required to decode one iteration,d is the pipeline delays, which are a fixed value equal to 9, and_inputLen_ is the length of the input data.

The table shows the number of clocks the block requires to decode one iteration for normal and short frame types with different code rates and parallelism levels.

Code Rate Number of Clocks Per Iteration for Parallelism 45 Number of Clocks Per Iteration for Parallelism 180
Normal Short Normal Short
1/4 19,440 5,040 5,400 1,404
1/3 19,200 4,800 5,280 1,320
2/5 19,008 4,752 5,184 1,296
1/2 17,280 4,160 4,680 1,140
3/5 18,432 4,608 4,896 1,224
2/3 14,400 3,600 3,840 960
3/4 13,680 3,072 3,600 816
4/5 13,248 2,800 3,456 740
5/6 12,960 2,832 3,360 740
8/9 10,240 2,560 2,640 660
9/10 10,080 Code rate not supported for short frame 2,592 Code rate not supported for short frame

This figure shows a Logic Analyzer waveform of the sample output and latency of theDVB-S2 LDPC Decoder block for the default configuration when you specifyframeType as 0 (Normal frame),codeRateIdx as 5 (2/3 code rate), andParallelism level as 45. The latency of the block is 180,011 clock cycles.

DVB-S2 LDPC Decoder latency for default configuration scalar input

Vector Input

The latency of the block is equal to (r x _t_) +d + inputLen. In this calculation, r is the number of iterations,t is the number of clocks required to decode one iteration,d is the pipeline delays, and inputLen is the length of the input data.

The table shows the number of clocks the block requires to decode one iteration for normal and short frame types with different code rates and parallelism levels.

Code Rate Number of Clocks Per Iteration for Parallelism 45 Number of Clocks Per Iteration for Parallelism 180
Normal Short Normal Short
1/4 19,440 5,040 5,400 1,404
1/3 19,200 4,800 5,280 1,320
2/5 19,008 4,752 5,184 1,296
1/2 17,280 4,160 4,680 1,140
3/5 18,432 4,608 4,896 1,224
2/3 14,400 3,600 3,840 960
3/4 13,680 3,072 3,600 816
4/5 13,248 2,800 3,456 740
5/6 12,960 2,832 3,360 740
8/9 10,240 2,560 2,640 660
9/10 10,080 Code rate not supported for short frame 2,592 Code rate not supported for short frame

The table shows the number of pipeline delays for normal and short frame types with different code rates and parallelism levels.

Code Rate Number of Pipeline Delays for Parallelism 45 Number of Pipeline Delays for Parallelism 180
Normal Short Normal Short
1/4 1117 325 299 101
1/3 1478 398 270 90
2/5 901 253 245 83
1/2 757 338 209 80
3/5 613 181 173 65
2/3 758 218 150 60
3/4 397 3,072 119 63
4/5 325 158 101 50
5/6 398 123 90 51
8/9 278 98 70 40
9/10 181 Code rate not supported for short frame 65 Code rate not supported for short frame

This figure shows a Logic Analyzer waveform of the sample output and latency of theDVB-S2 LDPC Decoder block for the default configuration for an eight-element column vector when you specify frameType as0 (Normal frame), codeRateIdx as5 (2/3 code rate), and Parallelism level as45. The latency of the block is 37,657 clock cycles.

DVB-S2 LDPC Decoder Latency for Default Configuration for or an eight-element column vector

This section shows the EbNo and BER plots of the block for specified inputs and parameter settings.

This plot shows the performance of the block for a 4 bit QPSK-modulated LLR input of short and normal frames with code rates 1/2 and 3/4, respectively, when you set theAlgorithm parameter to Min-sum and theParallelism level parameter to 45.

DVB-S2 LDPC Decoder BER performance with Min-sum, Parallelism 45, QPSK

This plot shows the performance of the block for a 4 bit 16-APSK-modulated LLR input of short and normal frames with code rates 3/5 and 5/6, respectively, when you set theAlgorithm parameter to Min-sum and theParallelism level parameter to 45.

DVB-S2 LDPC Decoder BER performance with Min-sum, Parallelism 45, 16-APSK

This plot shows the performance of the block for a 4 bit QPSK-modulated LLR input of short and normal frames with code rates 1/2 and 3/4, respectively, when you set theAlgorithm parameter to Min-sum and theParallelism level parameter to 180.

DVB-S2 LDPC Decoder BER performance with Min-sum, Parallelism 180, QPSK

The performance of the synthesized HDL code varies with the target and synthesis options. It also varies based on the type of algorithm, input type, frame type source, code rate source, decoding termination criteria, parallelism, and word length of the input LLR values.

This table shows the resource and performance data synthesis results of the block for the supported DVB-S2 standard for scalar and vector inputs when you specify the input LLR values in fixdt(1,4,0) format and set the Algorithm parameter to Min-sum, the Number of iterations parameter to 8, Parallelism parameter to 45, and the FEC frame source parameter to Input port. The generated HDL is targeted to the AMD® Zynq® UltraScale+™ MPSoC - ZCU102 Evaluation Board.

Input Type Slice LUTs Slice Registers Block RAMs Maximum Frequency in MHz
Scalar 13386 8111 135 325.85
Vector 16901 12433 145 321.96

This table shows the resource and performance data synthesis results of the block for the supported DVB-S2 standard for scalar and vector inputs when you specify the input LLR values in fixdt(1,4,0) format and set the Algorithm parameter to Min-sum, the Number of iterations parameter to 8, Parallelism parameter to 180, and the FEC frame source parameter to Input port. The generated HDL is targeted to the AMD Zynq UltraScale+ MPSoC - ZCU102 Evaluation Board.

Input Type Slice LUTs Slice Registers Block RAMs Maximum Frequency in MHz
Scalar 44411 31150 225 286.47
Vector 48392 35664 225 287.71

References

[1] ETSI Standard EN 302 307 V1.4.1: Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), European Telecommunications Standards Institute, Valbonne, France, 2005-03.

[2] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. https://doi.org/10.1109/TIT.1962.1057683.

[3] Hocevar, D.E. “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes.” In IEEE Workshop On Signal Processing Systems, 2004. SIPS 2004, 107–12. Austin, Texas, USA: IEEE, 2004. https://doi.org/10.1109/SIPS.2004.1363033.

[4] Chen, Jinghu, R.M. Tanner, C. Jones, and Yan Li. "Improved Min-Sum Decoding Algorithms for Irregular LDPC Codes." In_Proceedings. International Symposium on Information Theory, 2005. ISIT 2005_. https://doi: 10.1109/ISIT.2005.1523374.

Extended Capabilities

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This block supports C/C++ code generation for Simulink® accelerator and rapid accelerator modes and for DPI component generation.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline (HDL Coder).
OutputPipeline Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2022a

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The DVB-S2 LDPC Decoder block now supports column vector as input.

The DVB-S2 LDPC Decoder block now supports specifying the scaling factor through an input port and the parallelism level for the block for faster decoding.