Sample Control Bus Selector - Select signals from the control signal bus used with Wireless HDL Toolbox blocks - Simulink (original) (raw)

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Select signals from the control signal bus used with Wireless HDL Toolbox blocks

Libraries:
Wireless HDL Toolbox / Utilities

Description

The Sample Control Bus Selector block selects signals from thesamplecontrol bus. This bus is used for modeling streaming control signals in communication systems for hardware. See Sample Control Bus.

The block is an implementation of the Simulink® Bus Selector block. See Bus Selector for more information.

Ports

Input

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Control signals accompanying the sample stream, specified as asamplecontrol bus. The bus includes the start,end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the input frame
end — Indicates the end of the input frame
valid — Indicates that the data on the inputdata port is valid

For more details, see Sample Control Bus.

Data Types: bus

Output

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Start of frame, returned as a Boolean scalar. This signal is 1 (true) for one time step, corresponding to the first valid sample of the frame.

Data Types: Boolean

End of frame, returned as a Boolean scalar. This signal is 1 (true) for one time step, corresponding to the last valid sample of the frame.

Data Types: Boolean

Validity of samples, returned as a Boolean scalar. This signal is 1 (true) on time steps that correspond to valid samples.

Data Types: Boolean

Extended Capabilities

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This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

To learn more about using buses for HDL code generation, see Buses (HDL Coder) and Use Buses to Improve Readability of Model and Generate HDL Code (HDL Coder).

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2017b