IEEE 1164 (original) (raw)

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dbo:abstract The IEEE 1164 standard (Multivalue Logic System for VHDL Model Interoperability) is a technical standard published by the IEEE in 1993. It describes the definitions of logic values to be used in electronic design automation, for the VHDL hardware description language. It was sponsored by the Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers (IEEE). The standardization effort was based on the donation of the Synopsys MVL-9 type declaration. The primary data type std_ulogic (standard unresolved logic) consists of nine character literals (see table on the right). This system promoted a useful set of logic values that typical CMOS logic designs could implement in the vast majority of modeling situations, including: * 'Z' literal to make tri-state buffer logic easy * 'H' and 'L' weak drives to permit wired-AND and wired-OR logic. * 'U' for default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary. In VHDL, the hardware designer makes the declarations visible via the following library and use statements: library IEEE;use IEEE.std_logic_1164.all; (en) IEEE 1164 표준은 VHDL 하드웨어 기술 방식에서 논리값의 단일 표현을 지원하는 선언을 포함하는 패키지 설계 단위를 정의한다. 전기 전자 기술자 협회(IEEE)의 의 후원을 받았다. 이 표준에 대한 표준화 노력은 시높시스 MVL-9 타입 선언의 기증에서 시작되었다. (ko)
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rdfs:comment IEEE 1164 표준은 VHDL 하드웨어 기술 방식에서 논리값의 단일 표현을 지원하는 선언을 포함하는 패키지 설계 단위를 정의한다. 전기 전자 기술자 협회(IEEE)의 의 후원을 받았다. 이 표준에 대한 표준화 노력은 시높시스 MVL-9 타입 선언의 기증에서 시작되었다. (ko) The IEEE 1164 standard (Multivalue Logic System for VHDL Model Interoperability) is a technical standard published by the IEEE in 1993. It describes the definitions of logic values to be used in electronic design automation, for the VHDL hardware description language. It was sponsored by the Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers (IEEE). The standardization effort was based on the donation of the Synopsys MVL-9 type declaration. In VHDL, the hardware designer makes the declarations visible via the following library and use statements: (en)
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