EECS 373: Design of Microprocessor-Based Systems (original) (raw)

Announcements

• 12/20/2011: Grades posted to Wolverine Access. Final gradedistribution.
• 12/16/2011: Project/Demo Session from 4:00-6:00 PM in EECS Atrium.
• 12/13/2011: Take home midterm due at 12:00 PM.
• 12/04/2011: Demo/Poster Session details:
  • Who: EECS 373 students, friends and family, and people in the halls
  • What: demo your project, present your results
  • When: Fri, Dec 16 from 4:00-6:00pm
  • Where: EECS Atrium
  • Why: Because we want to see it work. And it's 25% of your grade.
  • How: Prepare a demo. Cover 373 topics. Make a poster (templates:PowerPoint and Keynote) Practice your pitch.
• 12/04/2011: Midterm 2 details:
  • Take home exam
  • Handed out: 12/8 at 12:00pm
  • Due on: 12/13 at 12:00pm
• 11/20/2011: Support hours for remainder of the semester:
  Sunday Afternoon -- Lohit, Darren
  Sunday Evening -- Pat
  Monday Afternoon -- Matt
  Monday Evening -- Darren
  Wednesday Afternoon -- Matt
  Wednesday Evening -- Pat
  Thursday Evening -- Lohit
• 11/20/2011: Project Status Meetings
• 11/18/2011: Extra Credit Announced
• 11/05/2011: List of sponsored projects posted.
• 10/11/2011: Homework 2 (also a practice midterm) posted.
  Due at NOON on Wed October 19. Slide under my door (4773 CSE).
  Come to class on 10/13 with any questions.
• 10/11/2011: Oct 13 topic changed from wireless communications to review.
• 10/11/2011: Worked out assembly and toolchain examples:
  • Login to a CAEN Linux machine (e.g. ssh UNIQUENAME@loginlinux.engin.umich.edu)
  • Download: Makefile,example1.s,example2.c,example3.c,example3.s
  • Look in the Makefile to see how tools are used.
  • Type: make ex1 (and look at the new files created).
  • Type: make ex2
  • Type: make ex2sim (Runs your code in a simulator).
  • Type: make ex3
  • Type: make clean (Deletes all of the compiled files).
• 10/10/2011: Verilog simulation on CAEN:
  • Login to a CAEN Linux machine (e.g. ssh UNIQUENAME@loginlinux.engin.umich.edu)
  • Download: inv.v andinv_testbench.v
  • Type: verilog inv.v inv_testbench.v
  • You'll see the output from your simulation. Play around with more complicated examples.
• 10/10/2011: Verilog references:quickref,combinational logic,sequential logic,
  samples,examples,asic-world.com,Icarus,language reference.
• 09/15/2011: Homework (Project) 1 is posted. This roadmap might be helpful.
  • 9/22: Rev 1.3
  • Or, svn co svn+ssh://UNIQNAME/afs/umich.edu/p/p/ppannuto/Public/373F11 proj1
  • Part II Assignments
  • (temporary backup link to assignment list)
  • Static Analysis Results
• 09/06/2011: Welcome to EECS 373!

Course Administrivia

Course:
EECS 373, Fall 2011, 4 Units, CN:
Instructional Staff:
Prabal Dutta (Instructor)
Matt Smith (Lab Instructor)
Lohit Yerva (GSI)
Darren Ashton (IA)
Pat Pannuto (IA)
Homepage:
http://www.eecs.umich.edu/~prabal/teaching/eecs373-f11
Lab Bug Website:
Google Doc
Lecture:
1690 CSE, TuTh: 10:30 AM - 12:00 PM
Lab:
2334 EECS

Course Description

This class is focused on the principles and practices of modern embedded systems design. In class, we will focus on computer architecture beyond the CPU, fundamentals of the hardware/software interface, techniques for sensing and controlling the physical world, and a few other topics. In lab, we will focus on the ARM Cortex-M3, Actel FPGAs, and other supporting hardware, to learn how to design, build, and program embedded systems. Labs during the first half of the course will focus on essential topics. The second half of the course will focus on the design and implementation of non-trivial, open-ended project involving both hardware and software. The labs and project will require a substantial amount of time -- this is a lab-intensive class with a heavy workload.

Course Calendar

Syllabus (Tentative)

Prerequisites

The curricular prequisites for this class include EECS 270(Introduction to Logic Design), EECS 280 (Programming and Introductory Data Structures), and EECS 370 (Introduction to Computer Organization). Thecourse bulletin outlines the contents of these courses. In general, students are expected to have a firm grasp on combinational and sequential logic design, be familiar with assembly language programming (for some architecture), be proficient in C programming, and know theirway around the elements of a computer. In addition, success in this course will require substantial reading and hacking, and students will need a high degree of patience and determination.

Policies

Honor Code. The Engineering Honor Code applies to all assignments and exams.

Learn Concepts Together through Discussion. Verbal collaboration between members of different groups is permitted for the purpose of helping classmates to understand concepts essential to the labs or providing one another with insights into the best way to approach the in-lab assignments.

Do Your Own Work. Individual assignments (e.g., prelabs, homeworks, and exams) are to be performed on your own. Group assignments (e.g., labs, lab reports, and postlabs) are to be performed only by members of the group. Non-verbal collaboration (e.g. drawing sample schematics on paper or the whiteboard, sharing schematics or code) is not allowed. You may not help debug another group's hardware or software without consent from the lab or course instructor. You are also not allowed to possess, look at, use, or in any way derive advantage from the existence of code, lab reports, or other material prepared in prior years.

Attend Your Registered Lab. You are expected to attend the lab section for which you are registered. If you would like to switch lab sections, but the section you want is full, you must find someone in that lab section to swap positions with you. Once you have agreed on a swap, send email to Matt Smith. All section swaps must be completed before the second week of lab.

Prelabs. Prelabs are due in lab during the week the lab is to start. All prelabs must be turned in within the 20 minutes after the offical start of lab (on the half hour) (to allow for tardiness, printing problems, etc.) or you will only get 50% of the credit otherwise earned. Prelabs more than one week late will earn no credit. For any labs which span multiple weeks, the prelab is due during the first week of that lab. Prelabs are to be done individually unless otherwise specified in the lab itself.

Postlabs. Postlabs are due in lab the week after the last week of that lab. They are due 20 minutes after the start of that lab period. Just like prelabs, late labs earn only 50% of the credit otherwise earned and postlabs which are more than one week late get no credit. Postlabs are to be done by the group unless otherwise specified in the lab itself.

**In-Labs.**In-labs are due by Friday of the last week of the lab in open lab hours (you are welcome to turn it in before this and most students do). One of the lab instructors must sign your in-lab form by that time for the in-lab to be on time. You should hand in the signed (and dated) in-lab form with your postlab. Late in-labs lose 10% of their value per business day (Monday though Friday not including holidays) they are late. You may only work with your lab group (generally one other person) on your in-lab.

Grading

Resources

1. ARMv7 Architecture Reference Manual
2. ARM Cortex-M3 Technical Reference Manual v2.1
3. ARM and Thumb-2 Instruction Set Quick Reference Card
4. ARM Architecture Procedure Call Standard (EABI)
5. ARM Cortex-M3 Embedded Software Development (AN-179)
6. Actel SmartFusion MSS User Guide
7. Actel SmartFusion Analog User Guide
8. Actel A2F Eval Kit User Guide
9. CodeSourcery Getting Started
10. GNU Assembler
11. GNU Compiler
12. GNU Linker
13. Linkers and Loaders
14. GNU Debugger
15. GNU Binary Utilities

Support