Topics tagged amdgpu (original) (raw)

Topic Replies Views Activity
[RFC] Add CallBr Intrinsic Support IR & Optimizations rfc , amdgpu 5 186 May 6, 2025
GreedyRegAlloc unnecessary stack reloads Code Generation regalloc , arm64 , amdgpu 0 54 April 23, 2025
RFC: llvm.gpu builtins for target agnostic code representation IR & Optimizations nvptx , amdgpu , clang , libc , spirv 0 59 March 13, 2025
[RFC] Desugar variadics. Codegen for new targets, optimisation for existing IR & Optimizations gpu , amdgpu , libc 6 822 July 19, 2024
some dialects in AMGGPU dialects are equal to ROCDL dialects , Is it redundant? AMDGPU amdgpu , llvm , mlir 1 132 June 20, 2024
Assembling and linking AMD GPU kernel code Beginners hip , gpu , amdgpu 21 442 May 16, 2024
[RFC] MMRAs - Memory Model Relaxation Annotations IR & Optimizations core , gpu , amdgpu , llvm , llvm-ir 16 878 May 14, 2024
Loop unroller fails to unroll loop Loop Optimizations amdgpu , llvm 6 726 April 23, 2024
Confused by inconsistencies in GPU magic constants MLIR gpu , amdgpu 19 699 September 18, 2023
InferAddrSpace] The operand with non-FLAT-address-space got Undefined when rewriting its user to new address space IR & Optimizations amdgpu , llvm 28 538 September 4, 2023
The value of a constant global variable is random after linking for AMDGPU LLD gpu , amdgpu 0 204 July 18, 2023
[RFC] Cleaning up the NVIDIA (and potentially AMD) GPU backend Code Generation gpu , nvptx , amdgpu 5 537 June 29, 2023
Catching up on uniformity analysis AMDGPU amdgpu , llvm 5 465 February 13, 2023
Convert NVIDIA GPU LLVM IR(NVVM) alloca instruction to AMDGPU's AMDGPU gpu , amdgpu , llvm 7 1200 September 9, 2022
[TableGen/RegAlloc] How to use a fixed register in an instruction? Code Generation regalloc , gpu , amdgpu 5 743 August 16, 2022
[GISel/DAG] Getting a TableGen pattern to match both `G_ADD` and `G_PTR_ADD` in GISel Code Generation amdgpu 0 254 August 12, 2022
Feedback on new flag for AMDGPU Clang Frontend amdgpu 4 382 February 22, 2022