| How to force two virtual register allocate to the same physical register in LLVM? Code Generation regalloc , llvm |
|
1 |
54 |
December 8, 2025 |
| Is LLVM custom Register Allocation able to only spilling virtual register to memory Beginners regalloc |
|
2 |
110 |
April 25, 2025 |
| GreedyRegAlloc unnecessary stack reloads Code Generation regalloc , arm64 , amdgpu |
|
0 |
81 |
April 23, 2025 |
| How to verify correct regalloc for a kernel? AMDGPU regalloc |
|
5 |
251 |
August 24, 2024 |
| Register Allocation and Calling Conventions Beginners regalloc |
|
0 |
93 |
July 13, 2024 |
| Why is there spiillage in this program even after using register allocator? Code Generation regalloc , clang , llvm |
|
3 |
88 |
July 9, 2024 |
| Allocating different live ranges to same physicals LLVM Project regalloc |
|
3 |
179 |
April 26, 2024 |
| Rematerialized virtual register ran out of registers during register allocation RISCV regalloc |
|
1 |
233 |
December 20, 2023 |
| On semantics of Reserved keyword for subregisters Code Generation regalloc |
|
5 |
193 |
August 25, 2023 |
| "isolated" live interval segment with no defs in the predecessors: should the verifier have caught it? Code Generation regalloc , llvm |
|
3 |
242 |
May 5, 2023 |
| Question about register spilling, rematerialization, and racy accesses Code Generation regalloc , llvm |
|
3 |
627 |
February 10, 2023 |
| Pass to tie an output operand to a subregister of an input operand Common CodeGen Infrastructure regalloc |
|
2 |
546 |
December 13, 2022 |
| [TableGen/RegAlloc] How to use a fixed register in an instruction? Code Generation regalloc , gpu , amdgpu |
|
5 |
777 |
August 16, 2022 |
| Are you using -mllvm -consider-local-interval-cost? IR & Optimizations regalloc |
|
1 |
329 |
March 9, 2022 |