Andriy Hikavyy - Academia.edu (original) (raw)

Papers by Andriy Hikavyy

ECS Journal of Solid State Science and Technology, 2021

We describe challenges of the epitaxial Si-cap/Si0.75Ge0.25//Si-substrate growth process, in view... more We describe challenges of the epitaxial Si-cap/Si0.75Ge0.25//Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-growth on top of strained Si0.75Ge0.25, even for thinner Si0.75Ge0.25 layers and when growing the Si-cap layer at a lower temperature. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap/Si0.75Ge0.25//Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer-to-wafer bonding and Si-...

2019 IEEE International Electron Devices Meeting (IEDM), 2019

We report on p and n-type vertical gate-all-around (GAA) nanowire (NW) and nanosheet (NS) FETs wh... more We report on p and n-type vertical gate-all-around (GAA) nanowire (NW) and nanosheet (NS) FETs which offer attractive opportunities for ultra-scaled circuits. An in-depth evaluation is presented on the impact of doping and key device dimensions to improve the performance, variability, noise and reliability behavior for junctionless (JL) vs. inversion-mode (IM) vertical FETs built with an RMG scheme. The latter enables a novel concept to introduce stress in VFETs for enhanced mobility with up to a19% higher ION predicted. SiGe/Si pillars and self-aligned spacers offer a solution to gate vertical (mis)alignment towards the S/D. As MRAM selector, VNS FETs can allow substantial area reduction (64% for 2VNS per cell; 3nm node design rules) vs. finFET based cells, with smaller read/write energy consumption and latency times.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to... more As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

ECS Meeting Abstracts, 2008

not Available.

ECS Meeting Abstracts, 2012

ECS Transactions, 2019

Questa tesi, condotta nei laboratori di Imec in Belgio, rappresenta l'ultimo passo del mio percor... more Questa tesi, condotta nei laboratori di Imec in Belgio, rappresenta l'ultimo passo del mio percorso universitario. Voglio esprimere la mia gratitudine al mio supervisor Dr. Erik Rosseel, per la grande pazienza avuta nel guidarmi attraverso complessi ed entusiasmanti concetti e per la fiducia riposta in me, sicuramente più di quanto mi aspettassi. Ringrazio, inoltre, il Dr. Clement Porret e Anurag Vohra per il tempo passato a colmare le mie lacune, ben oltre gli orari di lavoro, ma soprattutto per i tanti momenti passati insieme che hanno reso la mia permanenza in Belgio, non solo un periodo di grande apprendimento, ma anche di spensieratezza. Sono grato al Dr. Roger Loo e al Dr. Andriy Hikavyy per i preziosi consigli ricevuti durante i meeting, che hanno contribuito a rendere il mio lavoro più solido. In questi mesi ho potuto beneficiare della vastissima conoscenza del Dr. Eddy Simoen, della gentilezza e della disponibilità di Dirk Rondas, Johnny Steenberg e Brigitte Parmentier. A Yan Hua Huang, a tutti i meravigliosi membri dell'epi team e al manager Dr. Robert Langer va un sentito ringraziamento. Ma soprattutto, in questo percorso non posso dimenticare il ruolo fondamentale della mia famiglia, per gli immensi sacrifici sostenuti e per non avermi mai fatto mancare supporto e affetto, nonostante la distanza gli abbia impedito di essere appieno partecipi di questo percorso. Un amore incondizionato, dal valore inestimabile e senza tempo. Ringrazio inoltre tutti coloro che mi sono stati accanto, contribuendo alla mia crescita personale e per aver aver reso questi anni uno splendido ricordo al quale riserverò sempre un posto speciale.

Semiconductor Science and Technology, 2019

Vertically stacked gate-all-around nanowires (GAA NWs) are considered a promising architecture fo... more Vertically stacked gate-all-around nanowires (GAA NWs) are considered a promising architecture for ultimately scaled complementary metal oxide semiconductor devices. These are the natural evolution of the fin-shaped field effect transistor (finFET) design and enable a better electrostatic control and a higher drive current per footprint w.r.t. previous architectures. Transmission electron microscopy (TEM) analysis is employed in the development stages of these devices to investigate morphology, material diffusion, oxidation and strain in order to achieve the desired nanowires shape and size and the required performances. Nano beam diffraction and geometric phase analysis of high-resolution scanning TEM (STEM) images are used in this work to evaluate strain at the nmscale along the nanowires at different steps of the fabrication process. Initially strained Ge layers, in the early stages of the GAA NWs fabrication, relax after the fin-reveal and source/drain etching process steps. Strain is then restored after source/drain epitaxial deposition and maintained till the NWs release. TEM analyses of these structures are particularly challenging due to the dimensions of the GAA NWs which are smaller than the thickness of a typical TEM specimen. This generates artifacts due to different materials and multiple structures overlapping in projection in TEM images. To avoid these issues, several TEM lamellae at different positions in the device and/or 3D imaging STEM/energy dispersive spectroscopy tomography are employed.

ECS Journal of Solid State Science and Technology, 2019

Japanese Journal of Applied Physics, 2019

We report on production compatible low temperature (⩽320°C) selective epitaxial growth schemes fo... more We report on production compatible low temperature (⩽320°C) selective epitaxial growth schemes for boron doped Ge 0.99 Sn 0.01 and Ge in source/ drain areas of FinFET and gate-all-around (GAA) strained-Ge pMOS transistors. Active B concentrations are as high as 3.2 × 10 20 cm −3 and 2.2 × 10 20 cm −3 for Ge 0.99 Sn 0.01 and Ge, respectively. The Ge:B growth is based on a cyclic deposition and etch approach using Cl 2 as an etchant, while the Ge 0.99 Sn 0.01 :B growth is selective in nature. Low Ti/p+ Ge(Sn):B contact resistivities of 3.6 × 10 −9 Ω cm 2 (Ge 0.99 Sn 0.01) and 5.5 × 10 −9 Ω cm 2 (Ge:B) have been obtained without any post-epi activation anneal. This work is the first demonstration of a selective, conformally doped Ge 1−x Sn x :B source/drain epi implemented on Ge FinFET device structure with fin widths down to 10 nm and on GAA devices (horizontal compressively strained-Ge nanowires).

ECS Transactions, 2016

As contact resistance becomes a bottle-neck in scaled CMOS devices, there is a need for source/dr... more As contact resistance becomes a bottle-neck in scaled CMOS devices, there is a need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers for the Source/Drain formation in Si bulk FinFETs. We report on the macroscopic and microscopic properties of the Si:P layers and discuss the details of the microstructure and the manifestation of Phosphorus-Vacancy complexes at high Phosphorus concentrations. We analyze how a post-epi thermal budget like spike or laser annealing modifies the microstructure and leads to an enhanced P activation and diffusion. We also zoom in on some of the integration aspects of the Si:P layers and discuss the benefit of the high-P concentration for the contact resistivity and the final device performance.

ECS Journal of Solid State Science and Technology, 2017

This paper reports on a Deep-Level Transient Spectroscopy (DLTS) study of the electrically active... more This paper reports on a Deep-Level Transient Spectroscopy (DLTS) study of the electrically active defects in ∼100 nm Si:C stressors, formed by chemical vapor deposition on p-type Czochralski silicon substrates. In addition, the impact of a post-deposition Rapid Thermal Annealing (RTA) at 850 • C on the DLT-spectra is investigated. It is shown that close to the surface at least two types of hole traps are present: one kind exhibiting slow hole capture, which may have a partial extended defect nature and a second type of hole trap behaving like a point defect. RTA increases the concentration of both hole traps and, in addition, introduces a point defect at E V + 0.35 eV in the depletion region of the silicon substrate at some distance from the Si:C epi layer. This level most likely corresponds with C i O i-related centers. Finally, a negative feature is found systematically for larger reverse bias pulses, which could point to a response of trap states at the Si:C/silicon hetero-interface.

2016 IEEE Symposium on VLSI Technology, 2016

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked hori... more We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

2016 China Semiconductor Technology International Conference (CSTIC), 2016

Electrically active defects in silicon-based epitaxial layers on silicon substrates have been stu... more Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects have been investigated, like, the impact of the pre-epi cleaning conditions and the effect of a post-deposition anneal on the deep-level properties. It is shown that the pre-cleaning thermal budget has a strong influence on the defects at the substrate/epi layer interface. At the same time, a post-deposition Forming Gas Anneal can passivate to a large extent the active defect states. Finally, it is shown that application of a post-deposition anneal increases the out-diffusion of carbon from a Si:C stressor layer into the p-type CZ substrate.

2015 Symposium on VLSI Technology (VLSI Technology), 2015

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high de... more Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

ECS Transactions, 2012

Novel device architectures offer improved scalability but come often at the price of increased la... more Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiv...

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant... more An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CETINV-normalized GM,SAT,INT of 6.7 nm.mS/μm, the Si0.3Ge0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

Journal of Applied Physics, 2014

Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hamp... more Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hampering the reliability of performance predictions of tunneling devices based on these materials. The nonlocal band-to-band tunneling model for compressively strained SiGe is calibrated based on a comparison of strained SiGe p-i-n tunneling diode measurements and doping-profile-based diode simulations. Dopant and Ge profiles of the diodes are determined by secondary ion mass spectrometry and capacitance-voltage measurements. Theoretical parameters of the band-to-band tunneling model are calculated based on strain-dependent properties such as bandgap, phonon energy, deformation-potential-based electron-phonon coupling, and hole effective masses of strained SiGe. The latter is determined with a 6-band k·p model. The calibration indicates an underestimation of the theoretical electron-phonon coupling with nearly an order of magnitude. Prospects of compressively strained SiGe tunneling transis...