Dr. Deva Nand - Academia.edu (original) (raw)

Papers by Dr. Deva Nand

2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

Journal of Circuits, Systems and Computers

This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTG... more This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode operation of existing DMTGDI design and DMPL design is identified and illustrated through mathematical formulation and simulations. To resolve this concern, the pre-charge/pre-discharge transistor in existing DMTGDI design is replaced by dual mode inverter in the proposal. The functional verification and performance comparison of NAND, NOR, XOR gates and 1-bit full adder based on proposed M-DMTGDI is carried out using 90 nm BSIM4 model card for bulk CMOS using Symica DE tool. The performance of the circuits is evaluated in terms of power, delay and Power Delay Product (PDP) in both static and dynamic modes. The variation of PDP with the ratio of the time the circuit is designed to run in dynamic mode against static mode is also investigated to analyze the energy efficiency of the M-DMTGDI design. The proposed approa...

2022 2nd International Conference on Intelligent Technologies (CONIT)

2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)

In today's world where data breaching and misuse of confidential data are so common, an end u... more In today's world where data breaching and misuse of confidential data are so common, an end user's utmost priority should be to keep one's data secure. This is where information security and cryptography comes into the picture and in this paper, a pipelined and pseudo randomized implementation of TDES encryption standard on FPGA using Verilog HDL is designed which can encrypt and decrypt a given user's messages with high throughput and the pseudo randomizer randomizes the key with the help of a Linear Feedback Shift Register which makes the encrypted output random thereby making it more secure than the traditional TDES systems. The target device used is xc7vx330t-3ffg1157 from Virtex-7 FPGA family offered by Xilinx on which a maximum frequency of 608.224 MHz and maximum throughput of 38.92 Gigabits per second was achieved. The proposed design is also faster when compared to previous works on their respective platforms. The proposed system was designed and analyzed thoroughly using the Xilinx ISE Design Suite v14.7.

2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT), 2021

This paper proposes Transmission Gate Diffusion Input (TGDI) based design using Carbon Nano tube ... more This paper proposes Transmission Gate Diffusion Input (TGDI) based design using Carbon Nano tube Field Effect Transistors (CNTFETs). The performance of proposed design is analyzed for 2-input gates, 2:1 multiplexer(MUX), 1-bit full adder and 2-bit Ripple Carry Adder (RCA) in terms of delay, power and Power Delay Product (PDP). Simulative investigation is done at 32nm using HSPICE tool and comparison of performance of the proposed with GDI based CNTFET counterparts. Analysis of result shows that TGDI based CNTFET circuits offer benefits of less power and delay resulting in reduction of overall PDP in comparison with GDI based CNTFET circuits. A maximum PDP reduction of 77.23% and 81.92% for 2-input gates and multiplexer is achieved using the proposed approach respectively as compared to their GDI counterparts. Corresponding values are 67.79% and 21.35% for a 1-bit full adder and 2-bit RCA circuit respectively.

2021 7th International Conference on Signal Processing and Communication (ICSC), 2021

This article presents the new realization of capacitance multiplier based on current follower dif... more This article presents the new realization of capacitance multiplier based on current follower differential input transconductance amplifier (CFDITA). Capacitance multiplier has been realized by one active block CFDITA, three resistors and one capacitor. Multiplication factor of the realized capacitance multiplier can be controlled by using external resistors as well as by bias current of CFDITA. Ideal & non-ideal analyses have been carried out for the implemented circuit. PSPICE software is used for designing & simulation of circuit in 0.18μm CMOS technology. To power the circuit, ±1.25 V is used. The simulation results are found in accordance with theoretical aspects.

2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 2020

This paper proposes a voltage-mode second-order multifunction filter that uses a voltage differen... more This paper proposes a voltage-mode second-order multifunction filter that uses a voltage differencing differential difference amplifier (VDDDA) as an active building block. The proposed filter is sort of MISO multifunction filter having three input nodes and single output node. It comprises of one VDDDA, one resistor and two identical capacitors. In this proposal, the filter offers low-pass (LP), high-pass (HP), band-stop (BS), bandpass (BP), and all-pass (AP) responses for the same circuit configuration by selecting the appropriate input signals. The quality factor and natural frequency both can be electronically controllable and tunable with a dc bias current. Theoretical results have been conformed in SYMICA DE simulations using 0.18mum0.18\mu m0.18mum TSMCS CNOIS CMOS process parameters with supply voltages of pm0.9V\pm 0.9Vpm0.9V.

Ballistic transport based graphene field effect transistor (GFET) is the emerging nanoelectronics... more Ballistic transport based graphene field effect transistor (GFET) is the emerging nanoelectronics device technology, which is promising to add a new dimension to electronic devices and to replace conventional silicon technology, especially for radio frequency applications. In this paper, the radio (GHz) frequency static linearity and nonlinearity performance potential are analyzed for the ballistic approach GFET under the ballistic transport regime. This work explores the static linearity of graphene FET mathematically under the quasi-ballistic transport regime along with the scaling outlook of the GFETs at four different channel lengths. The proposed model explores close mathematical expressions for Harmonic distortion, intermodulation distortion, and interception points and also depicted them in graphical form. The second and third order harmonics and intermodulation distortions are analyzed with help of mathematical analysis of drain current equation formulated using Mckelvey’s f...

MatSciRN: Process & Device Modeling (Topic), 2018

This paper puts forward an all new electronically tunable filter namely “Shadow Filter” which is ... more This paper puts forward an all new electronically tunable filter namely “Shadow Filter” which is not only capable of achieving a constant bandwidth, but also capable of features such as variable center frequencyconstant bandwidth filter. This is achieved by using operational floating current conveyor (OFCC) based Trans Admittance mode (TAM) as well as Trans Impedance mode (TIM) with a Trans Admittance Amplifier (TAM) amplifier in a feedback path. The proposed configuration allows adjustment of filter parameters such as the 3dB frequency and the Q-factor of the filter through gain of the used amplifier which in turn is controlled only by only one grounded passive element. The obtained filter is low pass-controlled band pass filter (LP_BP). To facilitate electronic tuning of the filter parameters, MOS-based implementation of grounded resistors is used. The operation of the proposed filters is verified through SPICE simulations using 0.5μm technology model parameters from MOSIS (AGILENT).

2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020

Since the days when they were only a small bunch of logic gates that could design any Boolean Fun... more Since the days when they were only a small bunch of logic gates that could design any Boolean Function, Field Programmable Gated Array (FPGA) have come a long way and evolved into many complex chips. The FPGAs have now become a very essential part of the semiconductor and Very Large Scale Integration industry. This paper presents a memory design, based on FPGA which can locate the address required by CPU almost instantly. This memory design works efficiently in Memory intensive jobs also. In this paper, the same hardware architecture has been designed and synthesized with different memory sizes and then they are compared by analyzing the number of lookup tables (LUTs) they use, their on-chip power and the delays associated with them.

2018 5th International Conference on Signal Processing and Integrated Networks (SPIN), 2018

A digitally controlled operational floating current conveyor (OFCC) based filter for hearing aid ... more A digitally controlled operational floating current conveyor (OFCC) based filter for hearing aid is presented. The proposed circuit uses a trans conductance amplifier and band pass biquadratic filter for selection of a particular frequency band with the help of capacitor array for auditory impairment. The circuit uses only three OFFCs and MOS based grounded resistors which reduces power consumption significantly. Extensive simulations are carried out using SPICE to validate theoretical predictions and found in close agreement.

IOP Conference Series: Materials Science and Engineering, 2021

In the present proposal current-mode (CM) full-wave rectifiers (FWR) using a differential-differe... more In the present proposal current-mode (CM) full-wave rectifiers (FWR) using a differential-difference current conveyor (DDCC) block, two MOS-based diodes and three grounded resistors. Two proposals of rectifiers are presented, the first is CM FW positive rectifier and the second is CM FW negative rectifier. The value 200MHz was observed in the operating frequency of the simulated designs. The SPICE simulations with 180 nm TSMC CMOS technology model file has been used to ensure the proper functioning of both of the proposals.

A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene f... more A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene field effect transistors (GFETs) with large area graphene is presented in which the quantum mechanical density gradient method is utilised. The basic device physics of the two-dimensional (2D) graphene channel is studied analytically. This modeling leads to the precise drain current calculation of the GFETs. The drain current calculation for GFETs starts from charge carrier concentration, its density of states and quantum capacitance(QC). QC depends on the channel voltage as a function of gate to source voltage Vgs and drain to source voltage Vds primarily. The formulation of the drain current with velocity saturation has been done by the Monte Carlo simulation method. The performance of the analytical GFETs model is present the precise values of QC, its impact on drain current and transfer as well as output characteristics. The impact of QC at nanometer technology adds the nonlinearity t...

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), 2021

This contribution proposes a technique for leakage power reduction in footed domino circuits by i... more This contribution proposes a technique for leakage power reduction in footed domino circuits by incorporating Leakage Control NMOS Transistor (LCNT) technique along with a footed diode inverter. The analysis is done using footed domino gates for two, four and eight input OR gates to investigate the proposed techniques at 90nm, 45nm and 32nm technology nodes in both precharge and evaluation phase using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. The total leakage power saving is (23.7%-71.8%) in precharge phase and (22.6%-77.1%) in evaluation phase using the proposed approach. The efficiency of the proposed approach increases with scaling of technology i.e., the leakage power saving achieved by the proposed approach improves at lower technology node.

2021 Asian Conference on Innovation in Technology (ASIANCON), 2021

Presently there has been an increased demand for energy as conventional sources of energy is goin... more Presently there has been an increased demand for energy as conventional sources of energy is going to reduce rapidly. It leads to create a high demand for energy sources and everybody knows that these sources are limited in the environment. So here require to think about other sources of energy and need to go with it while keeping in mind, that it should not affect human life. Various sources of energy conservation methods produce noise, air and water pollution, etc. The implementation of this also to be cost-effective. In this scope, piezoelectric discs become good for energy harvesting and storage for future applications. It takes advantage of the energy generated when people walking on it. This converts it into electric energy which used in an electronic gadget that requires power. This research paper is based on a new approach to solving the above problems by introducing here an Internet of things based energy harvesting system using piezoelectric discs. Which are capable to drive energy to electronic devices from stored energy in the battery. This setup is just not only harvested the energy although anyone can see the energy-saving related parameters voltage, current, battery level. It is also able to handle functions like mobile charging station application with the help of an Internet of thing based android application remotely in contrast with smart cities. Designing and implementing work is done for a real-time prototype system and tested for energy harvesting.

Journal of Computational Electronics, 2021

2021 2nd International Conference for Emerging Technology (INCET), 2021

In this paper, a new Dadda Multiplier is designed using 4:2 compressors and parallel prefix adder... more In this paper, a new Dadda Multiplier is designed using 4:2 compressors and parallel prefix adders. From study and analysis in the literature reported in the recent past it is well known that a significant functional component in any processing module is a multiplier. In the processor, the multiplier takes up the majority of the hardware consumed as compared to any other arithmetic operations. Among the existing multiplication methods, Dadda multiplication method is advantageous in terms of reduction in delay.The main aim of a quality multiplier is to be as fast and consume as low area as possible. To decrease the delay of Dadda multiplier we have employed 4:2 compressor in the reduction stage. In the proposed system, parallel prefix adders are used to add the final stage of the partial product. In this paper, 4 Dadda multipliers employing 4:2 compressor block are proposed using Sklansky adder (SA), Kogge-Stone adder (KSA), Brent-Kung adder (BKA), and Ladner-Fischer adder (LFA). The proposed multiplier designs and conventional design are simulated on Xilinx Vivado 201S.2. The proposed designs are analyzed concerning conventional multiplier structure in terms of parameters delay (ns) and area (No. of LUTs).

Microprocessors and Microsystems, 2021

Abstract This contribution proposes a technique for leakage power reduction in Dual Mode Logic (D... more Abstract This contribution proposes a technique for leakage power reduction in Dual Mode Logic (DML) circuits by incorporating Gated Leakage Transistor (GLT). The resulting circuits are named as GALEOR with Dual Mode Logic (GDML). Further, GDML design is extended by including a footed diode transistor, the design so obtained is referred to as GALEOR with Dual Mode Logic with footed diode (GDMLD). The analysis is done using footed type A and type B DML gates, resulting in GDML and GDMLD variants referred to as GDML-TA, GDML-TB, GDMLD-TA and GDMLD-TB. Two input NAND and NOR gates along with a full adder and a 2-bit multiplier circuit are used to investigate the proposed techniques at 90 nm and 45 nm technology nodes in both static and dynamic mode using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. Average leakage power saving is 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD in static mode. Similarly, in pre-charge phase of dynamic mode, this value varies from 5.47%-28.22% for GDML and 14.55%-77.51% for GDMLD. For evaluation phase, average leakage power saving of 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD is achieved. Analysis of delay reveals that both the techniques increase delay of the design while providing significant leakage power saving.

IOP Conference Series: Materials Science and Engineering, 2021

Two voltage mode digital modulators have been proposed i.e. Binary Amplitude Shift Keying (BASK) ... more Two voltage mode digital modulators have been proposed i.e. Binary Amplitude Shift Keying (BASK) modulator and Binary Phase Shift Keying (BPSK) modulator. Both circuits use Dual-X Second Generation Current Conveyor (DXCCII) as the active building block and have the advantages of proper input impedances and use of grounded resistor. Detailed mathematical analysis of both circuits are given. The circuits have been simulated with SPICE using 0.35µm CMOS technology parameters. The supply voltage of ±1.8 V is used. Much satisfactory results have been obtained with the proposed circuits.

International Journal of Electrical and Computer Engineering (IJECE), 2017

This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on opera... more This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.

2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

Journal of Circuits, Systems and Computers

This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTG... more This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode operation of existing DMTGDI design and DMPL design is identified and illustrated through mathematical formulation and simulations. To resolve this concern, the pre-charge/pre-discharge transistor in existing DMTGDI design is replaced by dual mode inverter in the proposal. The functional verification and performance comparison of NAND, NOR, XOR gates and 1-bit full adder based on proposed M-DMTGDI is carried out using 90 nm BSIM4 model card for bulk CMOS using Symica DE tool. The performance of the circuits is evaluated in terms of power, delay and Power Delay Product (PDP) in both static and dynamic modes. The variation of PDP with the ratio of the time the circuit is designed to run in dynamic mode against static mode is also investigated to analyze the energy efficiency of the M-DMTGDI design. The proposed approa...

2022 2nd International Conference on Intelligent Technologies (CONIT)

2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)

In today's world where data breaching and misuse of confidential data are so common, an end u... more In today's world where data breaching and misuse of confidential data are so common, an end user's utmost priority should be to keep one's data secure. This is where information security and cryptography comes into the picture and in this paper, a pipelined and pseudo randomized implementation of TDES encryption standard on FPGA using Verilog HDL is designed which can encrypt and decrypt a given user's messages with high throughput and the pseudo randomizer randomizes the key with the help of a Linear Feedback Shift Register which makes the encrypted output random thereby making it more secure than the traditional TDES systems. The target device used is xc7vx330t-3ffg1157 from Virtex-7 FPGA family offered by Xilinx on which a maximum frequency of 608.224 MHz and maximum throughput of 38.92 Gigabits per second was achieved. The proposed design is also faster when compared to previous works on their respective platforms. The proposed system was designed and analyzed thoroughly using the Xilinx ISE Design Suite v14.7.

2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT), 2021

This paper proposes Transmission Gate Diffusion Input (TGDI) based design using Carbon Nano tube ... more This paper proposes Transmission Gate Diffusion Input (TGDI) based design using Carbon Nano tube Field Effect Transistors (CNTFETs). The performance of proposed design is analyzed for 2-input gates, 2:1 multiplexer(MUX), 1-bit full adder and 2-bit Ripple Carry Adder (RCA) in terms of delay, power and Power Delay Product (PDP). Simulative investigation is done at 32nm using HSPICE tool and comparison of performance of the proposed with GDI based CNTFET counterparts. Analysis of result shows that TGDI based CNTFET circuits offer benefits of less power and delay resulting in reduction of overall PDP in comparison with GDI based CNTFET circuits. A maximum PDP reduction of 77.23% and 81.92% for 2-input gates and multiplexer is achieved using the proposed approach respectively as compared to their GDI counterparts. Corresponding values are 67.79% and 21.35% for a 1-bit full adder and 2-bit RCA circuit respectively.

2021 7th International Conference on Signal Processing and Communication (ICSC), 2021

This article presents the new realization of capacitance multiplier based on current follower dif... more This article presents the new realization of capacitance multiplier based on current follower differential input transconductance amplifier (CFDITA). Capacitance multiplier has been realized by one active block CFDITA, three resistors and one capacitor. Multiplication factor of the realized capacitance multiplier can be controlled by using external resistors as well as by bias current of CFDITA. Ideal & non-ideal analyses have been carried out for the implemented circuit. PSPICE software is used for designing & simulation of circuit in 0.18μm CMOS technology. To power the circuit, ±1.25 V is used. The simulation results are found in accordance with theoretical aspects.

2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 2020

This paper proposes a voltage-mode second-order multifunction filter that uses a voltage differen... more This paper proposes a voltage-mode second-order multifunction filter that uses a voltage differencing differential difference amplifier (VDDDA) as an active building block. The proposed filter is sort of MISO multifunction filter having three input nodes and single output node. It comprises of one VDDDA, one resistor and two identical capacitors. In this proposal, the filter offers low-pass (LP), high-pass (HP), band-stop (BS), bandpass (BP), and all-pass (AP) responses for the same circuit configuration by selecting the appropriate input signals. The quality factor and natural frequency both can be electronically controllable and tunable with a dc bias current. Theoretical results have been conformed in SYMICA DE simulations using 0.18mum0.18\mu m0.18mum TSMCS CNOIS CMOS process parameters with supply voltages of pm0.9V\pm 0.9Vpm0.9V.

Ballistic transport based graphene field effect transistor (GFET) is the emerging nanoelectronics... more Ballistic transport based graphene field effect transistor (GFET) is the emerging nanoelectronics device technology, which is promising to add a new dimension to electronic devices and to replace conventional silicon technology, especially for radio frequency applications. In this paper, the radio (GHz) frequency static linearity and nonlinearity performance potential are analyzed for the ballistic approach GFET under the ballistic transport regime. This work explores the static linearity of graphene FET mathematically under the quasi-ballistic transport regime along with the scaling outlook of the GFETs at four different channel lengths. The proposed model explores close mathematical expressions for Harmonic distortion, intermodulation distortion, and interception points and also depicted them in graphical form. The second and third order harmonics and intermodulation distortions are analyzed with help of mathematical analysis of drain current equation formulated using Mckelvey’s f...

MatSciRN: Process & Device Modeling (Topic), 2018

This paper puts forward an all new electronically tunable filter namely “Shadow Filter” which is ... more This paper puts forward an all new electronically tunable filter namely “Shadow Filter” which is not only capable of achieving a constant bandwidth, but also capable of features such as variable center frequencyconstant bandwidth filter. This is achieved by using operational floating current conveyor (OFCC) based Trans Admittance mode (TAM) as well as Trans Impedance mode (TIM) with a Trans Admittance Amplifier (TAM) amplifier in a feedback path. The proposed configuration allows adjustment of filter parameters such as the 3dB frequency and the Q-factor of the filter through gain of the used amplifier which in turn is controlled only by only one grounded passive element. The obtained filter is low pass-controlled band pass filter (LP_BP). To facilitate electronic tuning of the filter parameters, MOS-based implementation of grounded resistors is used. The operation of the proposed filters is verified through SPICE simulations using 0.5μm technology model parameters from MOSIS (AGILENT).

2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020

Since the days when they were only a small bunch of logic gates that could design any Boolean Fun... more Since the days when they were only a small bunch of logic gates that could design any Boolean Function, Field Programmable Gated Array (FPGA) have come a long way and evolved into many complex chips. The FPGAs have now become a very essential part of the semiconductor and Very Large Scale Integration industry. This paper presents a memory design, based on FPGA which can locate the address required by CPU almost instantly. This memory design works efficiently in Memory intensive jobs also. In this paper, the same hardware architecture has been designed and synthesized with different memory sizes and then they are compared by analyzing the number of lookup tables (LUTs) they use, their on-chip power and the delays associated with them.

2018 5th International Conference on Signal Processing and Integrated Networks (SPIN), 2018

A digitally controlled operational floating current conveyor (OFCC) based filter for hearing aid ... more A digitally controlled operational floating current conveyor (OFCC) based filter for hearing aid is presented. The proposed circuit uses a trans conductance amplifier and band pass biquadratic filter for selection of a particular frequency band with the help of capacitor array for auditory impairment. The circuit uses only three OFFCs and MOS based grounded resistors which reduces power consumption significantly. Extensive simulations are carried out using SPICE to validate theoretical predictions and found in close agreement.

IOP Conference Series: Materials Science and Engineering, 2021

In the present proposal current-mode (CM) full-wave rectifiers (FWR) using a differential-differe... more In the present proposal current-mode (CM) full-wave rectifiers (FWR) using a differential-difference current conveyor (DDCC) block, two MOS-based diodes and three grounded resistors. Two proposals of rectifiers are presented, the first is CM FW positive rectifier and the second is CM FW negative rectifier. The value 200MHz was observed in the operating frequency of the simulated designs. The SPICE simulations with 180 nm TSMC CMOS technology model file has been used to ensure the proper functioning of both of the proposals.

A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene f... more A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene field effect transistors (GFETs) with large area graphene is presented in which the quantum mechanical density gradient method is utilised. The basic device physics of the two-dimensional (2D) graphene channel is studied analytically. This modeling leads to the precise drain current calculation of the GFETs. The drain current calculation for GFETs starts from charge carrier concentration, its density of states and quantum capacitance(QC). QC depends on the channel voltage as a function of gate to source voltage Vgs and drain to source voltage Vds primarily. The formulation of the drain current with velocity saturation has been done by the Monte Carlo simulation method. The performance of the analytical GFETs model is present the precise values of QC, its impact on drain current and transfer as well as output characteristics. The impact of QC at nanometer technology adds the nonlinearity t...

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), 2021

This contribution proposes a technique for leakage power reduction in footed domino circuits by i... more This contribution proposes a technique for leakage power reduction in footed domino circuits by incorporating Leakage Control NMOS Transistor (LCNT) technique along with a footed diode inverter. The analysis is done using footed domino gates for two, four and eight input OR gates to investigate the proposed techniques at 90nm, 45nm and 32nm technology nodes in both precharge and evaluation phase using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. The total leakage power saving is (23.7%-71.8%) in precharge phase and (22.6%-77.1%) in evaluation phase using the proposed approach. The efficiency of the proposed approach increases with scaling of technology i.e., the leakage power saving achieved by the proposed approach improves at lower technology node.

2021 Asian Conference on Innovation in Technology (ASIANCON), 2021

Presently there has been an increased demand for energy as conventional sources of energy is goin... more Presently there has been an increased demand for energy as conventional sources of energy is going to reduce rapidly. It leads to create a high demand for energy sources and everybody knows that these sources are limited in the environment. So here require to think about other sources of energy and need to go with it while keeping in mind, that it should not affect human life. Various sources of energy conservation methods produce noise, air and water pollution, etc. The implementation of this also to be cost-effective. In this scope, piezoelectric discs become good for energy harvesting and storage for future applications. It takes advantage of the energy generated when people walking on it. This converts it into electric energy which used in an electronic gadget that requires power. This research paper is based on a new approach to solving the above problems by introducing here an Internet of things based energy harvesting system using piezoelectric discs. Which are capable to drive energy to electronic devices from stored energy in the battery. This setup is just not only harvested the energy although anyone can see the energy-saving related parameters voltage, current, battery level. It is also able to handle functions like mobile charging station application with the help of an Internet of thing based android application remotely in contrast with smart cities. Designing and implementing work is done for a real-time prototype system and tested for energy harvesting.

Journal of Computational Electronics, 2021

2021 2nd International Conference for Emerging Technology (INCET), 2021

In this paper, a new Dadda Multiplier is designed using 4:2 compressors and parallel prefix adder... more In this paper, a new Dadda Multiplier is designed using 4:2 compressors and parallel prefix adders. From study and analysis in the literature reported in the recent past it is well known that a significant functional component in any processing module is a multiplier. In the processor, the multiplier takes up the majority of the hardware consumed as compared to any other arithmetic operations. Among the existing multiplication methods, Dadda multiplication method is advantageous in terms of reduction in delay.The main aim of a quality multiplier is to be as fast and consume as low area as possible. To decrease the delay of Dadda multiplier we have employed 4:2 compressor in the reduction stage. In the proposed system, parallel prefix adders are used to add the final stage of the partial product. In this paper, 4 Dadda multipliers employing 4:2 compressor block are proposed using Sklansky adder (SA), Kogge-Stone adder (KSA), Brent-Kung adder (BKA), and Ladner-Fischer adder (LFA). The proposed multiplier designs and conventional design are simulated on Xilinx Vivado 201S.2. The proposed designs are analyzed concerning conventional multiplier structure in terms of parameters delay (ns) and area (No. of LUTs).

Microprocessors and Microsystems, 2021

Abstract This contribution proposes a technique for leakage power reduction in Dual Mode Logic (D... more Abstract This contribution proposes a technique for leakage power reduction in Dual Mode Logic (DML) circuits by incorporating Gated Leakage Transistor (GLT). The resulting circuits are named as GALEOR with Dual Mode Logic (GDML). Further, GDML design is extended by including a footed diode transistor, the design so obtained is referred to as GALEOR with Dual Mode Logic with footed diode (GDMLD). The analysis is done using footed type A and type B DML gates, resulting in GDML and GDMLD variants referred to as GDML-TA, GDML-TB, GDMLD-TA and GDMLD-TB. Two input NAND and NOR gates along with a full adder and a 2-bit multiplier circuit are used to investigate the proposed techniques at 90 nm and 45 nm technology nodes in both static and dynamic mode using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. Average leakage power saving is 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD in static mode. Similarly, in pre-charge phase of dynamic mode, this value varies from 5.47%-28.22% for GDML and 14.55%-77.51% for GDMLD. For evaluation phase, average leakage power saving of 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD is achieved. Analysis of delay reveals that both the techniques increase delay of the design while providing significant leakage power saving.

IOP Conference Series: Materials Science and Engineering, 2021

Two voltage mode digital modulators have been proposed i.e. Binary Amplitude Shift Keying (BASK) ... more Two voltage mode digital modulators have been proposed i.e. Binary Amplitude Shift Keying (BASK) modulator and Binary Phase Shift Keying (BPSK) modulator. Both circuits use Dual-X Second Generation Current Conveyor (DXCCII) as the active building block and have the advantages of proper input impedances and use of grounded resistor. Detailed mathematical analysis of both circuits are given. The circuits have been simulated with SPICE using 0.35µm CMOS technology parameters. The supply voltage of ±1.8 V is used. Much satisfactory results have been obtained with the proposed circuits.

International Journal of Electrical and Computer Engineering (IJECE), 2017

This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on opera... more This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.