F. Guarin - Academia.edu (original) (raw)

Papers by F. Guarin

Research paper thumbnail of Reliability characteristics of 200 GHz f/sub T//285 GHz f/sub MAX/ SiGe HBTs

25th Annual Technical Digest 2003. IEEE Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003., 2003

Bookmarks Related papers MentionsView impact

Research paper thumbnail of 65NM Cmos Technology for Low Power Applications

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005

Fischer2, T. Pompl2, G. Massey, A. Vayshenker, WL Tan1, A. Ebert, W. Lin1, W. Gao1, J. Lian2, J.-... more Fischer2, T. Pompl2, G. Massey, A. Vayshenker, WL Tan1, A. Ebert, W. Lin1, W. Gao1, J. Lian2, J.-P. Kim3, P. Wrschka, J.-H. Yang3, A. Ajmera, R. Knoefler2, Y.-W. Teh1, F. Jamin, JE Park3, K. Hooper, C. Griffin, P. Nguyen, V. Klee2, V. Ku, C. Baiocco, G. Johnson, L. Tai, J. ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Experimental and simulation results of magnetic modulation of gate oxide tunneling current in nano-scaled MOS transistors

IEEE Electron Device Letters, 2015

ABSTRACT An experimental-simulation methodology to explore the spatially nonhomogeneous propertie... more ABSTRACT An experimental-simulation methodology to explore the spatially nonhomogeneous properties of the tunneling current in nanoscaled MOSFET is introduced. The magnetic field B is introduced into the Schrödinger-Poisson system, which allows simulating the effect of the B field on the gate oxide tunneling current and be compared with experimental data. We found out that sweeping the B field from negative to positive values is equivalent to scan or map the tunneling mechanism along the channel from source to drain. The proposed methodology is useful for studying nonhomogeneous space distributed conductive properties, and it was validated with a 28-nm n-type Si MOSFET.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Avalanche current induced hot carrier degradation in 200 GHz SiGe heterojunction bipolar transistors

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual., 2003

ABSTRACT SiGe heterojunction bipolar transistors (HBTs) have been investigated under accelerated ... more ABSTRACT SiGe heterojunction bipolar transistors (HBTs) have been investigated under accelerated avalanche stress conditions, where the base-emitter junction is forward biased, while the collector-base junction is reverse biased under avalanche conditions. The high energy avalanche carriers (hot carriers) introduce damage at Si-SiO2 interfaces and degrade the characteristics of the SiGe HBTs. A new model has been developed to predict the damage at the Si-SiO2 interface. The DC degradation of the base current is shown to correlate with the injected charge total and corresponding energy. The change of base current dependence on avalanche charges and applied voltage is shown, and a model is used to predict the parameter degradation within a typical digital switching application. The impact of this degradation mechanism to fT has also been studied and found not to be significant.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Hot carrier reliability of high-speed SiGe HBT’s under accelerated collector-base avalanche bias

2008 7th International Caribbean Conference on Devices, Circuits and Systems, 2008

ABSTRACT As SiGe heterojunction bipolar transistor (HBT) based technologies reach fT performance ... more ABSTRACT As SiGe heterojunction bipolar transistor (HBT) based technologies reach fT performance above 200 GHz the transistors are more likely to be operating in the avalanche region of collector-base junction. This avalanche effect imposes a reliability concern due to the damage induced by high-energy avalanche charges (hot carriers) on the Si-SiO2 interfaces. The impact of accelerated avalanche bias stress on 200 GHz SiGe HBTs was investigated and found to cause an increase in base current with no corresponding change of collector current. The increase of the base current correlates with the injected avalanche charge and its corresponding kinetic energy. A new empirical avalanche degradation model has been developed to predict the shifts in DC characteristics. Further studies showed that the SiGe HBT avalanche damage can be partially recovered by normal forward operation and/or high temperature anneal. The AC impact of this degradation mechanism has also been studied and found not to be significant. According to the reliability results of this study, the avalanche induced hot carrier degradation will not have a significant impact on the lifetime of the 200 GHz SiGe HBTs in a typical high speed digital circuit application.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Methodology for recovery of hot carrier induced degradation in bipolar devices

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Ring oscillator design for MOSFET device reliability investigations and its use for in-line monitoring

Bookmarks Related papers MentionsView impact

Research paper thumbnail of 32nm general purpose bulk CMOS technology for high performance applications at low voltage

2008 IEEE International Electron Devices Meeting, 2008

... Semiconductor , 4Chartered Semiconductor Manufacturing, 5Infineon Technologies AG, 6Samsung E... more ... Semiconductor , 4Chartered Semiconductor Manufacturing, 5Infineon Technologies AG, 6Samsung Electronics Co Ltd, 7Toshiba email: franck.arnaud@st.com ; phone : 1 ... Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

2014 IEEE International Electron Devices Meeting, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Non-homogeneous space mechanical strain induces asymmetrical magneto-tunneling conductance in MOSFETs

2014 44th European Solid State Device Research Conference (ESSDERC), 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Process dependence of AC/DC PBTI in HKMG n-MOSFETs

2014 IEEE International Reliability Physics Symposium, 2014

ABSTRACT It is well known that n-MOSFET aging under AC and DC Positive Bias Temperature Instabili... more ABSTRACT It is well known that n-MOSFET aging under AC and DC Positive Bias Temperature Instability (PBTI) is strongly dependent on the adopted HK stack processes. In this work it is reported, for the first time, a detailed analysis of the nature of the PBTI degradation and recovery under DC and AC conditions by a novel stress and test methodology. Our observations over two HK processes (A &amp; B) support the PBTI physical picture of two uncorrelated independent contributions to the PBTI damage. Namely, electron trap activation in pre-existing (before stress) process induced traps as well as electron traps generation in the HK bulk oxide. It is shown that the relative role of these two components to PBTI aging is strongly process dependent and fully explains the observed DC vs. AC PBTI process sensitivity. This finding challenges the generally expected dependence of AC/DC PBTI Vt shift ratio as function of AC pulse duty cycle. The root cause of such a striking AC and DC PBTI aging differences in these two processes and its implication to technology qualification are discussed in details.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Effect of I/O oxide process optimization on the nbti dependence of T<inf>inv</inf> scaling for a 20 nm bulk planar Replacement Gate process

2014 IEEE International Reliability Physics Symposium, 2014

ABSTRACT We present results on the beneficial effect of an additional thermal treatment on the NB... more ABSTRACT We present results on the beneficial effect of an additional thermal treatment on the NBTI aging of an I/O thick oxide process in 20nm Replacement Metal Gate (RMG) High-k Metal Gate (HKMG) technology. It is shown that for an as-grown thermal thick oxide gate process, the NBTI induced device threshold voltage shift (ΔVth) scales as Tinv-2 when stressed at a given gate voltage Vg. On the other hand, the ΔVth dependence on Vg is ΔVth ~ (Vg)4 for a given Tinv. These findings seem to be apparently inconsistent with well known power law NBTI dependence on Eox (~ (Vg/Tinv)). The expected NBTI dependence on Eox (ΔVth ~ (Vg/Tinv)4) is recovered when the as-grown thermal thick oxide is treated with an additional high temperature anneal. We have evaluated the NBTI induced ΔVth time evolution, its recovery behavior, temperature and voltage dependence under DC and AC bias stress conditions with and without the oxide thermal treatment. Our observations over the two gate stack processes (as-grown I/O oxide with and without anneal treatment) support the NBTI physical picture of two uncorrelated contributions to the NBTI damage. Namely, shallow hole trap activation in process induced pre-existing (before stress) traps as well as deep hole traps and/or interface states generation. The last component is quasi permanent and is dominant in both gate stack processes. In particular, for the as-grown I/O oxide the NBTI damage is mainly due to an increase contribution of the quasi permanent component with increasing Tinv. This unexpected Tinv dependence is reduced by the additional anneal treatment. The implication of these findings on the NBTI characterization and modeling will be discussed.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Magnetic field induced gate leakage current in 65nm nMOS transistors

2009 Proceedings of the European Solid State Device Research Conference, 2009

Bookmarks Related papers MentionsView impact

Research paper thumbnail of High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

IEEE International Reliability Physics Symposium Proceedings, 2010

... Semiconductor Research & Development Center, Hopewell Junction, NY 12533 We are grateful ... more ... Semiconductor Research & Development Center, Hopewell Junction, NY 12533 We are grateful for helpful discussions with Jordi Sune, Tanya Nigam, Ernest Wu, Eduard Cartier, Andreas Kerber. FR=0.01%,K=102 FR=0.1%,K=103 FR=1% FR=5% FR=10% IL HK IL+HK ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998

... M. Hargrove, S. Crowder, E. Nowak, R. Logan, LK Han, H. Ng, A. Ray, D. Sinitsky, P. Smeys, F.... more ... M. Hargrove, S. Crowder, E. Nowak, R. Logan, LK Han, H. Ng, A. Ray, D. Sinitsky, P. Smeys, F. Guarin, J. Oberschmidt, E. Crabbe, D ... In order to achieve optimal device performance, thin gate oxide, retrograde wells and strong halos coupled with shallow junctions are required. ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of SiGe HBT performance and reliability trends through f/sub T/ of 350 GHz

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual., 2003

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Device scaling and application trends for over 200GHz SiGe HBTs

2003 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003. Digest of Papers., 2003

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Wafer level reliability evaluation of 120GHz SiGe HBT's

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004., 2004

A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bip... more A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a wafer level reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz fT and 100 GHz fmax. Accelerated current stress as high as Jc=34

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Nanometer Scale Complementary Silicon MOSFETs as Detectors of Terahertz and Sub-terahertz Radiation

2007 IEEE Sensors, 2007

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Reliability characteristics of 200 GHz f/sub T//285 GHz f/sub MAX/ SiGe HBTs

25th Annual Technical Digest 2003. IEEE Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003., 2003

Bookmarks Related papers MentionsView impact

Research paper thumbnail of 65NM Cmos Technology for Low Power Applications

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005

Fischer2, T. Pompl2, G. Massey, A. Vayshenker, WL Tan1, A. Ebert, W. Lin1, W. Gao1, J. Lian2, J.-... more Fischer2, T. Pompl2, G. Massey, A. Vayshenker, WL Tan1, A. Ebert, W. Lin1, W. Gao1, J. Lian2, J.-P. Kim3, P. Wrschka, J.-H. Yang3, A. Ajmera, R. Knoefler2, Y.-W. Teh1, F. Jamin, JE Park3, K. Hooper, C. Griffin, P. Nguyen, V. Klee2, V. Ku, C. Baiocco, G. Johnson, L. Tai, J. ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Experimental and simulation results of magnetic modulation of gate oxide tunneling current in nano-scaled MOS transistors

IEEE Electron Device Letters, 2015

ABSTRACT An experimental-simulation methodology to explore the spatially nonhomogeneous propertie... more ABSTRACT An experimental-simulation methodology to explore the spatially nonhomogeneous properties of the tunneling current in nanoscaled MOSFET is introduced. The magnetic field B is introduced into the Schrödinger-Poisson system, which allows simulating the effect of the B field on the gate oxide tunneling current and be compared with experimental data. We found out that sweeping the B field from negative to positive values is equivalent to scan or map the tunneling mechanism along the channel from source to drain. The proposed methodology is useful for studying nonhomogeneous space distributed conductive properties, and it was validated with a 28-nm n-type Si MOSFET.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Avalanche current induced hot carrier degradation in 200 GHz SiGe heterojunction bipolar transistors

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual., 2003

ABSTRACT SiGe heterojunction bipolar transistors (HBTs) have been investigated under accelerated ... more ABSTRACT SiGe heterojunction bipolar transistors (HBTs) have been investigated under accelerated avalanche stress conditions, where the base-emitter junction is forward biased, while the collector-base junction is reverse biased under avalanche conditions. The high energy avalanche carriers (hot carriers) introduce damage at Si-SiO2 interfaces and degrade the characteristics of the SiGe HBTs. A new model has been developed to predict the damage at the Si-SiO2 interface. The DC degradation of the base current is shown to correlate with the injected charge total and corresponding energy. The change of base current dependence on avalanche charges and applied voltage is shown, and a model is used to predict the parameter degradation within a typical digital switching application. The impact of this degradation mechanism to fT has also been studied and found not to be significant.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Hot carrier reliability of high-speed SiGe HBT’s under accelerated collector-base avalanche bias

2008 7th International Caribbean Conference on Devices, Circuits and Systems, 2008

ABSTRACT As SiGe heterojunction bipolar transistor (HBT) based technologies reach fT performance ... more ABSTRACT As SiGe heterojunction bipolar transistor (HBT) based technologies reach fT performance above 200 GHz the transistors are more likely to be operating in the avalanche region of collector-base junction. This avalanche effect imposes a reliability concern due to the damage induced by high-energy avalanche charges (hot carriers) on the Si-SiO2 interfaces. The impact of accelerated avalanche bias stress on 200 GHz SiGe HBTs was investigated and found to cause an increase in base current with no corresponding change of collector current. The increase of the base current correlates with the injected avalanche charge and its corresponding kinetic energy. A new empirical avalanche degradation model has been developed to predict the shifts in DC characteristics. Further studies showed that the SiGe HBT avalanche damage can be partially recovered by normal forward operation and/or high temperature anneal. The AC impact of this degradation mechanism has also been studied and found not to be significant. According to the reliability results of this study, the avalanche induced hot carrier degradation will not have a significant impact on the lifetime of the 200 GHz SiGe HBTs in a typical high speed digital circuit application.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Methodology for recovery of hot carrier induced degradation in bipolar devices

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Ring oscillator design for MOSFET device reliability investigations and its use for in-line monitoring

Bookmarks Related papers MentionsView impact

Research paper thumbnail of 32nm general purpose bulk CMOS technology for high performance applications at low voltage

2008 IEEE International Electron Devices Meeting, 2008

... Semiconductor , 4Chartered Semiconductor Manufacturing, 5Infineon Technologies AG, 6Samsung E... more ... Semiconductor , 4Chartered Semiconductor Manufacturing, 5Infineon Technologies AG, 6Samsung Electronics Co Ltd, 7Toshiba email: franck.arnaud@st.com ; phone : 1 ... Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

2014 IEEE International Electron Devices Meeting, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Non-homogeneous space mechanical strain induces asymmetrical magneto-tunneling conductance in MOSFETs

2014 44th European Solid State Device Research Conference (ESSDERC), 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Process dependence of AC/DC PBTI in HKMG n-MOSFETs

2014 IEEE International Reliability Physics Symposium, 2014

ABSTRACT It is well known that n-MOSFET aging under AC and DC Positive Bias Temperature Instabili... more ABSTRACT It is well known that n-MOSFET aging under AC and DC Positive Bias Temperature Instability (PBTI) is strongly dependent on the adopted HK stack processes. In this work it is reported, for the first time, a detailed analysis of the nature of the PBTI degradation and recovery under DC and AC conditions by a novel stress and test methodology. Our observations over two HK processes (A &amp; B) support the PBTI physical picture of two uncorrelated independent contributions to the PBTI damage. Namely, electron trap activation in pre-existing (before stress) process induced traps as well as electron traps generation in the HK bulk oxide. It is shown that the relative role of these two components to PBTI aging is strongly process dependent and fully explains the observed DC vs. AC PBTI process sensitivity. This finding challenges the generally expected dependence of AC/DC PBTI Vt shift ratio as function of AC pulse duty cycle. The root cause of such a striking AC and DC PBTI aging differences in these two processes and its implication to technology qualification are discussed in details.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Effect of I/O oxide process optimization on the nbti dependence of T<inf>inv</inf> scaling for a 20 nm bulk planar Replacement Gate process

2014 IEEE International Reliability Physics Symposium, 2014

ABSTRACT We present results on the beneficial effect of an additional thermal treatment on the NB... more ABSTRACT We present results on the beneficial effect of an additional thermal treatment on the NBTI aging of an I/O thick oxide process in 20nm Replacement Metal Gate (RMG) High-k Metal Gate (HKMG) technology. It is shown that for an as-grown thermal thick oxide gate process, the NBTI induced device threshold voltage shift (ΔVth) scales as Tinv-2 when stressed at a given gate voltage Vg. On the other hand, the ΔVth dependence on Vg is ΔVth ~ (Vg)4 for a given Tinv. These findings seem to be apparently inconsistent with well known power law NBTI dependence on Eox (~ (Vg/Tinv)). The expected NBTI dependence on Eox (ΔVth ~ (Vg/Tinv)4) is recovered when the as-grown thermal thick oxide is treated with an additional high temperature anneal. We have evaluated the NBTI induced ΔVth time evolution, its recovery behavior, temperature and voltage dependence under DC and AC bias stress conditions with and without the oxide thermal treatment. Our observations over the two gate stack processes (as-grown I/O oxide with and without anneal treatment) support the NBTI physical picture of two uncorrelated contributions to the NBTI damage. Namely, shallow hole trap activation in process induced pre-existing (before stress) traps as well as deep hole traps and/or interface states generation. The last component is quasi permanent and is dominant in both gate stack processes. In particular, for the as-grown I/O oxide the NBTI damage is mainly due to an increase contribution of the quasi permanent component with increasing Tinv. This unexpected Tinv dependence is reduced by the additional anneal treatment. The implication of these findings on the NBTI characterization and modeling will be discussed.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Magnetic field induced gate leakage current in 65nm nMOS transistors

2009 Proceedings of the European Solid State Device Research Conference, 2009

Bookmarks Related papers MentionsView impact

Research paper thumbnail of High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

IEEE International Reliability Physics Symposium Proceedings, 2010

... Semiconductor Research & Development Center, Hopewell Junction, NY 12533 We are grateful ... more ... Semiconductor Research & Development Center, Hopewell Junction, NY 12533 We are grateful for helpful discussions with Jordi Sune, Tanya Nigam, Ernest Wu, Eduard Cartier, Andreas Kerber. FR=0.01%,K=102 FR=0.1%,K=103 FR=1% FR=5% FR=10% IL HK IL+HK ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998

... M. Hargrove, S. Crowder, E. Nowak, R. Logan, LK Han, H. Ng, A. Ray, D. Sinitsky, P. Smeys, F.... more ... M. Hargrove, S. Crowder, E. Nowak, R. Logan, LK Han, H. Ng, A. Ray, D. Sinitsky, P. Smeys, F. Guarin, J. Oberschmidt, E. Crabbe, D ... In order to achieve optimal device performance, thin gate oxide, retrograde wells and strong halos coupled with shallow junctions are required. ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of SiGe HBT performance and reliability trends through f/sub T/ of 350 GHz

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual., 2003

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Device scaling and application trends for over 200GHz SiGe HBTs

2003 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003. Digest of Papers., 2003

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Wafer level reliability evaluation of 120GHz SiGe HBT's

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004., 2004

A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bip... more A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a wafer level reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz fT and 100 GHz fmax. Accelerated current stress as high as Jc=34

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Nanometer Scale Complementary Silicon MOSFETs as Detectors of Terahertz and Sub-terahertz Radiation

2007 IEEE Sensors, 2007

Bookmarks Related papers MentionsView impact