Frank Poppen - Academia.edu (original) (raw)
Papers by Frank Poppen
2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)
Up-to-date FPGA evaluation boards, like the Digilent Arty A7 mounting a Xilinx Artix-7 FPGA, come... more Up-to-date FPGA evaluation boards, like the Digilent Arty A7 mounting a Xilinx Artix-7 FPGA, come with an integrated<br> FTDI chip which makes programming and debugging quite easy. In our work, we synthesized the VexRiscv based Murax<br> processor to an Artix-7 FPGA and at first lead out the JTAG relevant signals of the Riscv core to the board's Pmod<br> Header to connect to a dedicated Olimex JTAG Adapter through a second USB cable. As it turns out, this extra effort<br> on hardware can be minimized by use of some Xilinx Debug IP named BSCANE2. Collecting the required information on how<br> to do this was tedious. So we came to the decision to document our path to success with this short report. We expect<br> that the reader is familiar with the README.md to be found at https://github.com/SpinalHDL/VexRiscv and that the<br> reader is capable of generating the Murax SoC as it is described there.
FDL 2011 Proceedings, 2011
Due to the ever increasing need for enhanced productivity in electronic system design new methods... more Due to the ever increasing need for enhanced productivity in electronic system design new methods and tools in the area of Electronic System Level (ESL) design are becoming more important. Regrettably, the introduction of new methods and tools come at a certain cost, and after its introduction it might be hard to assess the real improvements in the development process. In this paper we present a methodology to model the design process and linked cause-effects based on experience and statistical data. In our case-study we create two models of the same design flow: 1st traditional design flow and 2nd ESL design flow using high-level synthesis. By means of Monte Carlo simulations we automatically process 10.000 probabilistically varied benchmark runs so that the causalities in the modeled development process become clear and the impact of changes to the flow can be predicted prior to their implementation.
New design methods and tools often promise large benefits for specific engineering tasks or whole... more New design methods and tools often promise large benefits for specific engineering tasks or whole engineering processes to make increasingly complex and sophisticated products possible. However, estimations for the pay-off of new methods or tools are based on gut feelings or rare expert knowledge. In this paper we present our approach for well-founded quantitative estimations for the economic impact of new methods or tools. We show the beginning of our methodology with an early experiment and the impact analysis for a case study of a design flow for electronic circuits.
SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to dou... more SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to double every 18 months as Moore’s Law did not loose its correctness yet. Higher levels of abstraction need to be introduced to handle the billions of transistors of future designs and to keep, or even better shorten, time to market. At the same point the designer of these sub micron devices will have to observe the power dissipation of his SoC. The continuous enhancement of battery’s energy capacity does not keep up with the more and more power consuming applications. This is critical to handheld products like cellular phones and PDAs. RT level abstraction is the entry point in most designflows today. During synthesis a gate level netlist is being generated. If any, power estimations and optimizations usually are performed on these netlists. In the low power community it is well known that at this point most opportunities of higher level power optimizations are wasted. The better flow is th...
Simulation of systems under development is a widely used methodology for early design evaluation ... more Simulation of systems under development is a widely used methodology for early design evaluation and performance analysis. Many engineers trust on MATLAB & Simulink as a simulation environment, especially since it offers many domain specific block sets for fast, easy and efficient use. With its ability to generate life source code from the simulation model it becomes a powerful development tool. After code generation it is common practice to proceed to the real world and maybe coupling HW executing the generated SW with simulation (HW in the loop simulation), which can be considered to be a big jump into the cold water. The contribution of this paper is a concept and proof-of-concept implementation of a co-simulation interface between a C-based System on Chip (SoC) model and MATLAB & Simulink. The proposed approach enables the coupling of application domain specific high level simulation with a bit and cycle accurate virtual execution platform of a specific embedded HW/SW platform w...
Proceedings of the Workshop on Design Automation for CPS and IoT, 2019
The application of digital control in the automotive domain clearly follows an evolution with inc... more The application of digital control in the automotive domain clearly follows an evolution with increasing complexity of both covered functions and their interaction. Advanced Driver Assistance Systems (ADAS) and Automated Driving (AD) functions comprise modular interacting software components that typically build upon a layered architecture. As these components are generally developed by different teams, using different tools for different functional purposes and building upon different models of computation, an integration of all components guaranteeing the satisfaction of all requirements calls for coherent handling of timing properties. In this work we propose to address this challenge by applying four well-known paradigms consisting out of a contract-based component framework, formal timing specifications and semantically clear computation and interaction models. For making these paradigms accessible for engineers we have integrated them into an Eclipse-based environment, called ...
Global markets dictate the continuous improvement of the efficiency of any industries' develo... more Global markets dictate the continuous improvement of the efficiency of any industries' development processes. This is especially true for the industry of integrated circuits. Unfortunately, it is usually not obvious how one can improve development processes to stay in business. Some few time-consuming benchmark runs cannot deliver a deep insight in new process methodologies and company specific best practices. In this paper we demonstrate that it is possible to estimate the impact of process changes on effort, cost and quality in an Electronic Design Automation (EDA) flow using a defined methodology and our IMPACT tool. We simulate a design flow 10.000 times in a probabilistic manner and analyze the influence of cause-effect relationships on the development effort and costs. This approach allows the prediction of process behavior prior to the implementation of process changes.
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, 2014
Intelligent automotive electronics significantly improved driving safety in the last decades. Wit... more Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.
SAE Technical Paper Series
Simulation of systems under development is a widely used methodology for early design evaluation ... more Simulation of systems under development is a widely used methodology for early design evaluation and performance analysis. Many engineers trust on MATLAB & Simulink as a simulation environment, especially since it offers many domain specific block sets for fast, easy and efficient use. With its ability to generate life source code from the simulation model it becomes a powerful development tool. After code generation it is common practice to proceed to the real world and maybe coupling HW executing the generated SW with simulation (HW in the loop simulation), which can be considered to be a big jump into the cold water. The contribution of this paper is a concept and proof-of-concept implementation of a co-simulation interface between a C-based System on Chip (SoC) model and MATLAB & Simulink. The proposed approach enables the coupling of application domain specific high level simulation with a bit and cycle accurate virtual execution platform of a specific embedded HW/SW platform without interfacing troubles. Our concept was implemented for and applied to the development of an embedded medical devicea Wearable Artificial Kidney Device (WAKD).
Fdl 2011 Proceedings, 2011
Abstract Due to the ever increasing need for enhanced productivity in electronic system design ne... more Abstract Due to the ever increasing need for enhanced productivity in electronic system design new methods and tools in the area of Electronic System Level (ESL) design are becoming more important. Regrettably, the introduction of new methods and tools come at ...
The psychoacoustically motivated filter-bank design introduced in this paper was systematically e... more The psychoacoustically motivated filter-bank design introduced in this paper was systematically examined for power reduction potential by applying methodologies and tools supporting power analysis and optimisation at different levels of abstraction. The application of selected tools from the tool suite that was developed in the European project POET, led to a 62 % reduction of power compared to the initial non-optimised design. We show that optimising integrated circuits for power early in the design-phase at high abstraction levels uncovers potential for dramatic savings of power consumption.
In this paper we demonstrate that estimating power at abstraction levels higher than gate or even... more In this paper we demonstrate that estimating power at abstraction levels higher than gate or even RTL early in the design flow is a feasible approach towards broadening the design-space exploration process, shortening time to market and designing integrated circuits with reduced power dissipation. We compare different implementations of a benchmark design at different levels of abstraction, starting from the algorithm level. Different algorithms for a 128-point FFT/iFFT processor for ultrawide band communication systems [8] are estimated for power using the ChipVision tool ORINOCO [7]. We compare the results with estimations at lower abstraction levels using the Cadence tools RTL Compiler, BuildGates and ncsim. We conclude that it is possible to make the right decisions regarding power at algorithmic abstraction level without coding a single line of HDL.
ABSTRACT Over the last decades, intelligent electronics in heterogeneous systems improved all asp... more ABSTRACT Over the last decades, intelligent electronics in heterogeneous systems improved all aspects of everyone’s daily life. An advantage a modern civilization cannot ignore. The increasing complexity of the electronic components though, makes us dependent on solving a growing design verification challenge. Especially knowing, that safety relevant functionality as in automotive driving is part of this development. Standardized as well as proprietary concepts, languages and tools line up for the task [6]. Unfortunately, there is no such thing as one size fits all in this. Verification engineers need to choose and combine what fits best for the company, the design-team and application domain. They create company’s verification strategies with deep roots into the design process. Changes to the strategy need to be done carefully and incrementally to ensure continued productivity. Based on VHDL in the past, our IFS verification methodology was also implemented in SystemC (SC) [2] and covers Analog Mixed-Signal (AMS) [1] [4], and Matlab/Simulink [3] today. In this work we proceed with concepts of UVM [9] and show how UVM components are instantiable in our SC test environment to verify designs specified in VHDL (-AMS), SystemC (-AMS), Verilog (-AMS) or any language a mixed-language simulation environment exists for. Our work does not depend on proprietary technology, but is applicable to any SC based environment.
Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn), 2014
ABSTRACT We present a new system-level design methodology enabling the consideration of process v... more ABSTRACT We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level backannotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multiphysics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.
Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn), 2014
ABSTRACT We present a new system-level design methodology enabling the consideration of process v... more ABSTRACT We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level backannotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multiphysics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.
EURASIP Journal on Advances in Signal Processing, 2009
A concept and architecture of a personal communication system (PCS) is introduced that integrates... more A concept and architecture of a personal communication system (PCS) is introduced that integrates audio communication and hearing support for the elderly and hearing-impaired through a personal hearing system (PHS). The concept envisions a central processor connected to audio headsets via a wireless body area network (WBAN). To demonstrate the concept, a prototype PCS is presented that is implemented on a netbook computer with a dedicated audio interface in combination with a mobile phone. The prototype can be used for field-testing possible applications and to reveal possibilities and limitations of the concept of integrating hearing support in consumer audio communication devices. It is shown that the prototype PCS can integrate hearing aid functionality, telephony, public announcement systems, and home entertainment. An exemplary binaural speech enhancement scheme that represents a large class of possible PHS processing schemes is shown to be compatible with the general concept. However, an analysis of hardware and software architectures shows that the implementation of a PCS on future advanced cell phone-like devices is challenging. Because of limitations in processing power, recoding of prototype implementations into fixed point arithmetic will be required and WBAN performance is still a limiting factor in terms of data rate and delay.
SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to dou... more SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to double every 18 months as Moore's Law did not loose its correctness yet. Higher levels of abstraction need to be introduced to handle the billions of transistors of future designs and to keep, or even better shorten, time to market. At the same point the
2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)
Up-to-date FPGA evaluation boards, like the Digilent Arty A7 mounting a Xilinx Artix-7 FPGA, come... more Up-to-date FPGA evaluation boards, like the Digilent Arty A7 mounting a Xilinx Artix-7 FPGA, come with an integrated<br> FTDI chip which makes programming and debugging quite easy. In our work, we synthesized the VexRiscv based Murax<br> processor to an Artix-7 FPGA and at first lead out the JTAG relevant signals of the Riscv core to the board's Pmod<br> Header to connect to a dedicated Olimex JTAG Adapter through a second USB cable. As it turns out, this extra effort<br> on hardware can be minimized by use of some Xilinx Debug IP named BSCANE2. Collecting the required information on how<br> to do this was tedious. So we came to the decision to document our path to success with this short report. We expect<br> that the reader is familiar with the README.md to be found at https://github.com/SpinalHDL/VexRiscv and that the<br> reader is capable of generating the Murax SoC as it is described there.
FDL 2011 Proceedings, 2011
Due to the ever increasing need for enhanced productivity in electronic system design new methods... more Due to the ever increasing need for enhanced productivity in electronic system design new methods and tools in the area of Electronic System Level (ESL) design are becoming more important. Regrettably, the introduction of new methods and tools come at a certain cost, and after its introduction it might be hard to assess the real improvements in the development process. In this paper we present a methodology to model the design process and linked cause-effects based on experience and statistical data. In our case-study we create two models of the same design flow: 1st traditional design flow and 2nd ESL design flow using high-level synthesis. By means of Monte Carlo simulations we automatically process 10.000 probabilistically varied benchmark runs so that the causalities in the modeled development process become clear and the impact of changes to the flow can be predicted prior to their implementation.
New design methods and tools often promise large benefits for specific engineering tasks or whole... more New design methods and tools often promise large benefits for specific engineering tasks or whole engineering processes to make increasingly complex and sophisticated products possible. However, estimations for the pay-off of new methods or tools are based on gut feelings or rare expert knowledge. In this paper we present our approach for well-founded quantitative estimations for the economic impact of new methods or tools. We show the beginning of our methodology with an early experiment and the impact analysis for a case study of a design flow for electronic circuits.
SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to dou... more SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to double every 18 months as Moore’s Law did not loose its correctness yet. Higher levels of abstraction need to be introduced to handle the billions of transistors of future designs and to keep, or even better shorten, time to market. At the same point the designer of these sub micron devices will have to observe the power dissipation of his SoC. The continuous enhancement of battery’s energy capacity does not keep up with the more and more power consuming applications. This is critical to handheld products like cellular phones and PDAs. RT level abstraction is the entry point in most designflows today. During synthesis a gate level netlist is being generated. If any, power estimations and optimizations usually are performed on these netlists. In the low power community it is well known that at this point most opportunities of higher level power optimizations are wasted. The better flow is th...
Simulation of systems under development is a widely used methodology for early design evaluation ... more Simulation of systems under development is a widely used methodology for early design evaluation and performance analysis. Many engineers trust on MATLAB & Simulink as a simulation environment, especially since it offers many domain specific block sets for fast, easy and efficient use. With its ability to generate life source code from the simulation model it becomes a powerful development tool. After code generation it is common practice to proceed to the real world and maybe coupling HW executing the generated SW with simulation (HW in the loop simulation), which can be considered to be a big jump into the cold water. The contribution of this paper is a concept and proof-of-concept implementation of a co-simulation interface between a C-based System on Chip (SoC) model and MATLAB & Simulink. The proposed approach enables the coupling of application domain specific high level simulation with a bit and cycle accurate virtual execution platform of a specific embedded HW/SW platform w...
Proceedings of the Workshop on Design Automation for CPS and IoT, 2019
The application of digital control in the automotive domain clearly follows an evolution with inc... more The application of digital control in the automotive domain clearly follows an evolution with increasing complexity of both covered functions and their interaction. Advanced Driver Assistance Systems (ADAS) and Automated Driving (AD) functions comprise modular interacting software components that typically build upon a layered architecture. As these components are generally developed by different teams, using different tools for different functional purposes and building upon different models of computation, an integration of all components guaranteeing the satisfaction of all requirements calls for coherent handling of timing properties. In this work we propose to address this challenge by applying four well-known paradigms consisting out of a contract-based component framework, formal timing specifications and semantically clear computation and interaction models. For making these paradigms accessible for engineers we have integrated them into an Eclipse-based environment, called ...
Global markets dictate the continuous improvement of the efficiency of any industries' develo... more Global markets dictate the continuous improvement of the efficiency of any industries' development processes. This is especially true for the industry of integrated circuits. Unfortunately, it is usually not obvious how one can improve development processes to stay in business. Some few time-consuming benchmark runs cannot deliver a deep insight in new process methodologies and company specific best practices. In this paper we demonstrate that it is possible to estimate the impact of process changes on effort, cost and quality in an Electronic Design Automation (EDA) flow using a defined methodology and our IMPACT tool. We simulate a design flow 10.000 times in a probabilistic manner and analyze the influence of cause-effect relationships on the development effort and costs. This approach allows the prediction of process behavior prior to the implementation of process changes.
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, 2014
Intelligent automotive electronics significantly improved driving safety in the last decades. Wit... more Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.
SAE Technical Paper Series
Simulation of systems under development is a widely used methodology for early design evaluation ... more Simulation of systems under development is a widely used methodology for early design evaluation and performance analysis. Many engineers trust on MATLAB & Simulink as a simulation environment, especially since it offers many domain specific block sets for fast, easy and efficient use. With its ability to generate life source code from the simulation model it becomes a powerful development tool. After code generation it is common practice to proceed to the real world and maybe coupling HW executing the generated SW with simulation (HW in the loop simulation), which can be considered to be a big jump into the cold water. The contribution of this paper is a concept and proof-of-concept implementation of a co-simulation interface between a C-based System on Chip (SoC) model and MATLAB & Simulink. The proposed approach enables the coupling of application domain specific high level simulation with a bit and cycle accurate virtual execution platform of a specific embedded HW/SW platform without interfacing troubles. Our concept was implemented for and applied to the development of an embedded medical devicea Wearable Artificial Kidney Device (WAKD).
Fdl 2011 Proceedings, 2011
Abstract Due to the ever increasing need for enhanced productivity in electronic system design ne... more Abstract Due to the ever increasing need for enhanced productivity in electronic system design new methods and tools in the area of Electronic System Level (ESL) design are becoming more important. Regrettably, the introduction of new methods and tools come at ...
The psychoacoustically motivated filter-bank design introduced in this paper was systematically e... more The psychoacoustically motivated filter-bank design introduced in this paper was systematically examined for power reduction potential by applying methodologies and tools supporting power analysis and optimisation at different levels of abstraction. The application of selected tools from the tool suite that was developed in the European project POET, led to a 62 % reduction of power compared to the initial non-optimised design. We show that optimising integrated circuits for power early in the design-phase at high abstraction levels uncovers potential for dramatic savings of power consumption.
In this paper we demonstrate that estimating power at abstraction levels higher than gate or even... more In this paper we demonstrate that estimating power at abstraction levels higher than gate or even RTL early in the design flow is a feasible approach towards broadening the design-space exploration process, shortening time to market and designing integrated circuits with reduced power dissipation. We compare different implementations of a benchmark design at different levels of abstraction, starting from the algorithm level. Different algorithms for a 128-point FFT/iFFT processor for ultrawide band communication systems [8] are estimated for power using the ChipVision tool ORINOCO [7]. We compare the results with estimations at lower abstraction levels using the Cadence tools RTL Compiler, BuildGates and ncsim. We conclude that it is possible to make the right decisions regarding power at algorithmic abstraction level without coding a single line of HDL.
ABSTRACT Over the last decades, intelligent electronics in heterogeneous systems improved all asp... more ABSTRACT Over the last decades, intelligent electronics in heterogeneous systems improved all aspects of everyone’s daily life. An advantage a modern civilization cannot ignore. The increasing complexity of the electronic components though, makes us dependent on solving a growing design verification challenge. Especially knowing, that safety relevant functionality as in automotive driving is part of this development. Standardized as well as proprietary concepts, languages and tools line up for the task [6]. Unfortunately, there is no such thing as one size fits all in this. Verification engineers need to choose and combine what fits best for the company, the design-team and application domain. They create company’s verification strategies with deep roots into the design process. Changes to the strategy need to be done carefully and incrementally to ensure continued productivity. Based on VHDL in the past, our IFS verification methodology was also implemented in SystemC (SC) [2] and covers Analog Mixed-Signal (AMS) [1] [4], and Matlab/Simulink [3] today. In this work we proceed with concepts of UVM [9] and show how UVM components are instantiable in our SC test environment to verify designs specified in VHDL (-AMS), SystemC (-AMS), Verilog (-AMS) or any language a mixed-language simulation environment exists for. Our work does not depend on proprietary technology, but is applicable to any SC based environment.
Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn), 2014
ABSTRACT We present a new system-level design methodology enabling the consideration of process v... more ABSTRACT We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level backannotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multiphysics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.
Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn), 2014
ABSTRACT We present a new system-level design methodology enabling the consideration of process v... more ABSTRACT We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level backannotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multiphysics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.
EURASIP Journal on Advances in Signal Processing, 2009
A concept and architecture of a personal communication system (PCS) is introduced that integrates... more A concept and architecture of a personal communication system (PCS) is introduced that integrates audio communication and hearing support for the elderly and hearing-impaired through a personal hearing system (PHS). The concept envisions a central processor connected to audio headsets via a wireless body area network (WBAN). To demonstrate the concept, a prototype PCS is presented that is implemented on a netbook computer with a dedicated audio interface in combination with a mobile phone. The prototype can be used for field-testing possible applications and to reveal possibilities and limitations of the concept of integrating hearing support in consumer audio communication devices. It is shown that the prototype PCS can integrate hearing aid functionality, telephony, public announcement systems, and home entertainment. An exemplary binaural speech enhancement scheme that represents a large class of possible PHS processing schemes is shown to be compatible with the general concept. However, an analysis of hardware and software architectures shows that the implementation of a PCS on future advanced cell phone-like devices is challenging. Because of limitations in processing power, recoding of prototype implementations into fixed point arithmetic will be required and WBAN performance is still a limiting factor in terms of data rate and delay.
SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to dou... more SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to double every 18 months as Moore's Law did not loose its correctness yet. Higher levels of abstraction need to be introduced to handle the billions of transistors of future designs and to keep, or even better shorten, time to market. At the same point the