John Kikidis - Academia.edu (original) (raw)

Papers by John Kikidis

Research paper thumbnail of Enabling 10Gb/s Ethernet in Legacy Multi Mode Fiber Enterprise Networks

This paper describes the fundamentals of optical enterprise networks, including the enterprise Mu... more This paper describes the fundamentals of optical enterprise networks, including the enterprise Multi Source Agreement optical transceivers and their architecture. Then the different Ethernet optical PHY standards, and latest EDC technology that utilizes electronic signal processing methods to enable 10Gb/s Ethernet transmission over legacy MMF optical links, is presented. Finally, the EDC associated IEEE standard developments are presented.

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Research paper thumbnail of A combo Analog-to-Digital/Analog-to-Multiple-Value converter with configurable resolution

An analog-to-digital converter (ADC) with a configurable 4, 8 or 12-bit resolution is presented i... more An analog-to-digital converter (ADC) with a configurable 4, 8 or 12-bit resolution is presented in this paper. It is based on a binary tree structure implemented with current-mode circuits whereas an appropriate integer division is performed at the nodes of the tree. The binary representation of the analog input value is produced at the leaves of the tree while its

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Research paper thumbnail of Application of Forward Error Correcting Algorithms to Positioning Systems

Several new position estimation methods based on the error rate of received infrared patters were... more Several new position estimation methods based on the error rate of received infrared patters were discussed in this chapter. The estimation of the features of the infrared channel of the

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Research paper thumbnail of Investigation of 10-Gb/s RSOA-based upstream transmission in WDM-PONs utilizing optical filtering and electronic equalization

Export Date: 10 February 2012, Source: Scopus

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Research paper thumbnail of Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm

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Research paper thumbnail of Localization of a Target with Three Degrees of Freedom Using a Low Cost Wireless Infrared Sensor Network

Wireless Sensor Network, 2009

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Research paper thumbnail of Upstream transmission in WDM PONs at 10Gbps using low bandwidth RSOAs assisted with optical filtering and electronic equalization

2008 34th European Conference on Optical Communication, 2008

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Research paper thumbnail of Near-lossless compression of continuous-tone still images using fuzzy logic notions and the binary arithmetic coder (Q-Coder)

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 1994

There are numerous fields of applications that demand the storage of large quantities of data tha... more There are numerous fields of applications that demand the storage of large quantities of data that represent images. Many of these applications need to preserve every single detail of the input picture (e.g. medical purposes) thus image compression is necessary to reduce the number of bytes that are stored in a magnetic or optical medium. In this paper a novel

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Research paper thumbnail of Use of interleaving and error correction to infrared patterns for the improvement of position estimation systems

2008 IEEE International Conference on Emerging Technologies and Factory Automation, 2008

The problem of estimating the position of a mobile target indoors, has been addressed using sever... more The problem of estimating the position of a mobile target indoors, has been addressed using several approaches that are based on different media including RF, laser, ultrasonic, infrared or even magnetic signals [2-5]. The most popular localization methods rely either on ...

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Research paper thumbnail of Transmission performance improvement studies for low-cost 2.5 Gb/s rated DML sources operated at 10 Gb/s

2008 34th European Conference on Optical Communication, 2008

Introduction For the design of cost efficient terminal nodes in metro/access systems, the use of ... more Introduction For the design of cost efficient terminal nodes in metro/access systems, the use of directly modulated lasers (DMLs) is preferable due to their low cost, low driving voltage, small size and high output power. According to current standards (ITU-T G984.1), 2.5Gb/s transmitters must support distances up to 20 Km. Although current DML-based products satisfy this requirement, the frequency chirp characteristics and the limited bandwidth of 2.5Gb/s rated DMLs prevent their operation at 10Gb/s. However, research efforts are underway to extend the ...

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Research paper thumbnail of Sample/Hold, V2I and output latching techniques for an asynchronous low area ADC

2009 International Symposium on Signals, Circuits and Systems, 2009

The architecture of an asynchronous CMOS Analogue to Digital Converter (ADC) with a binary tree s... more The architecture of an asynchronous CMOS Analogue to Digital Converter (ADC) with a binary tree structure exhibiting ultra low die area and power consumption will be presented in this paper. It is based on integer division that is implemented by current mode circuits that operate without a clock signal. Special emphasis is given on the description of the Sample/Hold and

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Research paper thumbnail of Electronic Mitigation of the Filter Concatenation Effect of Low-Cost 2.5 Gb/s Rated DMLs Sources Operated at 10 Gb/s

Optical Fiber Communication Conference and National Fiber Optic Engineers Conference, 2009

Abstract: We experimentally investigate (using a re-circulating loop) the benefit of electronic e... more Abstract: We experimentally investigate (using a re-circulating loop) the benefit of electronic equalization in the mitigation of filter concatenation effects for low-cost DML transmitters rated for 2.5Gb/s but operated at 10Gb/s, applicable in transparent metro networks. ©2008 Optical Society of America OCIS codes: (060.2330) Fiber Optics Communications; (060.2360) Fiber Optics Links and Subsystems ... 1. Introduction Due to the fact that the metro network market is very cost sensitive, optical transparent network designs (without optoelectronic regeneration) appear attractive. However, one of ...

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Research paper thumbnail of Full-Duplex Bidirectional Transmission at 10 Gbps in WDM PONs with RSOA-Based ONU Using Offset Optical Filtering and Electronic Equalization

Optical Fiber Communication Conference and National Fiber Optic Engineers Conference, 2009

Full-Duplex Bidirectional Transmission at 10 Gbps in WDM ... PONs with RSOA-based ONU using Offse... more Full-Duplex Bidirectional Transmission at 10 Gbps in WDM ... PONs with RSOA-based ONU using Offset Optical Filtering ... M. Omella1*, I. Papagiannakis2, B. Schrenk1, D. Klonidis3, AN Birbas2, J. Kikidis4, J. Prat1 and I. Tomkos3 1: Signal Theory & Communications Dept., Universitat Politècnica de Catalunya (UPC) Barcelona, Spain 2: Electrical & Computer Eng. Dept, University of Patras, Rio, 26500 Patras, Greece 3: Athens Information Technology, 0.8km Markopoulo Av. Peania, Athens, Greece 4: Analog Integrated Electronic Systems SA, Greece * ...

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Research paper thumbnail of Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009

Abstract— An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a... more Abstract— An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a 150MS/s sampling rate and dissipating 34mW power. It is based on integer division circuits that are arranged in a binary tree structure. We emphasize on the digital calibration ...

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Research paper thumbnail of Asynchronous ADC with configurable resolution and binary tree structure

2010 4th International Symposium on Communications, Control and Signal Processing (ISCCSP), 2010

An Analogue to Digital Converter (ADC) implemented in CMOS technology (90nm TSMC) is described in... more An Analogue to Digital Converter (ADC) implemented in CMOS technology (90nm TSMC) is described in this paper which is based on a binary tree structure and has a configurable 4, 8 or 12-bits resolution. The function performed at the nodes of the binary tree is an integer division by a proper power of 2, that is implemented by a novel circuit. The developed ADC system is an asynchronous circuit operating in current mode needing only a small number of components. This fact in conjunction with the binary tree structure of the ADC architecture, lead to implementations with very low die area and power consumption (0.12mm2 and 72mW respectively for 12-bit resolution). The average sampling rate exceeds 140MS/s for 12-bit resolution. The proposed device can also be used in multi Gbps time-interleaved parallel ADC due to its very low die area and power consumption.

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Research paper thumbnail of An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division

2010 IEEE Computer Society Annual Symposium on VLSI, 2010

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Research paper thumbnail of Selecting appropriate calibration points for an ultra low area 8-bit subrange ADC

2010 8th Workshop on Intelligent Solutions in Embedded Systems, 2010

An ultra low area 8-bit subrange Analogue/Digital Converter that consists of a pair of Flash 4-bi... more An ultra low area 8-bit subrange Analogue/Digital Converter that consists of a pair of Flash 4-bit converter stages is described in this paper emphasising on the appropriate method for its real time calibration. Its active area occupies only 0.04 mm2 and dissipates less than 22 mW. The sampling rate is higher than 500 MS/s and the achieved Signal to Noise

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Research paper thumbnail of Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm<sup>2</sup> ADC with binary tree structure

2009 IEEE Conference on Emerging Technologies & Factory Automation, 2009

A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bi... more A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bits resolution, using a binary tree structure is presented which needs very low silicon area and relatively low power consumption for its implementation. The sampling rate of the 12-bit ADC exceeds 140MS/s and requires only 0.12 mm2 of area making it appropriate for ultra wideband

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Research paper thumbnail of The use of electronic equalization and offset filtering in the performance improvement of low-cost DML transmitters

2008 10th Anniversary International Conference on Transparent Optical Networks, 2008

Abstract The use of electronic compensation techniques for the transmission improvement of low-co... more Abstract The use of electronic compensation techniques for the transmission improvement of low-cost directly modulated sources is studied and evaluated experimentally. More specifically the research efforts presented here targeting in enhancing the transmission reach of common DML sources with limited bandwidth fabricated for operation at 2.5 Gb/s, but operated at 10 Gb/s. Performance improvement is achieved by means of electronic feed-forward and decision-feedback equalization (FFE/DFE) as well as off-set optical filtering at ...

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Research paper thumbnail of A voltage mode integer divider for fast A/D Conversion

2010 IEEE International Symposium on Industrial Electronics, 2010

Abstract-An analog circuit capable of implementing an integer division by a constant number is pr... more Abstract-An analog circuit capable of implementing an integer division by a constant number is presented in this paper. The quotient and the residue of the division are generated concurrently by a circuit operating in voltage mode that can be used in various A/D Conversion (ADC) ...

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Research paper thumbnail of Enabling 10Gb/s Ethernet in Legacy Multi Mode Fiber Enterprise Networks

This paper describes the fundamentals of optical enterprise networks, including the enterprise Mu... more This paper describes the fundamentals of optical enterprise networks, including the enterprise Multi Source Agreement optical transceivers and their architecture. Then the different Ethernet optical PHY standards, and latest EDC technology that utilizes electronic signal processing methods to enable 10Gb/s Ethernet transmission over legacy MMF optical links, is presented. Finally, the EDC associated IEEE standard developments are presented.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A combo Analog-to-Digital/Analog-to-Multiple-Value converter with configurable resolution

An analog-to-digital converter (ADC) with a configurable 4, 8 or 12-bit resolution is presented i... more An analog-to-digital converter (ADC) with a configurable 4, 8 or 12-bit resolution is presented in this paper. It is based on a binary tree structure implemented with current-mode circuits whereas an appropriate integer division is performed at the nodes of the tree. The binary representation of the analog input value is produced at the leaves of the tree while its

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Research paper thumbnail of Application of Forward Error Correcting Algorithms to Positioning Systems

Several new position estimation methods based on the error rate of received infrared patters were... more Several new position estimation methods based on the error rate of received infrared patters were discussed in this chapter. The estimation of the features of the infrared channel of the

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Research paper thumbnail of Investigation of 10-Gb/s RSOA-based upstream transmission in WDM-PONs utilizing optical filtering and electronic equalization

Export Date: 10 February 2012, Source: Scopus

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Research paper thumbnail of Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Localization of a Target with Three Degrees of Freedom Using a Low Cost Wireless Infrared Sensor Network

Wireless Sensor Network, 2009

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Research paper thumbnail of Upstream transmission in WDM PONs at 10Gbps using low bandwidth RSOAs assisted with optical filtering and electronic equalization

2008 34th European Conference on Optical Communication, 2008

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Near-lossless compression of continuous-tone still images using fuzzy logic notions and the binary arithmetic coder (Q-Coder)

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 1994

There are numerous fields of applications that demand the storage of large quantities of data tha... more There are numerous fields of applications that demand the storage of large quantities of data that represent images. Many of these applications need to preserve every single detail of the input picture (e.g. medical purposes) thus image compression is necessary to reduce the number of bytes that are stored in a magnetic or optical medium. In this paper a novel

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Research paper thumbnail of Use of interleaving and error correction to infrared patterns for the improvement of position estimation systems

2008 IEEE International Conference on Emerging Technologies and Factory Automation, 2008

The problem of estimating the position of a mobile target indoors, has been addressed using sever... more The problem of estimating the position of a mobile target indoors, has been addressed using several approaches that are based on different media including RF, laser, ultrasonic, infrared or even magnetic signals [2-5]. The most popular localization methods rely either on ...

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Research paper thumbnail of Transmission performance improvement studies for low-cost 2.5 Gb/s rated DML sources operated at 10 Gb/s

2008 34th European Conference on Optical Communication, 2008

Introduction For the design of cost efficient terminal nodes in metro/access systems, the use of ... more Introduction For the design of cost efficient terminal nodes in metro/access systems, the use of directly modulated lasers (DMLs) is preferable due to their low cost, low driving voltage, small size and high output power. According to current standards (ITU-T G984.1), 2.5Gb/s transmitters must support distances up to 20 Km. Although current DML-based products satisfy this requirement, the frequency chirp characteristics and the limited bandwidth of 2.5Gb/s rated DMLs prevent their operation at 10Gb/s. However, research efforts are underway to extend the ...

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Research paper thumbnail of Sample/Hold, V2I and output latching techniques for an asynchronous low area ADC

2009 International Symposium on Signals, Circuits and Systems, 2009

The architecture of an asynchronous CMOS Analogue to Digital Converter (ADC) with a binary tree s... more The architecture of an asynchronous CMOS Analogue to Digital Converter (ADC) with a binary tree structure exhibiting ultra low die area and power consumption will be presented in this paper. It is based on integer division that is implemented by current mode circuits that operate without a clock signal. Special emphasis is given on the description of the Sample/Hold and

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Research paper thumbnail of Electronic Mitigation of the Filter Concatenation Effect of Low-Cost 2.5 Gb/s Rated DMLs Sources Operated at 10 Gb/s

Optical Fiber Communication Conference and National Fiber Optic Engineers Conference, 2009

Abstract: We experimentally investigate (using a re-circulating loop) the benefit of electronic e... more Abstract: We experimentally investigate (using a re-circulating loop) the benefit of electronic equalization in the mitigation of filter concatenation effects for low-cost DML transmitters rated for 2.5Gb/s but operated at 10Gb/s, applicable in transparent metro networks. ©2008 Optical Society of America OCIS codes: (060.2330) Fiber Optics Communications; (060.2360) Fiber Optics Links and Subsystems ... 1. Introduction Due to the fact that the metro network market is very cost sensitive, optical transparent network designs (without optoelectronic regeneration) appear attractive. However, one of ...

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Research paper thumbnail of Full-Duplex Bidirectional Transmission at 10 Gbps in WDM PONs with RSOA-Based ONU Using Offset Optical Filtering and Electronic Equalization

Optical Fiber Communication Conference and National Fiber Optic Engineers Conference, 2009

Full-Duplex Bidirectional Transmission at 10 Gbps in WDM ... PONs with RSOA-based ONU using Offse... more Full-Duplex Bidirectional Transmission at 10 Gbps in WDM ... PONs with RSOA-based ONU using Offset Optical Filtering ... M. Omella1*, I. Papagiannakis2, B. Schrenk1, D. Klonidis3, AN Birbas2, J. Kikidis4, J. Prat1 and I. Tomkos3 1: Signal Theory &amp;amp;amp;amp;amp;amp;amp;amp; Communications Dept., Universitat Politècnica de Catalunya (UPC) Barcelona, Spain 2: Electrical &amp;amp;amp;amp;amp;amp;amp;amp; Computer Eng. Dept, University of Patras, Rio, 26500 Patras, Greece 3: Athens Information Technology, 0.8km Markopoulo Av. Peania, Athens, Greece 4: Analog Integrated Electronic Systems SA, Greece * ...

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Research paper thumbnail of Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009

Abstract— An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a... more Abstract— An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a 150MS/s sampling rate and dissipating 34mW power. It is based on integer division circuits that are arranged in a binary tree structure. We emphasize on the digital calibration ...

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Research paper thumbnail of Asynchronous ADC with configurable resolution and binary tree structure

2010 4th International Symposium on Communications, Control and Signal Processing (ISCCSP), 2010

An Analogue to Digital Converter (ADC) implemented in CMOS technology (90nm TSMC) is described in... more An Analogue to Digital Converter (ADC) implemented in CMOS technology (90nm TSMC) is described in this paper which is based on a binary tree structure and has a configurable 4, 8 or 12-bits resolution. The function performed at the nodes of the binary tree is an integer division by a proper power of 2, that is implemented by a novel circuit. The developed ADC system is an asynchronous circuit operating in current mode needing only a small number of components. This fact in conjunction with the binary tree structure of the ADC architecture, lead to implementations with very low die area and power consumption (0.12mm2 and 72mW respectively for 12-bit resolution). The average sampling rate exceeds 140MS/s for 12-bit resolution. The proposed device can also be used in multi Gbps time-interleaved parallel ADC due to its very low die area and power consumption.

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Research paper thumbnail of An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division

2010 IEEE Computer Society Annual Symposium on VLSI, 2010

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Research paper thumbnail of Selecting appropriate calibration points for an ultra low area 8-bit subrange ADC

2010 8th Workshop on Intelligent Solutions in Embedded Systems, 2010

An ultra low area 8-bit subrange Analogue/Digital Converter that consists of a pair of Flash 4-bi... more An ultra low area 8-bit subrange Analogue/Digital Converter that consists of a pair of Flash 4-bit converter stages is described in this paper emphasising on the appropriate method for its real time calibration. Its active area occupies only 0.04 mm2 and dissipates less than 22 mW. The sampling rate is higher than 500 MS/s and the achieved Signal to Noise

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Research paper thumbnail of Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm<sup>2</sup> ADC with binary tree structure

2009 IEEE Conference on Emerging Technologies & Factory Automation, 2009

A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bi... more A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bits resolution, using a binary tree structure is presented which needs very low silicon area and relatively low power consumption for its implementation. The sampling rate of the 12-bit ADC exceeds 140MS/s and requires only 0.12 mm2 of area making it appropriate for ultra wideband

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Research paper thumbnail of The use of electronic equalization and offset filtering in the performance improvement of low-cost DML transmitters

2008 10th Anniversary International Conference on Transparent Optical Networks, 2008

Abstract The use of electronic compensation techniques for the transmission improvement of low-co... more Abstract The use of electronic compensation techniques for the transmission improvement of low-cost directly modulated sources is studied and evaluated experimentally. More specifically the research efforts presented here targeting in enhancing the transmission reach of common DML sources with limited bandwidth fabricated for operation at 2.5 Gb/s, but operated at 10 Gb/s. Performance improvement is achieved by means of electronic feed-forward and decision-feedback equalization (FFE/DFE) as well as off-set optical filtering at ...

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Research paper thumbnail of A voltage mode integer divider for fast A/D Conversion

2010 IEEE International Symposium on Industrial Electronics, 2010

Abstract-An analog circuit capable of implementing an integer division by a constant number is pr... more Abstract-An analog circuit capable of implementing an integer division by a constant number is presented in this paper. The quotient and the residue of the division are generated concurrently by a circuit operating in voltage mode that can be used in various A/D Conversion (ADC) ...

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