Nishant Patil - Academia.edu (original) (raw)
Papers by Nishant Patil
IEEE Transactions on Electron Devices, 2009
We demonstrate ACCNT (pronounced as "accent"), a solution to the metallic-nanotube problem that d... more We demonstrate ACCNT (pronounced as "accent"), a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallicnanotube tolerance, delivering high ON-OFF ratios (10 4 −10 6 ) while preserving the current drive. In addition, this metallicnanotube tolerance can be engineered arbitrarily close to 100%. We present the ACCNT concepts in detail, verifying the concepts and underlying assumptions via experimental results. We further demonstrate inverters using ACCNT and ACCNT scalability to a wafer scale. ACCNT marks the first demonstration of a VLSIcompatible metallic-nanotube-tolerant design methodology.
By surmounting various obstacles across the spectrum from material synthesis to device fabricatio... more By surmounting various obstacles across the spectrum from material synthesis to device fabrication and circuit considerations, we provide a solid foundation so that carbon-based technology can move forward towards the vision of engineering VLSI circuits, but further research is still needed to realize the material potential such as higher density CNT synthesis, better metal to CNT/graphene contacts, and air-stable doping of CNT.
... SPICE models, based on ballistic transport theory, enable circuit-level simulation for circui... more ... SPICE models, based on ballistic transport theory, enable circuit-level simulation for circuit design and analysis. ... Figure 4. (a) Monolithic 3D-ICs using CNFETs and CNT interconnects [Wei 09b], (b) Pass-transistor ... Avouris 07] Avouris, P., et al., “Carbon-based electronics,” Nature ...
IEEE Transactions on Electron Devices, 2010
We present analyses for ACCNT (pronounced as "accent"), which is a solution to the metallic-nanot... more We present analyses for ACCNT (pronounced as "accent"), which is a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high ON-OFF ratios while preserving current drive. We analyze the ACCNT methodology in terms of its tradeoffs and explore optimizations that may serve as future design guidelines. We also investigate circuit-level considerations and the impact of density variation on the ACCNT design. We find that ACCNT can improve the yield of a one-million transistor chip from 0% (conventional CNT design) up to 99% at a cost of 3.3× area overhead if the fraction of semiconducting CNTs is improved to 99.9%.
Carbon Nanotubes (CNTs) are grown using chemical selfassembly. As a result, it is extremely diffi... more Carbon Nanotubes (CNTs) are grown using chemical selfassembly. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of Carbon Nanotube Field Effect Transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variation is presented based on experimental data extracted from aligned CNT growth. This model is used to quantify the impact of such variations on design metrics such as noise margins and delay variations of CNFET circuits. Finally, we analyze correlation that exists in aligned CNT growth, and demonstrate how the reliability of CNFET circuits can be significantly improved by taking advantage of such correlation.
Journal of Physical Chemistry C, 2009
... The growth of long aligned carbon nanotubes (CNTs) on arbitrary wafer sizes is highly desirab... more ... The growth of long aligned carbon nanotubes (CNTs) on arbitrary wafer sizes is highly desirable for large-scale integrated sensors and nanoelectronics.(1-3) While there exists some methods to align CNTs in situ during growth, the most attractive in terms of alignment accuracy ...
Applied Physics Letters, 2008
In this paper, high-performance back-gated carbon nanotube field-effect transistors based on tran... more In this paper, high-performance back-gated carbon nanotube field-effect transistors based on transferred aligned carbon nanotubes were fabricated and studies found that the on/off ratio can reach 107 and the current density can reach 1.6μA/μm after electrical breakdown. In addition, chemical doping with hydrazine was used to convert the p-type aligned nanotube devices into n-type. These devices were further utilized to demonstrate various logic circuits, including p-type metal-oxide-semiconductor inverters, diode-loaded inverters, complementary metal-oxide-semiconductor inverters, NAND, and NOR gates. This approach could work as the platform for future nanotube-based nanoelectronics.
Carbon nanotube field-effect transistors (CNFETs) show big promise as extensions to silicon-CMOS ... more Carbon nanotube field-effect transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits over silicon-CMOS, and 2) CNFET processing is compatible with existing silicon-CMOS processing. However, future gigascale systems cannot rely solely on existing chemical synthesis for guaranteed ideal devices. VLSI-scale logic circuits using CNFETs must overcome major challenges posed by: 1) Misaligned and mis-positioned Carbon Nanotubes (CNTs); 2) Metallic CNTs; and, 3) CNT density variations. This paper performs detailed analysis of the impact of these challenges on CNFET circuit performance. A combination of design and processing techniques, presented this paper, can enable VLSI-scale CNFET logic circuits that are immune to high rates of inherent imperfections. These techniques are inexpensive compared to traditional defect- and fault-tolerance, do not impose major changes in VLSI design flows, and are compatible with VLSI processing because they do not require special customization on chip-by-chip basis.
Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silic... more Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS due to excellent CV/I device performance. An ideal CNFET inverter fabricated using a perfect CNFET technology can have 5.1 times faster FO4 delay and 2.6 times lower energy per cycle compared to a 32nm Silicon CMOS inverter. Two fundamental challenges prevent us from creating CNFET-based logic designs with the advantages quoted above: 1. Misaligned Carbon Nanotubes (CNTs), and 2. Metallic CNTs. Misaligned CNTs can result in incorrect logic function implementations. This paper presents a technique for designing CNFET-based arbitrary logic functions that are guaranteed to be correct even in the presence of a large number of misaligned CNTs.
Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Trans... more Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs) resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of 103-105, and overcomes the limitations of existing metallic-CNT removal techniques. VMR enables first experimental demonstration of complex cascaded CNFET logic circuits. Such logic circuits are immune to both mis-positioned and metallic CNTs.
Acs Nano, 2009
Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that a... more Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that are directly integrated as thin-film transistors or conductive sheets may enable many new device structures. Applications ranging from disposable autonomous sensors to flexible, large-area displays and solar cells can dramatically expand the electronics market. With a practical, reliable method for controlling their electronic properties through solution assembly, submonolayer films of aligned single-walled carbon nanotubes (SWNTs) may provide a promising alternative for large-area, flexible electronics. Here, we report SWNT network TFTs (SWNTntTFTs) deposited from solution with controllable topology, on/off ratios averaging greater than 10(5), and an apparent mobility averaging 2 cm(2)/V.s, without any pre- or postprocessing steps. We employ a spin-assembly technique that results in chirality enrichment along with tunable alignment and density of the SWNTs by balancing the hydrodynamic force (spin rate) with the surface interaction force controlled by a chemically functionalized interface. This directed nanoscale assembly results in enriched semiconducting nanotubes yielding excellent TFT characteristics, which is corroborated with mu-Raman spectroscopy. Importantly, insight into the electronic properties of these SWNT networks as a function of topology is obtained.
IEEE Transactions on Nanotechnology, 2009
AbstractExperimental demonstration of wafer-scale growth of well-aligned, dense, single-walled c... more AbstractExperimental demonstration of wafer-scale growth of well-aligned, dense, single-walled carbon nanotubes on 4 ST-cut quartz wafers is presented. We developed a new carbon nan-otube (CNT) wafer-scale growth process. This process allows quartz wafers to be ...
IEEE Design & Test of Computers, 2005
DIGITAL CIRCUIT TESTING involves applying test patterns and observing the circuit's resp... more DIGITAL CIRCUIT TESTING involves applying test patterns and observing the circuit's responses to the applied patterns. The tester compares the observed response to a test pattern with the expected response and declares a chip defective upon mismatch. Test engineers usually ...
Nano Letters, 2009
Massive aligned carbon nanotubes hold great potential but also face significant integration/assem... more Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2008
AbstractCarbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to sili... more AbstractCarbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. ...
Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-dela... more Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-delay-product benefits compared to silicon CMOS. However, CNFET circuits are subject to several sources of imperfections. These imperfections lead to incorrect logic functionality and substantial circuit performance variations. Processing techniques alone are inadequate to overcome the challenges resulting from these imperfections. An imperfection-immune design methodology is required. We present an overview of imperfection-immune design techniques to overcome two major sources of CNFET imperfections: metallic Carbon Nanotubes (CNTs) and CNT density variations.
1 Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions Nishant Pa... more 1 Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions Nishant Patil, Albert Lin, Jie Zhang, H.S. Philip Wong, Subhasish Mitra Department of Electrical Engineering and Department of Computer Science Stanford University, Stanford, CA ...
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2012
Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly en... more Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.
IEEE Transactions on Nanotechnology, 2009
In this paper, we demonstrate postprocessing techniques to adjust the threshold voltage (V t ) an... more In this paper, we demonstrate postprocessing techniques to adjust the threshold voltage (V t ) and on-off ratio (I ON /I OFF ) of multiple-tube carbon nanotube field effect transistors (CNFETs). These postprocessing techniques open up an additional degree of freedom to further tune individual CNFETs in addition to various device synthesis and processing techniques. We demonstrate proof-of-concept experiments and fully characterize their design spaces and tradeoffs. The techniques, Threshold Voltage Setting and On-Off Ratio Tuning, were able to adjust the threshold by as much as 2 V and tune the on-off ratio across 5 × 10 3 to 5 × 10 5 . In addition, V t Setting could be used as an analysis tool to infer the V t distribution of grown carbon nanotubes (CNTs). These tuning techniques, combined with processes such as doping, will enable high-performance multiple-nanotube devices.
1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-... more 1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-delay product improvement over 32nm node Si CMOS (including diameter and doping variations), provided circuits can be built that are immune to misaligned and metallic nanotubes. A design technique that guarantees correct logic operation in the presence of misaligned nanotubes is also presented.
IEEE Transactions on Electron Devices, 2009
We demonstrate ACCNT (pronounced as "accent"), a solution to the metallic-nanotube problem that d... more We demonstrate ACCNT (pronounced as "accent"), a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallicnanotube tolerance, delivering high ON-OFF ratios (10 4 −10 6 ) while preserving the current drive. In addition, this metallicnanotube tolerance can be engineered arbitrarily close to 100%. We present the ACCNT concepts in detail, verifying the concepts and underlying assumptions via experimental results. We further demonstrate inverters using ACCNT and ACCNT scalability to a wafer scale. ACCNT marks the first demonstration of a VLSIcompatible metallic-nanotube-tolerant design methodology.
By surmounting various obstacles across the spectrum from material synthesis to device fabricatio... more By surmounting various obstacles across the spectrum from material synthesis to device fabrication and circuit considerations, we provide a solid foundation so that carbon-based technology can move forward towards the vision of engineering VLSI circuits, but further research is still needed to realize the material potential such as higher density CNT synthesis, better metal to CNT/graphene contacts, and air-stable doping of CNT.
... SPICE models, based on ballistic transport theory, enable circuit-level simulation for circui... more ... SPICE models, based on ballistic transport theory, enable circuit-level simulation for circuit design and analysis. ... Figure 4. (a) Monolithic 3D-ICs using CNFETs and CNT interconnects [Wei 09b], (b) Pass-transistor ... Avouris 07] Avouris, P., et al., “Carbon-based electronics,” Nature ...
IEEE Transactions on Electron Devices, 2010
We present analyses for ACCNT (pronounced as "accent"), which is a solution to the metallic-nanot... more We present analyses for ACCNT (pronounced as "accent"), which is a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high ON-OFF ratios while preserving current drive. We analyze the ACCNT methodology in terms of its tradeoffs and explore optimizations that may serve as future design guidelines. We also investigate circuit-level considerations and the impact of density variation on the ACCNT design. We find that ACCNT can improve the yield of a one-million transistor chip from 0% (conventional CNT design) up to 99% at a cost of 3.3× area overhead if the fraction of semiconducting CNTs is improved to 99.9%.
Carbon Nanotubes (CNTs) are grown using chemical selfassembly. As a result, it is extremely diffi... more Carbon Nanotubes (CNTs) are grown using chemical selfassembly. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of Carbon Nanotube Field Effect Transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variation is presented based on experimental data extracted from aligned CNT growth. This model is used to quantify the impact of such variations on design metrics such as noise margins and delay variations of CNFET circuits. Finally, we analyze correlation that exists in aligned CNT growth, and demonstrate how the reliability of CNFET circuits can be significantly improved by taking advantage of such correlation.
Journal of Physical Chemistry C, 2009
... The growth of long aligned carbon nanotubes (CNTs) on arbitrary wafer sizes is highly desirab... more ... The growth of long aligned carbon nanotubes (CNTs) on arbitrary wafer sizes is highly desirable for large-scale integrated sensors and nanoelectronics.(1-3) While there exists some methods to align CNTs in situ during growth, the most attractive in terms of alignment accuracy ...
Applied Physics Letters, 2008
In this paper, high-performance back-gated carbon nanotube field-effect transistors based on tran... more In this paper, high-performance back-gated carbon nanotube field-effect transistors based on transferred aligned carbon nanotubes were fabricated and studies found that the on/off ratio can reach 107 and the current density can reach 1.6μA/μm after electrical breakdown. In addition, chemical doping with hydrazine was used to convert the p-type aligned nanotube devices into n-type. These devices were further utilized to demonstrate various logic circuits, including p-type metal-oxide-semiconductor inverters, diode-loaded inverters, complementary metal-oxide-semiconductor inverters, NAND, and NOR gates. This approach could work as the platform for future nanotube-based nanoelectronics.
Carbon nanotube field-effect transistors (CNFETs) show big promise as extensions to silicon-CMOS ... more Carbon nanotube field-effect transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits over silicon-CMOS, and 2) CNFET processing is compatible with existing silicon-CMOS processing. However, future gigascale systems cannot rely solely on existing chemical synthesis for guaranteed ideal devices. VLSI-scale logic circuits using CNFETs must overcome major challenges posed by: 1) Misaligned and mis-positioned Carbon Nanotubes (CNTs); 2) Metallic CNTs; and, 3) CNT density variations. This paper performs detailed analysis of the impact of these challenges on CNFET circuit performance. A combination of design and processing techniques, presented this paper, can enable VLSI-scale CNFET logic circuits that are immune to high rates of inherent imperfections. These techniques are inexpensive compared to traditional defect- and fault-tolerance, do not impose major changes in VLSI design flows, and are compatible with VLSI processing because they do not require special customization on chip-by-chip basis.
Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silic... more Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS due to excellent CV/I device performance. An ideal CNFET inverter fabricated using a perfect CNFET technology can have 5.1 times faster FO4 delay and 2.6 times lower energy per cycle compared to a 32nm Silicon CMOS inverter. Two fundamental challenges prevent us from creating CNFET-based logic designs with the advantages quoted above: 1. Misaligned Carbon Nanotubes (CNTs), and 2. Metallic CNTs. Misaligned CNTs can result in incorrect logic function implementations. This paper presents a technique for designing CNFET-based arbitrary logic functions that are guaranteed to be correct even in the presence of a large number of misaligned CNTs.
Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Trans... more Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs) resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of 103-105, and overcomes the limitations of existing metallic-CNT removal techniques. VMR enables first experimental demonstration of complex cascaded CNFET logic circuits. Such logic circuits are immune to both mis-positioned and metallic CNTs.
Acs Nano, 2009
Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that a... more Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that are directly integrated as thin-film transistors or conductive sheets may enable many new device structures. Applications ranging from disposable autonomous sensors to flexible, large-area displays and solar cells can dramatically expand the electronics market. With a practical, reliable method for controlling their electronic properties through solution assembly, submonolayer films of aligned single-walled carbon nanotubes (SWNTs) may provide a promising alternative for large-area, flexible electronics. Here, we report SWNT network TFTs (SWNTntTFTs) deposited from solution with controllable topology, on/off ratios averaging greater than 10(5), and an apparent mobility averaging 2 cm(2)/V.s, without any pre- or postprocessing steps. We employ a spin-assembly technique that results in chirality enrichment along with tunable alignment and density of the SWNTs by balancing the hydrodynamic force (spin rate) with the surface interaction force controlled by a chemically functionalized interface. This directed nanoscale assembly results in enriched semiconducting nanotubes yielding excellent TFT characteristics, which is corroborated with mu-Raman spectroscopy. Importantly, insight into the electronic properties of these SWNT networks as a function of topology is obtained.
IEEE Transactions on Nanotechnology, 2009
AbstractExperimental demonstration of wafer-scale growth of well-aligned, dense, single-walled c... more AbstractExperimental demonstration of wafer-scale growth of well-aligned, dense, single-walled carbon nanotubes on 4 ST-cut quartz wafers is presented. We developed a new carbon nan-otube (CNT) wafer-scale growth process. This process allows quartz wafers to be ...
IEEE Design & Test of Computers, 2005
DIGITAL CIRCUIT TESTING involves applying test patterns and observing the circuit's resp... more DIGITAL CIRCUIT TESTING involves applying test patterns and observing the circuit's responses to the applied patterns. The tester compares the observed response to a test pattern with the expected response and declares a chip defective upon mismatch. Test engineers usually ...
Nano Letters, 2009
Massive aligned carbon nanotubes hold great potential but also face significant integration/assem... more Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2008
AbstractCarbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to sili... more AbstractCarbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. ...
Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-dela... more Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-delay-product benefits compared to silicon CMOS. However, CNFET circuits are subject to several sources of imperfections. These imperfections lead to incorrect logic functionality and substantial circuit performance variations. Processing techniques alone are inadequate to overcome the challenges resulting from these imperfections. An imperfection-immune design methodology is required. We present an overview of imperfection-immune design techniques to overcome two major sources of CNFET imperfections: metallic Carbon Nanotubes (CNTs) and CNT density variations.
1 Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions Nishant Pa... more 1 Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions Nishant Patil, Albert Lin, Jie Zhang, H.S. Philip Wong, Subhasish Mitra Department of Electrical Engineering and Department of Computer Science Stanford University, Stanford, CA ...
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2012
Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly en... more Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.
IEEE Transactions on Nanotechnology, 2009
In this paper, we demonstrate postprocessing techniques to adjust the threshold voltage (V t ) an... more In this paper, we demonstrate postprocessing techniques to adjust the threshold voltage (V t ) and on-off ratio (I ON /I OFF ) of multiple-tube carbon nanotube field effect transistors (CNFETs). These postprocessing techniques open up an additional degree of freedom to further tune individual CNFETs in addition to various device synthesis and processing techniques. We demonstrate proof-of-concept experiments and fully characterize their design spaces and tradeoffs. The techniques, Threshold Voltage Setting and On-Off Ratio Tuning, were able to adjust the threshold by as much as 2 V and tune the on-off ratio across 5 × 10 3 to 5 × 10 5 . In addition, V t Setting could be used as an analysis tool to infer the V t distribution of grown carbon nanotubes (CNTs). These tuning techniques, combined with processes such as doping, will enable high-performance multiple-nanotube devices.
1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-... more 1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-delay product improvement over 32nm node Si CMOS (including diameter and doping variations), provided circuits can be built that are immune to misaligned and metallic nanotubes. A design technique that guarantees correct logic operation in the presence of misaligned nanotubes is also presented.