Salvador Mir - Academia.edu (original) (raw)

Papers by Salvador Mir

Research paper thumbnail of Capteur MEMS faible impédance mécanique haute sensibilité pour la chirurgie de l'oreille moyenne

ABSTRACT En chirurgie reconstructrice de l'oreille moyenne, le positionnement des osselet... more ABSTRACT En chirurgie reconstructrice de l'oreille moyenne, le positionnement des osselets permet d'optimiser la transmission du son entre le tympan et l'oreille interne. La sonde permet de mesurer le déplacement des osselets et la transmission de la chaîne de l'oreille moyenne afin de juger instantanément du bon positionnement d'un osselet

Research paper thumbnail of Diagnosis in Linear and Nonlinear Mixed-Signal Systems: a Parameter Identification Based Technique

HAL (Le Centre pour la Communication Scientifique Directe), 2005

In this paper, we consider the nonlinear system modelling problem for on-chip testing and diagnos... more In this paper, we consider the nonlinear system modelling problem for on-chip testing and diagnosis of embedded mixed-signal systems. A Situation-Dependent AutoRegressive model with eXogenous variable (SDARX) is introduced to approximate the conventional Nonlinear-ARX (NARX). The parameter search space is divided into a linear weight subspace and the nonlinear parameter subspace. A nonlinear parameter estimation strategy combines the Levenberg-Marquardt method (LMM) for nonlinear parameter optimization and the leastsquare method (LSM) for linear parameter estimation. The diagnosis procedure requires a recursive estimation of the model parameters corresponding to the nominal behaviour, using input-output data recorded on the system under test. Emphasis is given to the characterisation of a particular failure mode by choosing the best model structure and identification of model parameters for diagnostic purposes. For fault identification, the parameter estimation technique is associated with the fault dictionary approach.

Research paper thumbnail of Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

This work presents reduced-code strategies for the static linearity test of successive-approximat... more This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.

Research paper thumbnail of Evaluation of Analog/RF Test Measurements at the Design Stage

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Apr 1, 2009

We present a method that is capable of handling process variations to evaluate analog/RF test mea... more We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides

Research paper thumbnail of Proceedings on 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC'06)

HAL (Le Centre pour la Communication Scientifique Directe), 2006

ISBN : 3-901882-19-

Research paper thumbnail of Design and test of MEMS

This paper deals with design, simulation and test of MEMS (microelectromechanical systems). Both ... more This paper deals with design, simulation and test of MEMS (microelectromechanical systems). Both existing tools and open research areas are addressed. An appropriate Computer-Aided Design (CAD) environment is presented. Similarities between the present development of MEMS and the development of microelectronics decades ago are pointed out, including the migration from point tools to CAD frameworks, testing and intellectual property (IP)

Research paper thumbnail of Design of high-performance band-pass sigma-delta modulator with concurrent error detection

This paper presents the design of a band-pass sigma-delta modulator to be used in digital radio s... more This paper presents the design of a band-pass sigma-delta modulator to be used in digital radio systems. The proposed circuit exploits the advantages provided by sigma-delta technique and by fully differential architecture. Band-pass sigma-delta conversion requires a very simple digital demodulation circuit. Oversampling and noise-shaping techniques provide a way to realize A/D converters with medium/high resolution without requiring high-precision analog

Research paper thumbnail of CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization

Springer eBooks, Nov 21, 2007

This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation o... more This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations, as a trade-off between estimated test metrics at the design stage. Specification-based tests are next optimized in terms of their capability of detecting catastrophic and parametric faults.

Research paper thumbnail of Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems

Silicon-compatible micromachining provides a low cost monolithic solution for the integration of ... more Silicon-compatible micromachining provides a low cost monolithic solution for the integration of microelectromechanical systems (MEMS). In the last years, CMP (the French MultiProject Wafer Service) has made available technological solutions for the fabrication of CMOS-compatible MEMS. Numerous monolithic devices have been fabricated using this service. The inspection of failed devices has allowed the identification of the most typical failure mechanisms

Research paper thumbnail of RF transceiver parameter identification using regressive models

In this paper, we consider the nonlinear system modelling problem for on-chip testing of embedded... more In this paper, we consider the nonlinear system modelling problem for on-chip testing of embedded mixed-signal systems. Behavioural modelling is proposed to characterize RF transceiver, in terms of input and output signals using simplified mathematical expressions. A Situation-Dependent AutoRegressive model with exogenous variable (SDARX) is introduced to approximate the conventional Nonlinear-ARX (NARX). The parameter search space is divided into a

Research paper thumbnail of Extending fault-based testing to microelectromechanical systems

As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research effort... more As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research efforts shift towards the design of systems of increasing complexity. The ways in which testing is going to be performed for large volume complex devices embedding MEMS are not known. As in the microelectronics industry, the development of cost-effective tests for larger systems may well require test stimuli targeting actual faults, developing fault lists and fault models for realistic manufacturing defects and failure modes, and using fault simulation as a major approach for assessing testability and dependability. In this paper, we illustrate how fault-based testing can be extended to MEMS, both for bulk and surface micromachining technologies, making possible the reuse of analog testing techniques.

Research paper thumbnail of Unified built-in self-test for fully differential analog circuits

Journal of Electronic Testing, 1996

ABSTRACT The reduction of test costs, especially in high safety systems, requires that the same t... more ABSTRACT The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.

Research paper thumbnail of Diagnostic de fautes de circuits analogiques basé sur l'estimation non paramétrique de densité

HAL (Le Centre pour la Communication Scientifique Directe), Jun 15, 2011

ABSTRACT

Research paper thumbnail of A versatile technique for evaluating test measurements at the design stage

HAL (Le Centre pour la Communication Scientifique Directe), Jun 10, 2009

International audienc

Research paper thumbnail of A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology

This work presents the design, integration and experimental validation of an on-chip sinusoidal s... more This work presents the design, integration and experimental validation of an on-chip sinusoidal signal generator for analog and mixed signal Built-In Self-Test applications. The integrated generator is based on a calibrated harmonic cancellation strategy, previously presented by the authors, that consists in combining five digital square-waves with appropriate phase-shifts and scale weights. The generator employs a digital shift-register to provide a set of phase-shifted digital squarewave signals. These square-wave signals are then scaled and combined using controlled current sources. The proof-of-concept prototype of the sinusoidal signal generator was integrated in STMicroelectronics 28 nm FDSOI technology and characterized in the laboratory to validate the feasibility of the proposal. Obtained results show a performance of 52 dB of SFDR for a generated sinusoidal signal at 166.67 MHz. The generator was tested in an operation frequency range from 1 MHz to 333 MHz.

Research paper thumbnail of Fault diagnosis of analog circuits based on machine learning

Research paper thumbnail of Diagnosis of Local Spot Defects in Analog Circuits

IEEE Transactions on Instrumentation and Measurement, Oct 1, 2012

We present a method for diagnosing local spot defects in analog circuits. The method aims to iden... more We present a method for diagnosing local spot defects in analog circuits. The method aims to identify a subset of defects that are likely to have occurred and suggests to give them priority in a classical failure analysis. For this purpose, the method relies on a combination of multiclass classifiers that are trained using data from fault simulation. The method is demonstrated on an industrial large-scale case study. The device under consideration is a controller area network transceiver used in automobile systems. This device demands high-quality control due to the reliability requirements of the application wherein it is deployed. The diagnosis problem is discussed by taking into consideration the realities of this case study.

Research paper thumbnail of Convertisseur analogique-numérique sigma-delta muni d'un circuit de test

HAL (Le Centre pour la Communication Scientifique Directe), Jun 30, 2010

Research paper thumbnail of UTBB FD-SOI Technology for Silicon-based Quantum Dots and Cryo-CMOS Electronics

HAL (Le Centre pour la Communication Scientifique Directe), Oct 14, 2019

International audienc

Research paper thumbnail of Session details: Testing and diagnosis of analogue and mixed-signal circuits

Design, Automation, and Test in Europe, Mar 8, 2010

Research paper thumbnail of Capteur MEMS faible impédance mécanique haute sensibilité pour la chirurgie de l'oreille moyenne

ABSTRACT En chirurgie reconstructrice de l'oreille moyenne, le positionnement des osselet... more ABSTRACT En chirurgie reconstructrice de l'oreille moyenne, le positionnement des osselets permet d'optimiser la transmission du son entre le tympan et l'oreille interne. La sonde permet de mesurer le déplacement des osselets et la transmission de la chaîne de l'oreille moyenne afin de juger instantanément du bon positionnement d'un osselet

Research paper thumbnail of Diagnosis in Linear and Nonlinear Mixed-Signal Systems: a Parameter Identification Based Technique

HAL (Le Centre pour la Communication Scientifique Directe), 2005

In this paper, we consider the nonlinear system modelling problem for on-chip testing and diagnos... more In this paper, we consider the nonlinear system modelling problem for on-chip testing and diagnosis of embedded mixed-signal systems. A Situation-Dependent AutoRegressive model with eXogenous variable (SDARX) is introduced to approximate the conventional Nonlinear-ARX (NARX). The parameter search space is divided into a linear weight subspace and the nonlinear parameter subspace. A nonlinear parameter estimation strategy combines the Levenberg-Marquardt method (LMM) for nonlinear parameter optimization and the leastsquare method (LSM) for linear parameter estimation. The diagnosis procedure requires a recursive estimation of the model parameters corresponding to the nominal behaviour, using input-output data recorded on the system under test. Emphasis is given to the characterisation of a particular failure mode by choosing the best model structure and identification of model parameters for diagnostic purposes. For fault identification, the parameter estimation technique is associated with the fault dictionary approach.

Research paper thumbnail of Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

This work presents reduced-code strategies for the static linearity test of successive-approximat... more This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.

Research paper thumbnail of Evaluation of Analog/RF Test Measurements at the Design Stage

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Apr 1, 2009

We present a method that is capable of handling process variations to evaluate analog/RF test mea... more We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides

Research paper thumbnail of Proceedings on 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC'06)

HAL (Le Centre pour la Communication Scientifique Directe), 2006

ISBN : 3-901882-19-

Research paper thumbnail of Design and test of MEMS

This paper deals with design, simulation and test of MEMS (microelectromechanical systems). Both ... more This paper deals with design, simulation and test of MEMS (microelectromechanical systems). Both existing tools and open research areas are addressed. An appropriate Computer-Aided Design (CAD) environment is presented. Similarities between the present development of MEMS and the development of microelectronics decades ago are pointed out, including the migration from point tools to CAD frameworks, testing and intellectual property (IP)

Research paper thumbnail of Design of high-performance band-pass sigma-delta modulator with concurrent error detection

This paper presents the design of a band-pass sigma-delta modulator to be used in digital radio s... more This paper presents the design of a band-pass sigma-delta modulator to be used in digital radio systems. The proposed circuit exploits the advantages provided by sigma-delta technique and by fully differential architecture. Band-pass sigma-delta conversion requires a very simple digital demodulation circuit. Oversampling and noise-shaping techniques provide a way to realize A/D converters with medium/high resolution without requiring high-precision analog

Research paper thumbnail of CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization

Springer eBooks, Nov 21, 2007

This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation o... more This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations, as a trade-off between estimated test metrics at the design stage. Specification-based tests are next optimized in terms of their capability of detecting catastrophic and parametric faults.

Research paper thumbnail of Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems

Silicon-compatible micromachining provides a low cost monolithic solution for the integration of ... more Silicon-compatible micromachining provides a low cost monolithic solution for the integration of microelectromechanical systems (MEMS). In the last years, CMP (the French MultiProject Wafer Service) has made available technological solutions for the fabrication of CMOS-compatible MEMS. Numerous monolithic devices have been fabricated using this service. The inspection of failed devices has allowed the identification of the most typical failure mechanisms

Research paper thumbnail of RF transceiver parameter identification using regressive models

In this paper, we consider the nonlinear system modelling problem for on-chip testing of embedded... more In this paper, we consider the nonlinear system modelling problem for on-chip testing of embedded mixed-signal systems. Behavioural modelling is proposed to characterize RF transceiver, in terms of input and output signals using simplified mathematical expressions. A Situation-Dependent AutoRegressive model with exogenous variable (SDARX) is introduced to approximate the conventional Nonlinear-ARX (NARX). The parameter search space is divided into a

Research paper thumbnail of Extending fault-based testing to microelectromechanical systems

As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research effort... more As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research efforts shift towards the design of systems of increasing complexity. The ways in which testing is going to be performed for large volume complex devices embedding MEMS are not known. As in the microelectronics industry, the development of cost-effective tests for larger systems may well require test stimuli targeting actual faults, developing fault lists and fault models for realistic manufacturing defects and failure modes, and using fault simulation as a major approach for assessing testability and dependability. In this paper, we illustrate how fault-based testing can be extended to MEMS, both for bulk and surface micromachining technologies, making possible the reuse of analog testing techniques.

Research paper thumbnail of Unified built-in self-test for fully differential analog circuits

Journal of Electronic Testing, 1996

ABSTRACT The reduction of test costs, especially in high safety systems, requires that the same t... more ABSTRACT The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.

Research paper thumbnail of Diagnostic de fautes de circuits analogiques basé sur l'estimation non paramétrique de densité

HAL (Le Centre pour la Communication Scientifique Directe), Jun 15, 2011

ABSTRACT

Research paper thumbnail of A versatile technique for evaluating test measurements at the design stage

HAL (Le Centre pour la Communication Scientifique Directe), Jun 10, 2009

International audienc

Research paper thumbnail of A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology

This work presents the design, integration and experimental validation of an on-chip sinusoidal s... more This work presents the design, integration and experimental validation of an on-chip sinusoidal signal generator for analog and mixed signal Built-In Self-Test applications. The integrated generator is based on a calibrated harmonic cancellation strategy, previously presented by the authors, that consists in combining five digital square-waves with appropriate phase-shifts and scale weights. The generator employs a digital shift-register to provide a set of phase-shifted digital squarewave signals. These square-wave signals are then scaled and combined using controlled current sources. The proof-of-concept prototype of the sinusoidal signal generator was integrated in STMicroelectronics 28 nm FDSOI technology and characterized in the laboratory to validate the feasibility of the proposal. Obtained results show a performance of 52 dB of SFDR for a generated sinusoidal signal at 166.67 MHz. The generator was tested in an operation frequency range from 1 MHz to 333 MHz.

Research paper thumbnail of Fault diagnosis of analog circuits based on machine learning

Research paper thumbnail of Diagnosis of Local Spot Defects in Analog Circuits

IEEE Transactions on Instrumentation and Measurement, Oct 1, 2012

We present a method for diagnosing local spot defects in analog circuits. The method aims to iden... more We present a method for diagnosing local spot defects in analog circuits. The method aims to identify a subset of defects that are likely to have occurred and suggests to give them priority in a classical failure analysis. For this purpose, the method relies on a combination of multiclass classifiers that are trained using data from fault simulation. The method is demonstrated on an industrial large-scale case study. The device under consideration is a controller area network transceiver used in automobile systems. This device demands high-quality control due to the reliability requirements of the application wherein it is deployed. The diagnosis problem is discussed by taking into consideration the realities of this case study.

Research paper thumbnail of Convertisseur analogique-numérique sigma-delta muni d'un circuit de test

HAL (Le Centre pour la Communication Scientifique Directe), Jun 30, 2010

Research paper thumbnail of UTBB FD-SOI Technology for Silicon-based Quantum Dots and Cryo-CMOS Electronics

HAL (Le Centre pour la Communication Scientifique Directe), Oct 14, 2019

International audienc

Research paper thumbnail of Session details: Testing and diagnosis of analogue and mixed-signal circuits

Design, Automation, and Test in Europe, Mar 8, 2010