Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs (original) (raw)

Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental <inline-formula> <tex-math notation="LaTeX">$\Sigma\Delta$ </tex-math> </inline-formula> Converter

Salvador Mir

IEEE Transactions on Device and Materials Reliability, 2019

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On-chip reduced-code static linearity test of VcmV_{cm}Vcm -based switching SAR ADCs using an incremental analog-to-digital converter

Salvador Mir

2020

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Static linearity BIST for VcmV_{cm}Vcm-based switching SAR ADCs using a reduced-code measurement technique

Salvador Mir

2020

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Design for Testability That Reduces Linearity Testing Time of SAR ADCs

Haruo Kobayashi

IEICE Transactions on Electronics, 2011

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DESIGN AND IMPLEMENTATION OF HIGH SPEED SPLIT SAR ADCs WITH IMPROVED LINEARITY

Florence Nishmitha

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A Self-Testing Platform with a Foreground Digital Calibration Technique for SAR ADCs

Shuenn Yuh Lee

Applied Sciences, 2016

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Linearity testing of precision analog-to-digital converters using stationary nonlinear inputs

Randall L Geiger

International Test Conference, 2003. Proceedings. ITC 2003.

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Behavioral model of split capacitor array DAC for use in SAR ADC design

Adarsha Adarsh

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Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

Salvador Mir

IEEE Transactions on Circuits and Systems I: Regular Papers, 2015

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High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy

Randall L Geiger

IEEE Transactions on Instrumentation and Measurement, 2009

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An Efficient Tool for the Assisted Design of SAR ADCs Capacitive DACs

Andrea Bonfanti

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A time efficient method for determination of static non-linearities of high-speed high-resolution ADCs

Santosh Vora

Measurement, 2005

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A fully digital-compatible BIST strategy for ADC linearity testing

Randall L Geiger

2007 IEEE International Test Conference, 2007

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A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

Salvador Mir

Journal of Electronic Testing, 2016

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PAPER Special Section on Analog Circuit Techniques and Related Topics SAR ADC Algorithm with Redundancy and Digital Error Correction

Tcg Wu

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An efficient threshold voltage generation for SAR ADCs

mahdiye khoshakhlagh

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Non-binary digital calibration for split-capacitor DAC in SAR ADC

Guo Dongdong

IEICE Electronics Express, 2015

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Testing High-Resolution ADCs With Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACs

Randall L Geiger

IEEE Transactions on Instrumentation and Measurement, 2007

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Implementation of a digital trim scheme for SAR ADCs

Georg Fischer

Advances in Radio Science, 2013

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A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture

M.S. Bhat

Sādhanā, 2019

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Analysis of Passive Charge Sharing-Based Segmented SAR ADCs

Richard Shi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020

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High Linearity SAR ADC for High Performance Sensor System

hadi heidari

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018

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Analysis and optimization of a SAR ADC with Attenuation Capacitor

Andrea Bonfanti

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A Maximum Likelihood Estimator for ADC and DAC Linearity Testing

Mario Savino

2008

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Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results

Mark Maddox

IEEE Journal of Solid-State Circuits, 2018

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Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

Randall L Geiger

IEEE Transactions on Instrumentation and Measurement, 2005

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A low power 12-bit 1MSps SAR ADC with capacitor array network

Murod Kurbanov

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SAR ADC Algorithm with Redundancy and Digital Error Correction

Haruo Kobayashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2010

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A high energy-efficiency and low-area switching scheme for SAR ADCs

Mohammad Sharifkhani

Analog Integrated Circuits and Signal Processing, 2020

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A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Randall L Geiger

IEEE Transactions on Instrumentation and Measurement, 2006

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A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS

Andrea Bonfanti

Analog Integrated Circuits and Signal Processing, 2014

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Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL

vimal shukla

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A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry

Dr.Anup Dandapat

Analog Integrated Circuits and Signal Processing, 2019

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A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Shravan Donthula

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A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS

Mark Maddox

2017 Symposium on VLSI Circuits, 2017

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