Sikha Mishra - Academia.edu (original) (raw)

Papers by Sikha Mishra

2023 International Conference in Advances in Power, Signal, and Information Technology (APSIT)

2021 Devices for Integrated Circuit (DevIC), 2021

In this paper, a dielectric modulated hetero channel (InP/InGaAs/InP) MOSFET with source-side cav... more In this paper, a dielectric modulated hetero channel (InP/InGaAs/InP) MOSFET with source-side cavity (DM-H-SC) biosensor is presented for identification of biomolecules like uricase, streptavidin, Ferro-cytochrome, and Protein. In the proposed structure, neutral biomolecules are simulated with their respective dielectric constants but charged biomolecules are simulated with both dielectric constant and charge density. Numerous electrical features such as surface potential, electric field, threshold voltage, and sensitivity of the proposed device have been estimated using the 2D TCAD platform. The highest sensitivity of 0.52 is realized for protein in comparison to uricase, streptavidin, Ferro-cytochrome. Again, a low peak electric field of 0.9× 106 V/cm is obtained at the drain end for protein as compared to other biomolecules.

2022 IEEE VLSI Device Circuit and System (VLSI DCS)

The demand of users increases day by day in context of wireless communication. The current resear... more The demand of users increases day by day in context of wireless communication. The current research emphasizes on many factors such as data rate, type of modulation, and characteristics of the channel. Out of all the factors, channel estimation is the interest in this work. In this paper, the channel estimation based on MIMO-OFDM has been performed. The multiple-input multiple-output(MIMO) system is developed using multiple antennas, where the Space Time Block Coding(STBC), has been tested over Rayleigh's flat fading channel. The concept for wireless communication using MIMO-OFDM has been considered and tested step-bystep. The noise analysis, Bit Error Rate (BER), Symbol Error Rate (SER) has been evaluated. The comparison result of Least Square (LS) method and Minimum Mean Square Error (MMSE) method shows the performance for slow fading environment, that leads the further improvement.

IETE Technical Review, 2021

Transactions on Electrical and Electronic Materials, May 24, 2021

A dielectric modulation (DM) highly sensitive InP/InGaAs/InP hetero channel dual material double ... more A dielectric modulation (DM) highly sensitive InP/InGaAs/InP hetero channel dual material double gate MOSFET (H-DMDG MOSFET) is designed and simulated for accurate identification of the bio-targets such as protein, streptavidin, uricase, biotin, APTES, and Keratin. Group III–V based materials are considered for biosensor design for its chemical inertness, high temperature/power ability, and high carrier velocity. Nanogap cavity is incorporated near the source and drain ends within the gate dielectric for sensing the neutral and charged analytes. The simulated parameters of the proposed structure are analyzed by varying dielectric constant and the charge density of the biomolecules. The influence of both the biomolecules on the electrical features like surface potential, drain current, electric field, and sensitivity have been examined. The highest sensitivity of 0.513 and a lower electric field of 1.98 × 106 V/cm is attained at the drain end for K = 8 as compared to other biomolecules.

ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management, 2019

A hot-carrier-reliability assessment of Silicon on Insulator (SOI) based multi-layer rectangular ... more A hot-carrier-reliability assessment of Silicon on Insulator (SOI) based multi-layer rectangular groove gate silicon on insulator (MLRGG-SOI) MOSFET has been done using Sentaurus TCAD simulator. The architecture integrates the merits of SOI and the recessed channel (RC) technique in to a conventional MOSFET. Further, the impact of structural design parameters and stack gate architecture are analyzed on the behavior of (rectangular groove gate silicon on insulator) RGG-SOI MOSFET. By using Poisson’s equation a compact equation for threshold voltage in terms of minimum surface potential has been developed. For device validation few results of MLRGG-SOI structure are estimated with conventional RGG-SOI structure. The comparison interprets that the proposed architecture provides an improved analog performance with enhanced short channel effects (SCEs).

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020

In the nanoscale regime circuit and device performance degrades due to the presence of parasitic ... more In the nanoscale regime circuit and device performance degrades due to the presence of parasitic capacitance. In the case of scaled devices, short channel effects (SCEs) are substantially reduced by using gate underlap at source and drain side with a significant reduction of drain current. Again, the implementation of the spacer on either side of the gate region helps to realize better drain current with a substantial increase in parasitic capacitance (Cgg), which deteriorates the device performance. In order to overcome these drawbacks, a corner spacer (CS) is introduced in double gate heterostructure MOSFET (DG-HMOSFET), which improves the device characteristics with the reduction in parasitic capacitances. The proposed work presents the comparison among spacer (S) and CS on DG-HMOSFET in order to realize the improvement of device parameters. Thus, the incorporation of high-k on CS- DG-HMOSFET shows the reduction in parasitic capacitance in all directions as compared to S-DG-HMOSFET.

Silicon, 2022

Biosensing has found its extensive applications in biological and medical investigations like cli... more Biosensing has found its extensive applications in biological and medical investigations like clinical diagnosis, environmental monitoring, and other analytical tasks. In this work, an InP/InGaAs/InP channel-based double gate MOSFET (H-DG MOSFET) biosensor has been proposed to identify the analytes like streptavidin, biotin, protein, APTES, and Keratin by using the dielectric modulation (DM) method. Being familiar with novel materials, group III-V nanomaterials have been considered for biosensing applications due to their superior and exceptional physical/chemical properties. The hetero channel concept has been incorporated for the improvement of sensitivity and subthreshold performance of the proposed biosensor, which is a function of both dielectric constant (K) and charge at the interface. The influence of neutral and charged biomolecules on the electrical appearances like surface potential, threshold voltage, sensitivity, a current, and subthreshold swing of H-DG MOSFET are examined. The proposed device attains a maximum sensitivity of 0.423 and a subthreshold swing of 198mV/decade for protein biomolecule.

2021 International Conference in Advances in Power, Signal, and Information Technology (APSIT), 2021

A thoughtful analysis of an innovative stepped asymmetric stack gate structure with graded workfu... more A thoughtful analysis of an innovative stepped asymmetric stack gate structure with graded workfunction has been assembled for rectangular trenched gate (SAS-GWRTG) silicon on insulator (SOI) MOSFET on TCAD device simulator. A compact model for the proposed structure has been formulated by solving the Poisson's equation. This structure takes advantage of the recessed channel to enhance the short channel effects (SCEs) and stepped stack gate at the drain side to improve the hot carrier effect. Further with graded work-function at the source side gate provides an enhanced device analog performance. The influence of negative junction depth (NJD) is explored on the sub-threshold parameters to achieve an optimized device performance. Investigation reveals the enhanced performance manifested by the proposed structure with better switching behaviour, high immunity to SCEs, and increased carrier transportation efficiency. So, this meaningful research is relatively beneficial for nano-scaled short channel devices.

2021 International Conference in Advances in Power, Signal, and Information Technology (APSIT), 2021

Advances in Natural Sciences: Nanoscience and Nanotechnology, 2021

In this work, the performance of dielectric modulated InP/InGaAs/InP based on the hetero channel ... more In this work, the performance of dielectric modulated InP/InGaAs/InP based on the hetero channel dual material double gate MOSFET (DM-H-DMDG MOSFET) for the label-free electrical identification of bio-targets has been inspected with the help of a 2D TCAD device simulator. The impact of bio-target’s location and their fill factor position has been analysed to observe the device sensitivity. Under the dry situation, the effect of charged and non-charged biomolecules on the electrical features such as threshold voltage, electric field, drain current, subthreshold performance, and sensitivity of DM-H-DMDG MOSFET has been evaluated. Simulation results show that the threshold voltage sensitivity of the proposed device is 0.62 and 0.59 when the fill factor is 100% and 50% respectively. The peak value of an electric field is 4.2 × 106 V cm−1 and 4.5 × 106 V cm−1 respectively near the source end and 0.5 × 105 V cm−1 and 5.5 × 105 V cm−1 near the drain end, when positively/negatively charged biomolecules are immobilised in the cavity. Again, the threshold voltage of the device is obtained as 0.265 V/0.245 V when the fill factor is 100% and 50% respectively.

2021 Devices for Integrated Circuit (DevIC), 2021

This paper presents a silicon-based grooved multi-layered gate architecture with air as buried ox... more This paper presents a silicon-based grooved multi-layered gate architecture with air as buried oxide layer to improve the self-heating effect (SHE) and also capable of enhancing the short channel effects (SCEs). This structure takes the benefit of the trenched stack gate to decrease the hot carrier effect (HCE) and linearly varied work-function along the gate region to enhance the carrier transport efficiency. An analytical model is formulated for the presented graded work-function (GW) trenched rectangular stacked gate (TRSG) silicon on nothing (SON) MOSFET and validated through TCAD device simulator. The proposed device performances are upgraded with its physical parameters like negative junction depth (NJD). The performance parameters of GW-TRSG SON MOSFET are compared with trenched rectangular gate (TRG) silicon on insulator (SOI) MOSFET in terms of sub-threshold parameters, electron mobility, and higher-order trans-conductance for better linearity and proficiency.

2019 Devices for Integrated Circuit (DevIC), 2019

This work reports a new grooved gate silicon-on-insulator (GG-SOI) MOSFET with multi-layered (SiO... more This work reports a new grooved gate silicon-on-insulator (GG-SOI) MOSFET with multi-layered (SiO2/Si3N4/SiO2) buried insulator structure to reduce self-heating effect (SHE). The proposed model is simulated using the Sentaurus TCAD simulator. As the thermal conductivity of SiO2/Si3N4/SiO2 buried insulator is higher than SiO2 buried layer, this innovative grooved gate SOI model is able to reduce the self-heating effect of the conventional GG-SOI MOSFET. Thus appropriate for high temperature solicitations. Performance comparison has been done between the multi-layer-buried recessed channel SOI and conventional SiO2 based GG-SOI MOSFET. The presented structure has well controlled the device temperature against the low thermal conductivity of conventional GG-SOI MOSFET. Further step gate concept is used for the improvement of analog performance and short channel effects (SCEs). Simulation results reveal the enhanced performance manifested by the proposed structure in terms of increased drain current, reduced device temperature and increased electron mobility.

ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management, 2019

Double Gate Metal Oxide Semiconductor Field Effect Transistors (DGMOSFET) have one of the emerged... more Double Gate Metal Oxide Semiconductor Field Effect Transistors (DGMOSFET) have one of the emerged potential contenders in CMOS VLSI technology due to the fast switching applications. In this proposed work the implementation of symmetrical work function variation of the dual material (SWVDM) at the source end of In0.53Ga0.47As/InP DG MOSFET using 2D Sentaurus TCAD device simulator. The high-K HfO2 is used in order to minimize the leakage. Simulation result reveals the excellent analog performance metrics like drive current, On resistance, and transconductance as compared to single material (SM) In0.53Ga0.47As/InP DG hetero MOSFET.

2017 Devices for Integrated Circuit (DevIC), 2017

In this work, a two dimensional (2D) Rectangular recessed channel (RRC) metal oxide field effect ... more In this work, a two dimensional (2D) Rectangular recessed channel (RRC) metal oxide field effect transistor using silicon on insulator (SOI) is designed and simulated using ATLAS 2D device simulator. The effect of RRC-SOI on analog (DC) and radio frequency (RF) parameter is investigated and the significance of this device over RRC MOSFET about short channel effect (SCE) is analyzed.

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020

A thoughtful analysis of a rectangular grooved stepped gate Silicon-on-nothing (RGSG-SON) MOSFET ... more A thoughtful analysis of a rectangular grooved stepped gate Silicon-on-nothing (RGSG-SON) MOSFET using TCAD simulator to control the short channel effects (SCEs) is presented in this paper. An evaluation has been performed between SOI and SON grooved gate MOS structures to realize the capability of the proposed structure. The exploration revealed that RGSG-SON MOSFET is more proficient as compared to grooved gate silicon on insulator (SOI) MOS structure with respect to sub-threshold performance and immunity to SCEs. Further the amalgamation of higher thermal conductivity such as air in the buried layer, the proposed structure can suppress the self- heating effect. So this thoughtful exploration is comparatively valuable to investigate the performance development of grooved gate SON over SOI for nano scaled MOSFET.

International Journal of Scientific & Technology Research, 2020

In this work the impact of spacer in InGaAs/InP hetero stepped double gate MOS transistor is inve... more In this work the impact of spacer in InGaAs/InP hetero stepped double gate MOS transistor is investigated by a 2D TCAD device simulator. To minimize the short channel effects (SCEs), under lap technique is used symmetrically in either side of the gate. However, it considerably decreases the On current due to enhanced channel resistance. Thus the spacers on under lap region are one of the solutions to overwhelm these problems. Therefore, difficulties associated with conventional under lap DG MOSFET can be eliminated with significant improvement in On current and intrinsic gain. Further, to reduce the punch-through effect, stepped gate concept is integrated in the double gate MOSFET to attain a better control on the channel carriers that eventually reduces the leakage current. So this paper presents a comparison made between symmetric spacer underlap hetero stepped double gate (SSUHS-DG) MOSFET and hetero stepped double gate (HS-DG) MOSFET; so far SSUHS-DG MOSFET offers better device ...

2023 International Conference in Advances in Power, Signal, and Information Technology (APSIT)

2021 Devices for Integrated Circuit (DevIC), 2021

In this paper, a dielectric modulated hetero channel (InP/InGaAs/InP) MOSFET with source-side cav... more In this paper, a dielectric modulated hetero channel (InP/InGaAs/InP) MOSFET with source-side cavity (DM-H-SC) biosensor is presented for identification of biomolecules like uricase, streptavidin, Ferro-cytochrome, and Protein. In the proposed structure, neutral biomolecules are simulated with their respective dielectric constants but charged biomolecules are simulated with both dielectric constant and charge density. Numerous electrical features such as surface potential, electric field, threshold voltage, and sensitivity of the proposed device have been estimated using the 2D TCAD platform. The highest sensitivity of 0.52 is realized for protein in comparison to uricase, streptavidin, Ferro-cytochrome. Again, a low peak electric field of 0.9× 106 V/cm is obtained at the drain end for protein as compared to other biomolecules.

2022 IEEE VLSI Device Circuit and System (VLSI DCS)

The demand of users increases day by day in context of wireless communication. The current resear... more The demand of users increases day by day in context of wireless communication. The current research emphasizes on many factors such as data rate, type of modulation, and characteristics of the channel. Out of all the factors, channel estimation is the interest in this work. In this paper, the channel estimation based on MIMO-OFDM has been performed. The multiple-input multiple-output(MIMO) system is developed using multiple antennas, where the Space Time Block Coding(STBC), has been tested over Rayleigh's flat fading channel. The concept for wireless communication using MIMO-OFDM has been considered and tested step-bystep. The noise analysis, Bit Error Rate (BER), Symbol Error Rate (SER) has been evaluated. The comparison result of Least Square (LS) method and Minimum Mean Square Error (MMSE) method shows the performance for slow fading environment, that leads the further improvement.

IETE Technical Review, 2021

Transactions on Electrical and Electronic Materials, May 24, 2021

A dielectric modulation (DM) highly sensitive InP/InGaAs/InP hetero channel dual material double ... more A dielectric modulation (DM) highly sensitive InP/InGaAs/InP hetero channel dual material double gate MOSFET (H-DMDG MOSFET) is designed and simulated for accurate identification of the bio-targets such as protein, streptavidin, uricase, biotin, APTES, and Keratin. Group III–V based materials are considered for biosensor design for its chemical inertness, high temperature/power ability, and high carrier velocity. Nanogap cavity is incorporated near the source and drain ends within the gate dielectric for sensing the neutral and charged analytes. The simulated parameters of the proposed structure are analyzed by varying dielectric constant and the charge density of the biomolecules. The influence of both the biomolecules on the electrical features like surface potential, drain current, electric field, and sensitivity have been examined. The highest sensitivity of 0.513 and a lower electric field of 1.98 × 106 V/cm is attained at the drain end for K = 8 as compared to other biomolecules.

ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management, 2019

A hot-carrier-reliability assessment of Silicon on Insulator (SOI) based multi-layer rectangular ... more A hot-carrier-reliability assessment of Silicon on Insulator (SOI) based multi-layer rectangular groove gate silicon on insulator (MLRGG-SOI) MOSFET has been done using Sentaurus TCAD simulator. The architecture integrates the merits of SOI and the recessed channel (RC) technique in to a conventional MOSFET. Further, the impact of structural design parameters and stack gate architecture are analyzed on the behavior of (rectangular groove gate silicon on insulator) RGG-SOI MOSFET. By using Poisson’s equation a compact equation for threshold voltage in terms of minimum surface potential has been developed. For device validation few results of MLRGG-SOI structure are estimated with conventional RGG-SOI structure. The comparison interprets that the proposed architecture provides an improved analog performance with enhanced short channel effects (SCEs).

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020

In the nanoscale regime circuit and device performance degrades due to the presence of parasitic ... more In the nanoscale regime circuit and device performance degrades due to the presence of parasitic capacitance. In the case of scaled devices, short channel effects (SCEs) are substantially reduced by using gate underlap at source and drain side with a significant reduction of drain current. Again, the implementation of the spacer on either side of the gate region helps to realize better drain current with a substantial increase in parasitic capacitance (Cgg), which deteriorates the device performance. In order to overcome these drawbacks, a corner spacer (CS) is introduced in double gate heterostructure MOSFET (DG-HMOSFET), which improves the device characteristics with the reduction in parasitic capacitances. The proposed work presents the comparison among spacer (S) and CS on DG-HMOSFET in order to realize the improvement of device parameters. Thus, the incorporation of high-k on CS- DG-HMOSFET shows the reduction in parasitic capacitance in all directions as compared to S-DG-HMOSFET.

Silicon, 2022

Biosensing has found its extensive applications in biological and medical investigations like cli... more Biosensing has found its extensive applications in biological and medical investigations like clinical diagnosis, environmental monitoring, and other analytical tasks. In this work, an InP/InGaAs/InP channel-based double gate MOSFET (H-DG MOSFET) biosensor has been proposed to identify the analytes like streptavidin, biotin, protein, APTES, and Keratin by using the dielectric modulation (DM) method. Being familiar with novel materials, group III-V nanomaterials have been considered for biosensing applications due to their superior and exceptional physical/chemical properties. The hetero channel concept has been incorporated for the improvement of sensitivity and subthreshold performance of the proposed biosensor, which is a function of both dielectric constant (K) and charge at the interface. The influence of neutral and charged biomolecules on the electrical appearances like surface potential, threshold voltage, sensitivity, a current, and subthreshold swing of H-DG MOSFET are examined. The proposed device attains a maximum sensitivity of 0.423 and a subthreshold swing of 198mV/decade for protein biomolecule.

2021 International Conference in Advances in Power, Signal, and Information Technology (APSIT), 2021

A thoughtful analysis of an innovative stepped asymmetric stack gate structure with graded workfu... more A thoughtful analysis of an innovative stepped asymmetric stack gate structure with graded workfunction has been assembled for rectangular trenched gate (SAS-GWRTG) silicon on insulator (SOI) MOSFET on TCAD device simulator. A compact model for the proposed structure has been formulated by solving the Poisson's equation. This structure takes advantage of the recessed channel to enhance the short channel effects (SCEs) and stepped stack gate at the drain side to improve the hot carrier effect. Further with graded work-function at the source side gate provides an enhanced device analog performance. The influence of negative junction depth (NJD) is explored on the sub-threshold parameters to achieve an optimized device performance. Investigation reveals the enhanced performance manifested by the proposed structure with better switching behaviour, high immunity to SCEs, and increased carrier transportation efficiency. So, this meaningful research is relatively beneficial for nano-scaled short channel devices.

2021 International Conference in Advances in Power, Signal, and Information Technology (APSIT), 2021

Advances in Natural Sciences: Nanoscience and Nanotechnology, 2021

In this work, the performance of dielectric modulated InP/InGaAs/InP based on the hetero channel ... more In this work, the performance of dielectric modulated InP/InGaAs/InP based on the hetero channel dual material double gate MOSFET (DM-H-DMDG MOSFET) for the label-free electrical identification of bio-targets has been inspected with the help of a 2D TCAD device simulator. The impact of bio-target’s location and their fill factor position has been analysed to observe the device sensitivity. Under the dry situation, the effect of charged and non-charged biomolecules on the electrical features such as threshold voltage, electric field, drain current, subthreshold performance, and sensitivity of DM-H-DMDG MOSFET has been evaluated. Simulation results show that the threshold voltage sensitivity of the proposed device is 0.62 and 0.59 when the fill factor is 100% and 50% respectively. The peak value of an electric field is 4.2 × 106 V cm−1 and 4.5 × 106 V cm−1 respectively near the source end and 0.5 × 105 V cm−1 and 5.5 × 105 V cm−1 near the drain end, when positively/negatively charged biomolecules are immobilised in the cavity. Again, the threshold voltage of the device is obtained as 0.265 V/0.245 V when the fill factor is 100% and 50% respectively.

2021 Devices for Integrated Circuit (DevIC), 2021

This paper presents a silicon-based grooved multi-layered gate architecture with air as buried ox... more This paper presents a silicon-based grooved multi-layered gate architecture with air as buried oxide layer to improve the self-heating effect (SHE) and also capable of enhancing the short channel effects (SCEs). This structure takes the benefit of the trenched stack gate to decrease the hot carrier effect (HCE) and linearly varied work-function along the gate region to enhance the carrier transport efficiency. An analytical model is formulated for the presented graded work-function (GW) trenched rectangular stacked gate (TRSG) silicon on nothing (SON) MOSFET and validated through TCAD device simulator. The proposed device performances are upgraded with its physical parameters like negative junction depth (NJD). The performance parameters of GW-TRSG SON MOSFET are compared with trenched rectangular gate (TRG) silicon on insulator (SOI) MOSFET in terms of sub-threshold parameters, electron mobility, and higher-order trans-conductance for better linearity and proficiency.

2019 Devices for Integrated Circuit (DevIC), 2019

This work reports a new grooved gate silicon-on-insulator (GG-SOI) MOSFET with multi-layered (SiO... more This work reports a new grooved gate silicon-on-insulator (GG-SOI) MOSFET with multi-layered (SiO2/Si3N4/SiO2) buried insulator structure to reduce self-heating effect (SHE). The proposed model is simulated using the Sentaurus TCAD simulator. As the thermal conductivity of SiO2/Si3N4/SiO2 buried insulator is higher than SiO2 buried layer, this innovative grooved gate SOI model is able to reduce the self-heating effect of the conventional GG-SOI MOSFET. Thus appropriate for high temperature solicitations. Performance comparison has been done between the multi-layer-buried recessed channel SOI and conventional SiO2 based GG-SOI MOSFET. The presented structure has well controlled the device temperature against the low thermal conductivity of conventional GG-SOI MOSFET. Further step gate concept is used for the improvement of analog performance and short channel effects (SCEs). Simulation results reveal the enhanced performance manifested by the proposed structure in terms of increased drain current, reduced device temperature and increased electron mobility.

ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management, 2019

Double Gate Metal Oxide Semiconductor Field Effect Transistors (DGMOSFET) have one of the emerged... more Double Gate Metal Oxide Semiconductor Field Effect Transistors (DGMOSFET) have one of the emerged potential contenders in CMOS VLSI technology due to the fast switching applications. In this proposed work the implementation of symmetrical work function variation of the dual material (SWVDM) at the source end of In0.53Ga0.47As/InP DG MOSFET using 2D Sentaurus TCAD device simulator. The high-K HfO2 is used in order to minimize the leakage. Simulation result reveals the excellent analog performance metrics like drive current, On resistance, and transconductance as compared to single material (SM) In0.53Ga0.47As/InP DG hetero MOSFET.

2017 Devices for Integrated Circuit (DevIC), 2017

In this work, a two dimensional (2D) Rectangular recessed channel (RRC) metal oxide field effect ... more In this work, a two dimensional (2D) Rectangular recessed channel (RRC) metal oxide field effect transistor using silicon on insulator (SOI) is designed and simulated using ATLAS 2D device simulator. The effect of RRC-SOI on analog (DC) and radio frequency (RF) parameter is investigated and the significance of this device over RRC MOSFET about short channel effect (SCE) is analyzed.

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020

A thoughtful analysis of a rectangular grooved stepped gate Silicon-on-nothing (RGSG-SON) MOSFET ... more A thoughtful analysis of a rectangular grooved stepped gate Silicon-on-nothing (RGSG-SON) MOSFET using TCAD simulator to control the short channel effects (SCEs) is presented in this paper. An evaluation has been performed between SOI and SON grooved gate MOS structures to realize the capability of the proposed structure. The exploration revealed that RGSG-SON MOSFET is more proficient as compared to grooved gate silicon on insulator (SOI) MOS structure with respect to sub-threshold performance and immunity to SCEs. Further the amalgamation of higher thermal conductivity such as air in the buried layer, the proposed structure can suppress the self- heating effect. So this thoughtful exploration is comparatively valuable to investigate the performance development of grooved gate SON over SOI for nano scaled MOSFET.

International Journal of Scientific & Technology Research, 2020

In this work the impact of spacer in InGaAs/InP hetero stepped double gate MOS transistor is inve... more In this work the impact of spacer in InGaAs/InP hetero stepped double gate MOS transistor is investigated by a 2D TCAD device simulator. To minimize the short channel effects (SCEs), under lap technique is used symmetrically in either side of the gate. However, it considerably decreases the On current due to enhanced channel resistance. Thus the spacers on under lap region are one of the solutions to overwhelm these problems. Therefore, difficulties associated with conventional under lap DG MOSFET can be eliminated with significant improvement in On current and intrinsic gain. Further, to reduce the punch-through effect, stepped gate concept is integrated in the double gate MOSFET to attain a better control on the channel carriers that eventually reduces the leakage current. So this paper presents a comparison made between symmetric spacer underlap hetero stepped double gate (SSUHS-DG) MOSFET and hetero stepped double gate (HS-DG) MOSFET; so far SSUHS-DG MOSFET offers better device ...