nader pakdaman - Academia.edu (original) (raw)
Papers by nader pakdaman
International Symposium for Testing and Failure Analysis, 2002
Dynamic hot-electron emission using time-resolved photon counting can address the long-term failu... more Dynamic hot-electron emission using time-resolved photon counting can address the long-term failure analysis and debug requirements of the semiconductor industry's advanced devices. This article identifies the detector performance parameters and components that are required to scale and keep pace with the industry's requirements. It addresses the scalability of dynamic emission with the semiconductor advanced device roadmap. It is important to understand the limitations to determining that a switching event has occurred. The article explains the criteria for event detection, which is suitable for tracking signal propagation and looking for logic or other faults in which timing is not critical. It discusses conditions for event timing, whose goal is to determine accurately when a switching event has occurred, usually for speed path analysis. One of the uses of a dynamic emission system is to identify faults by studying the emission as a general function of time.
<jats:title>Abstract</jats:title> <jats:p>Time-resolved photon emission has bee... more <jats:title>Abstract</jats:title> <jats:p>Time-resolved photon emission has been shown to be useful in analyzing clock skews and timing-related defects in flip-chip devices. In practice, time-resolved photon emission using the S-25 Quantar detector cannot be used at long loop lengths (typically &gt;10 μs). This paper discusses a near-infrared (NIR) optimized time-resolved emission system to demonstrate that even with long loop lengths time-resolved photon emission can be extremely useful for defect localization. Specifically, it describes time-resolved photon emission system, and shows how time-resolved photon emission was used to solve two different issues that caused scan fails on silicon-on-insulator devices, and briefly discusses the interpretation of optical waveforms. The two issues are presented as case studies.</jats:p>
Metrology, Inspection, and Process Control for Microlithography XXVII, 2013
We report a strong direct correlation (above 0.9) between conventional transistor-level parametri... more We report a strong direct correlation (above 0.9) between conventional transistor-level parametrics typically used in the industry to monitor and control intra-die variability (IDV) and a novel, non-contact performance-based metrology (PBM), technology that was integrated into an active die on a 32nm SOI advanced logic product platform. We demonstrate a PBM test structure measurement repeatability of less than 0.4%. In this work, we also demonstrate the compatibility of integrating the PBM technology into an advanced CMOS process flow with no added processing or steps, as well as its footprint scalability. The data suggests that the non-contact PBM technology meets all prerequisites for its deployment as a standard, within-product IDV monitor.
The 17th Annual SEMI/IEEE ASMC 2006 Conference, 2006
2009 IEEE International Conference on Microelectronic Test Structures, 2009
... These features enable accelerated yield ramp, maintain high productivity, and reduce costs. R... more ... These features enable accelerated yield ramp, maintain high productivity, and reduce costs. References [1] Duane S. Boning, Karthik Balakrishnan, Hong Cai ... 50, no. 4/5, pp. 451-468, 2006. [5] Kelin J. Kuhn, Chris Kenyon, Avner Kornfeld, Mark Liu, Atul Maheshwari, Wei-kai Shih ...
With the proliferation of flip chip packaging and multiple metal layer technology in advanced sem... more With the proliferation of flip chip packaging and multiple metal layer technology in advanced semiconductor integrated circuits (IC’s), traditional front-side probing and failure analysis tools are no longer viable. Full transistor level access from the substrate side (i.e., backside) of the chip is now required to fully realize such investigative work. Silicon is transmissive in the near-IR above its bandgap (≅ 1,000nm to 1,100nm). As a result, transistor level access can be achieved by optical means. To enable such optical access, it is necessary to first remove all heat dissipating devices such as finned heat sinks and integrated heat spreaders placed in contact with the silicon substrate. For most applications, the silicon is then mechanically thinned down to approximately 100μm, and a microscope objective is used to “probe” the chip optically for diagnostics and failure analysis. During such diagnostics and failure analysis, the device under test (DUT) is electrically exercised...
Metrology, Inspection, and Process Control for Microlithography XXIII, 2009
ABSTRACT We report on a performance-based measurement (PBM) technique from a volume production 65... more ABSTRACT We report on a performance-based measurement (PBM) technique from a volume production 65-nm multi-product wafer (MPW) process that shows far more sensitivity than the standard physical gate-length (CD) measurements. The performance (the electrical "effective" gate length, Leff) variation results measured by PBM can NOT be explained alone by CD (physical gate) measurement and show that the non-destructive (non-contact) PBM is able to monitor and control at first-level of electrical connectivity (>= M1), the bin-yield determining in-die variation that are NOT captured or realized by physical CD measurement. Along with this higher sensitivity, we also show that the process-induced variation (excursion) has a distinct signature versus "nominal" expected behavior.
International Symposium for Testing and Failure Analysis, 2002
Dynamic hot-electron emission using time-resolved photon counting can address the long-term failu... more Dynamic hot-electron emission using time-resolved photon counting can address the long-term failure analysis and debug requirements of the semiconductor industry's advanced devices. This article identifies the detector performance parameters and components that are required to scale and keep pace with the industry's requirements. It addresses the scalability of dynamic emission with the semiconductor advanced device roadmap. It is important to understand the limitations to determining that a switching event has occurred. The article explains the criteria for event detection, which is suitable for tracking signal propagation and looking for logic or other faults in which timing is not critical. It discusses conditions for event timing, whose goal is to determine accurately when a switching event has occurred, usually for speed path analysis. One of the uses of a dynamic emission system is to identify faults by studying the emission as a general function of time.
<jats:title>Abstract</jats:title> <jats:p>Time-resolved photon emission has bee... more <jats:title>Abstract</jats:title> <jats:p>Time-resolved photon emission has been shown to be useful in analyzing clock skews and timing-related defects in flip-chip devices. In practice, time-resolved photon emission using the S-25 Quantar detector cannot be used at long loop lengths (typically &gt;10 μs). This paper discusses a near-infrared (NIR) optimized time-resolved emission system to demonstrate that even with long loop lengths time-resolved photon emission can be extremely useful for defect localization. Specifically, it describes time-resolved photon emission system, and shows how time-resolved photon emission was used to solve two different issues that caused scan fails on silicon-on-insulator devices, and briefly discusses the interpretation of optical waveforms. The two issues are presented as case studies.</jats:p>
Metrology, Inspection, and Process Control for Microlithography XXVII, 2013
We report a strong direct correlation (above 0.9) between conventional transistor-level parametri... more We report a strong direct correlation (above 0.9) between conventional transistor-level parametrics typically used in the industry to monitor and control intra-die variability (IDV) and a novel, non-contact performance-based metrology (PBM), technology that was integrated into an active die on a 32nm SOI advanced logic product platform. We demonstrate a PBM test structure measurement repeatability of less than 0.4%. In this work, we also demonstrate the compatibility of integrating the PBM technology into an advanced CMOS process flow with no added processing or steps, as well as its footprint scalability. The data suggests that the non-contact PBM technology meets all prerequisites for its deployment as a standard, within-product IDV monitor.
The 17th Annual SEMI/IEEE ASMC 2006 Conference, 2006
2009 IEEE International Conference on Microelectronic Test Structures, 2009
... These features enable accelerated yield ramp, maintain high productivity, and reduce costs. R... more ... These features enable accelerated yield ramp, maintain high productivity, and reduce costs. References [1] Duane S. Boning, Karthik Balakrishnan, Hong Cai ... 50, no. 4/5, pp. 451-468, 2006. [5] Kelin J. Kuhn, Chris Kenyon, Avner Kornfeld, Mark Liu, Atul Maheshwari, Wei-kai Shih ...
With the proliferation of flip chip packaging and multiple metal layer technology in advanced sem... more With the proliferation of flip chip packaging and multiple metal layer technology in advanced semiconductor integrated circuits (IC’s), traditional front-side probing and failure analysis tools are no longer viable. Full transistor level access from the substrate side (i.e., backside) of the chip is now required to fully realize such investigative work. Silicon is transmissive in the near-IR above its bandgap (≅ 1,000nm to 1,100nm). As a result, transistor level access can be achieved by optical means. To enable such optical access, it is necessary to first remove all heat dissipating devices such as finned heat sinks and integrated heat spreaders placed in contact with the silicon substrate. For most applications, the silicon is then mechanically thinned down to approximately 100μm, and a microscope objective is used to “probe” the chip optically for diagnostics and failure analysis. During such diagnostics and failure analysis, the device under test (DUT) is electrically exercised...
Metrology, Inspection, and Process Control for Microlithography XXIII, 2009
ABSTRACT We report on a performance-based measurement (PBM) technique from a volume production 65... more ABSTRACT We report on a performance-based measurement (PBM) technique from a volume production 65-nm multi-product wafer (MPW) process that shows far more sensitivity than the standard physical gate-length (CD) measurements. The performance (the electrical "effective" gate length, Leff) variation results measured by PBM can NOT be explained alone by CD (physical gate) measurement and show that the non-destructive (non-contact) PBM is able to monitor and control at first-level of electrical connectivity (>= M1), the bin-yield determining in-die variation that are NOT captured or realized by physical CD measurement. Along with this higher sensitivity, we also show that the process-induced variation (excursion) has a distinct signature versus "nominal" expected behavior.